From 76aeed376644c2ad0fa4e44217d39b3e3567b323 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Sat, 11 Jul 2009 07:08:13 +0000
Subject: Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r]
 address is feasible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75360 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/ARM/ARMISelDAGToDAG.cpp | 15 +++++----------
 lib/Target/ARM/ARMInstrThumb.td    | 10 ++++++++++
 lib/Target/ARM/README-Thumb.txt    |  9 ---------
 3 files changed, 15 insertions(+), 19 deletions(-)

(limited to 'lib')

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index ce2a170..75e956b 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -454,16 +454,11 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
   // FIXME dl should come from the parent load or store, not the address
   DebugLoc dl = Op.getDebugLoc();
   if (N.getOpcode() != ISD::ADD) {
-    Base = N;
-    // We must materialize a zero in a reg! Returning a constant here
-    // wouldn't work without additional code to position the node within
-    // ISel's topological ordering in a place where ISel will process it
-    // normally.  Instead, just explicitly issue a tMOVri8 node!
-    SDValue CC = CurDAG->getRegister(ARM::CPSR, MVT::i32);
-    SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
-    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
-    SDValue Ops[] = { CC, CurDAG->getTargetConstant(0, MVT::i32), Pred, PredReg };
-    Offset = SDValue(CurDAG->getTargetNode(ARM::tMOVi8, dl, MVT::i32, Ops,4),0);
+    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
+    if (!NC || NC->getZExtValue() != 0)
+      return false;
+
+    Base = Offset = N;
     return true;
   }
 
diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td
index a473a20..f2c5a46 100644
--- a/lib/Target/ARM/ARMInstrThumb.td
+++ b/lib/Target/ARM/ARMInstrThumb.td
@@ -224,10 +224,12 @@ def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
                 "ldrh", " $dst, $addr",
                 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
 
+let AddedComplexity = 10 in
 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
                  "ldrsb", " $dst, $addr",
                  [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
 
+let AddedComplexity = 10 in
 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
                  "ldrsh", " $dst, $addr",
                  [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
@@ -620,6 +622,14 @@ def : T1Pat<(extloadi1  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
 def : T1Pat<(extloadi8  t_addrmode_s1:$addr),  (tLDRB t_addrmode_s1:$addr)>;
 def : T1Pat<(extloadi16 t_addrmode_s2:$addr),  (tLDRH t_addrmode_s2:$addr)>;
 
+// If it's possible to use [r,r] address mode for sextload, select to
+// ldr{b|h} + sxt{b|h} instead.
+def : TPat<(sextloadi8 t_addrmode_s1:$addr),
+           (tSXTB (tLDRB t_addrmode_s1:$addr))>;
+def : TPat<(sextloadi16 t_addrmode_s2:$addr),
+           (tSXTH (tLDRH t_addrmode_s2:$addr))>;
+
+
 // Large immediate handling.
 
 // Two piece imms.
diff --git a/lib/Target/ARM/README-Thumb.txt b/lib/Target/ARM/README-Thumb.txt
index 8ffe0b1..cc01794 100644
--- a/lib/Target/ARM/README-Thumb.txt
+++ b/lib/Target/ARM/README-Thumb.txt
@@ -244,12 +244,3 @@ to toggle the 's' bit since they do not set CPSR when they are inside IT blocks.
 Make use of hi register variants of cmp: tCMPhir / tCMPZhir.
 
 //===---------------------------------------------------------------------===//
-
-Rather than generating ldrsb, sometimes it's better to select to ldrb + sxtb.
-The problem is ldrsb addressing mode [r, r] means the zero offset requires an
-extra move. e.g. ldr_ext.ll test3:
-	movs r1, #0
-	ldrsb r0, [r0, r1]
-=>
-	ldrb	r0, [r0, #0]
-	sxtb	r0, r0
-- 
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