From 8a20844e277d1f51600134589aeb9ca88d9ca25d Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Tue, 19 Feb 2013 03:56:57 +0000 Subject: Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16, BtnezT8SltiX16, BtnezT8SltiuX16 . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175486 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips16InstrInfo.cpp | 17 ++++++++++++++++- lib/Target/Mips/Mips16InstrInfo.td | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index b619439..22cb963 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -132,7 +132,6 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { MachineBasicBlock &MBB = *MI->getParent(); - switch(MI->getDesc().getOpcode()) { default: return false; @@ -146,11 +145,19 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { case Mips::BteqzT8SltX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16); break; + case Mips::BteqzT8SltiX16: + ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16, + Mips::SltiRxImm16, Mips::SltiRxImmX16); + break; case Mips::BteqzT8SltuX16: // TBD: figure out a way to get this or remove the instruction // altogether. ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16); break; + case Mips::BteqzT8SltiuX16: + ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16, + Mips::SltiuRxImm16, Mips::SltiuRxImmX16); + break; case Mips::BtnezT8CmpX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16); break; @@ -161,11 +168,19 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { case Mips::BtnezT8SltX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16); break; + case Mips::BtnezT8SltiX16: + ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16, + Mips::SltiRxImm16, Mips::SltiRxImmX16); + break; case Mips::BtnezT8SltuX16: // TBD: figure out a way to get this or remove the instruction // altogether. ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltuRxRy16); break; + case Mips::BtnezT8SltiuX16: + ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16, + Mips::SltiuRxImm16, Mips::SltiuRxImmX16); + break; case Mips::RetRA16: ExpandRetRA16(MBB, MI, Mips::JrcRa16); break; diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 1a5c30b..0d90df4 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -1012,13 +1012,45 @@ def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; // def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; +// Format: SLTI rx, immediate MIPS16e +// Purpose: Set on Less Than Immediate +// To record the result of a less-than comparison with a constant. +// +// +def SltiRxImm16: FRI16_ins<0b01010, "slti", IIAlu> { + let Defs = [T8]; +} + // // Format: SLTI rx, immediate MIPS16e // Purpose: Set on Less Than Immediate (Extended) // To record the result of a less-than comparison with a constant. // +// +def SltiRxImmX16: FEXT_RI16_ins<0b01010, "slti", IIAlu> { + let Defs = [T8]; +} + def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; +// Format: SLTIU rx, immediate MIPS16e +// Purpose: Set on Less Than Immediate Unsigned +// To record the result of a less-than comparison with a constant. +// +// +def SltiuRxImm16: FRI16_ins<0b01011, "sltiu", IIAlu> { + let Defs = [T8]; +} + +// +// Format: SLTI rx, immediate MIPS16e +// Purpose: Set on Less Than Immediate Unsigned (Extended) +// To record the result of a less-than comparison with a constant. +// +// +def SltiuRxImmX16: FEXT_RI16_ins<0b01011, "sltiu", IIAlu> { + let Defs = [T8]; +} // // Format: SLTIU rx, immediate MIPS16e // Purpose: Set on Less Than Immediate Unsigned (Extended) -- cgit v1.1