From b555609e73f5091bf8180c0875fb1fa6c5ad0e7a Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Wed, 26 May 2010 01:21:14 +0000 Subject: Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMRegisterInfo.td | 119 +++++++++++++++++++++++----- lib/Target/Blackfin/BlackfinRegisterInfo.td | 28 ++++++- lib/Target/MBlaze/MBlazeRegisterInfo.td | 10 ++- lib/Target/MSP430/MSP430RegisterInfo.td | 11 ++- lib/Target/Mips/MipsRegisterInfo.td | 26 ++++-- lib/Target/PowerPC/PPCRegisterInfo.td | 30 ++++--- lib/Target/Sparc/SparcRegisterInfo.td | 6 -- lib/Target/SystemZ/SystemZRegisterInfo.td | 49 +++++++----- lib/Target/X86/X86RegisterInfo.td | 87 ++++++++++++++++---- 9 files changed, 279 insertions(+), 87 deletions(-) (limited to 'lib') diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index f815b0f..982401a 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -86,7 +86,6 @@ def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">; def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">; // Aliases of the F* registers used to hold 64-bit fp values (doubles) -let SubRegIndices = [ssub_0, ssub_1] in { def D0 : ARMReg< 0, "d0", [S0, S1]>; def D1 : ARMReg< 1, "d1", [S2, S3]>; def D2 : ARMReg< 2, "d2", [S4, S5]>; @@ -103,7 +102,6 @@ def D12 : ARMReg<12, "d12", [S24, S25]>; def D13 : ARMReg<13, "d13", [S26, S27]>; def D14 : ARMReg<14, "d14", [S28, S29]>; def D15 : ARMReg<15, "d15", [S30, S31]>; -} // VFP3 defines 16 additional double registers def D16 : ARMFReg<16, "d16">; def D17 : ARMFReg<17, "d17">; @@ -116,9 +114,6 @@ def D28 : ARMFReg<28, "d28">; def D29 : ARMFReg<29, "d29">; def D30 : ARMFReg<30, "d30">; def D31 : ARMFReg<31, "d31">; // Advanced SIMD (NEON) defines 16 quad-word aliases -let SubRegIndices = [dsub_0, dsub_1], - CompositeIndices = [(ssub_2 dsub_1, ssub_0), - (ssub_3 dsub_1, ssub_1)] in { def Q0 : ARMReg< 0, "q0", [D0, D1]>; def Q1 : ARMReg< 1, "q1", [D2, D3]>; def Q2 : ARMReg< 2, "q2", [D4, D5]>; @@ -127,8 +122,6 @@ def Q4 : ARMReg< 4, "q4", [D8, D9]>; def Q5 : ARMReg< 5, "q5", [D10, D11]>; def Q6 : ARMReg< 6, "q6", [D12, D13]>; def Q7 : ARMReg< 7, "q7", [D14, D15]>; -} -let SubRegIndices = [dsub_0, dsub_1] in { def Q8 : ARMReg< 8, "q8", [D16, D17]>; def Q9 : ARMReg< 9, "q9", [D18, D19]>; def Q10 : ARMReg<10, "q10", [D20, D21]>; @@ -137,7 +130,6 @@ def Q12 : ARMReg<12, "q12", [D24, D25]>; def Q13 : ARMReg<13, "q13", [D26, D27]>; def Q14 : ARMReg<14, "q14", [D28, D29]>; def Q15 : ARMReg<15, "q15", [D30, D31]>; -} // Pseudo 256-bit registers to represent pairs of Q registers. These should // never be present in the emitted code. @@ -146,9 +138,6 @@ def Q15 : ARMReg<15, "q15", [D30, D31]>; // starting D register number doesn't have to be multiple of 4. e.g. // D1, D2, D3, D4 would be a legal quad. But that would make the sub-register // stuffs very messy. -let SubRegIndices = [qsub_0, qsub_1], - CompositeIndices = [(dsub_2 qsub_1, dsub_0), - (dsub_3 qsub_1, dsub_1)] in { def QQ0 : ARMReg<0, "qq0", [Q0, Q1]>; def QQ1 : ARMReg<1, "qq1", [Q2, Q3]>; def QQ2 : ARMReg<2, "qq2", [Q4, Q5]>; @@ -157,21 +146,12 @@ def QQ4 : ARMReg<4, "qq4", [Q8, Q9]>; def QQ5 : ARMReg<5, "qq5", [Q10, Q11]>; def QQ6 : ARMReg<6, "qq6", [Q12, Q13]>; def QQ7 : ARMReg<7, "qq7", [Q14, Q15]>; -} // Pseudo 512-bit registers to represent four consecutive Q registers. -let SubRegIndices = [qqsub_0, qqsub_1], - CompositeIndices = [(qsub_2 qqsub_1, qsub_0), - (qsub_3 qqsub_1, qsub_1), - (dsub_4 qqsub_1, dsub_0), - (dsub_5 qqsub_1, dsub_1), - (dsub_6 qqsub_1, dsub_2), - (dsub_7 qqsub_1, dsub_3)] in { def QQQQ0 : ARMReg<0, "qqqq0", [QQ0, QQ1]>; def QQQQ1 : ARMReg<1, "qqqq1", [QQ2, QQ3]>; def QQQQ2 : ARMReg<2, "qqqq2", [QQ4, QQ5]>; def QQQQ3 : ARMReg<3, "qqqq3", [QQ6, QQ7]>; -} // Current Program Status Register. def CPSR : ARMReg<0, "cpsr">; @@ -458,3 +438,102 @@ def QQQQPR : RegisterClass<"ARM", [v8i64], // Condition code registers. def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; +//===----------------------------------------------------------------------===// +// Subregister Set Definitions... now that we have all of the pieces, define the +// sub registers for each register. +// + +// S sub-registers of D registers. +def : SubRegSet; +def : SubRegSet; + +// S sub-registers of Q registers. +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; + +// D sub-registers of Q registers. +def : SubRegSet; +def : SubRegSet; + +// S sub-registers of QQ registers. Note there are no sub-indices +// for referencing S4 - S7, S12 - S15, and S20 - S23. It doesn't +// look like we need them. +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; + +// D sub-registers of QQ registers. +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; + +// Q sub-registers of QQ registers. +def : SubRegSet; +def : SubRegSet; + + +// D sub-registers of QQQQ registers. +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; + +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; + +// Q sub-registers of QQQQ registers. +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; + +// QQ sub-registers of QQQQ registers. +def : SubRegSet; +def : SubRegSet; + diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.td b/lib/Target/Blackfin/BlackfinRegisterInfo.td index e1cfae9..8379ce7 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.td +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.td @@ -19,7 +19,6 @@ let Namespace = "BF" in { def lo16 : SubRegIndex; def hi16 : SubRegIndex; def lo32 : SubRegIndex; -def hi32 : SubRegIndex; } // Registers are identified with 3-bit group and 3-bit ID numbers. @@ -50,7 +49,6 @@ class Ri group, bits<3> num, string n> : BlackfinReg { // Ra 40-bit accumulator registers class Ra num, string n, list subs> : BlackfinReg { let SubRegs = subs; - let SubRegIndices = [hi32, lo32]; let Group = 4; let Num = num; } @@ -65,7 +63,6 @@ multiclass Rss group, bits<3> num, string n> { class Rii group, bits<3> num, string n, list subs> : BlackfinReg { let SubRegs = subs; - let SubRegIndices = [hi16, lo16]; let Group = group; let Num = num; } @@ -176,7 +173,7 @@ def RETN : Ri<7, 5, "retn">, DwarfRegNum<[38]>; def RETE : Ri<7, 6, "rete">, DwarfRegNum<[39]>; def ASTAT : Ri<4, 6, "astat">, DwarfRegNum<[40]> { - let Aliases = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS]; + let SubRegs = [AZ, AN, CC, NCC, AQ, AC0, AC1, AV0, AV0S, AV1, AV1S, V, VS]; } def SEQSTAT : Ri<7, 1, "seqstat">, DwarfRegNum<[41]>; @@ -194,6 +191,29 @@ def LC1 : Ri<6, 3, "lc1">, DwarfRegNum<[47]>; def LB0 : Ri<6, 2, "lb0">, DwarfRegNum<[48]>; def LB1 : Ri<6, 5, "lb1">, DwarfRegNum<[49]>; +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; +def : SubRegSet; + // Register classes. def D16 : RegisterClass<"BF", [i16], 16, [R0H, R0L, R1H, R1L, R2H, R2L, R3H, R3L, diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.td b/lib/Target/MBlaze/MBlazeRegisterInfo.td index d0a1e75..96a5c98 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.td +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.td @@ -17,15 +17,21 @@ class MBlazeReg : Register { let Namespace = "MBlaze"; } +class MBlazeRegWithSubRegs subregs> + : RegisterWithSubRegs { + field bits<5> Num; + let Namespace = "MBlaze"; +} + // MBlaze CPU Registers class MBlazeGPRReg num, string n> : MBlazeReg { let Num = num; } // MBlaze 32-bit (aliased) FPU Registers -class FPR num, string n, list aliases> : MBlazeReg { +class FPR num, string n, list subregs> + : MBlazeRegWithSubRegs { let Num = num; - let Aliases = aliases; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/MSP430/MSP430RegisterInfo.td b/lib/Target/MSP430/MSP430RegisterInfo.td index f8aec66..f488f00 100644 --- a/lib/Target/MSP430/MSP430RegisterInfo.td +++ b/lib/Target/MSP430/MSP430RegisterInfo.td @@ -43,9 +43,6 @@ def R13B : MSP430Reg<13, "r13">; def R14B : MSP430Reg<14, "r14">; def R15B : MSP430Reg<15, "r15">; -def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; } - -let SubRegIndices = [subreg_8bit] in { def PCW : MSP430RegWithSubregs<0, "r0", [PCB]>; def SPW : MSP430RegWithSubregs<1, "r1", [SPB]>; def SRW : MSP430RegWithSubregs<2, "r2", [SRB]>; @@ -62,7 +59,13 @@ def R12W : MSP430RegWithSubregs<12, "r12", [R12B]>; def R13W : MSP430RegWithSubregs<13, "r13", [R13B]>; def R14W : MSP430RegWithSubregs<14, "r14", [R14B]>; def R15W : MSP430RegWithSubregs<15, "r15", [R15B]>; -} + +def subreg_8bit : SubRegIndex { let Namespace = "MSP430"; } + +def : SubRegSet; def GR8 : RegisterClass<"MSP430", [i8], 8, // Volatile registers diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index be78a22..576110d 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -34,14 +34,9 @@ class FPR num, string n> : MipsReg { } // Mips 64-bit (aliased) FPU Registers -let Namespace = "Mips" in { -def sub_fpeven : SubRegIndex; -def sub_fpodd : SubRegIndex; -} -class AFPR num, string n, list subregs> +class AFPR num, string n, list subregs> : MipsRegWithSubRegs { let Num = num; - let SubRegIndices = [sub_fpeven, sub_fpodd]; } //===----------------------------------------------------------------------===// @@ -146,6 +141,25 @@ let Namespace = "Mips" in { } //===----------------------------------------------------------------------===// +// Subregister Set Definitions +//===----------------------------------------------------------------------===// + +let Namespace = "Mips" in { +def sub_fpeven : SubRegIndex; +def sub_fpodd : SubRegIndex; +} + +def : SubRegSet; + +def : SubRegSet; + +//===----------------------------------------------------------------------===// // Register Classes //===----------------------------------------------------------------------===// diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 8604f54..5aa6e02 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -10,15 +10,6 @@ // //===----------------------------------------------------------------------===// -let Namespace = "PPC" in { -def sub_lt : SubRegIndex; -def sub_gt : SubRegIndex; -def sub_eq : SubRegIndex; -def sub_un : SubRegIndex; -def sub_32 : SubRegIndex; -} - - class PPCReg : Register { let Namespace = "PPC"; } @@ -34,7 +25,6 @@ class GPR num, string n> : PPCReg { class GP8 : PPCReg { field bits<5> Num = SubReg.Num; let SubRegs = [SubReg]; - let SubRegIndices = [sub_32]; } // SPR - One of the 32-bit special-purpose registers @@ -235,7 +225,6 @@ def CR7EQ : CRBIT<30, "30">, DwarfRegNum<[0]>; def CR7UN : CRBIT<31, "31">, DwarfRegNum<[0]>; // Condition registers -let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68]>; def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69]>; def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70]>; @@ -244,8 +233,27 @@ def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72]>; def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73]>; def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>; def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>; + +let Namespace = "PPC" in { +def sub_lt : SubRegIndex; +def sub_gt : SubRegIndex; +def sub_eq : SubRegIndex; +def sub_un : SubRegIndex; } +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; +def : SubRegSet; + // Link register def LR : SPR<8, "lr">, DwarfRegNum<[65]>; //let Aliases = [LR] in diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index fede929..2b05c19 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -20,11 +20,6 @@ class SparcCtrlReg: Register { let Namespace = "SP"; } -let Namespace = "SP" in { -def sub_even : SubRegIndex; -def sub_odd : SubRegIndex; -} - // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers class Ri num, string n> : SparcReg { @@ -38,7 +33,6 @@ class Rf num, string n> : SparcReg { class Rd num, string n, list subregs> : SparcReg { let Num = num; let SubRegs = subregs; - let SubRegIndices = [sub_even, sub_odd]; } // Control Registers diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td index b561744..9c17573 100644 --- a/lib/Target/SystemZ/SystemZRegisterInfo.td +++ b/lib/Target/SystemZ/SystemZRegisterInfo.td @@ -53,14 +53,6 @@ class FPRL num, string n, list subregs> field bits<4> Num = num; } -let Namespace = "SystemZ" in { -def subreg_32bit : SubRegIndex; -def subreg_even32 : SubRegIndex; -def subreg_odd32 : SubRegIndex; -def subreg_even : SubRegIndex; -def subreg_odd : SubRegIndex; -} - // General-purpose registers def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>; def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>; @@ -79,7 +71,6 @@ def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>; def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>; def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>; -let SubRegIndices = [subreg_32bit] in { def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>; def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>; def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>; @@ -96,10 +87,8 @@ def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>; def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>; def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>; def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>; -} // Register pairs -let SubRegIndices = [subreg_even32, subreg_odd32] in { def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>; def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>; def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>; @@ -108,11 +97,7 @@ def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>, DwarfRegNum<[8]>; def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>; def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>; def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>; -} -let SubRegIndices = [subreg_even, subreg_odd], - CompositeIndices = [(subreg_even32 subreg_even, subreg_32bit), - (subreg_odd32 subreg_odd, subreg_32bit)] in { def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>; def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>; def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>; @@ -121,7 +106,6 @@ def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>, DwarfRegNum<[8]>; def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>; def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>; def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>; -} // Floating-point registers def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>; @@ -141,7 +125,6 @@ def F13S : FPRS<13, "f13">, DwarfRegNum<[29]>; def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>; def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>; -let SubRegIndices = [subreg_32bit] in { def F0L : FPRL< 0, "f0", [F0S]>, DwarfRegNum<[16]>; def F1L : FPRL< 1, "f1", [F1S]>, DwarfRegNum<[17]>; def F2L : FPRL< 2, "f2", [F2S]>, DwarfRegNum<[18]>; @@ -158,11 +141,41 @@ def F12L : FPRL<12, "f12", [F12S]>, DwarfRegNum<[28]>; def F13L : FPRL<13, "f13", [F13S]>, DwarfRegNum<[29]>; def F14L : FPRL<14, "f14", [F14S]>, DwarfRegNum<[30]>; def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>; -} // Status register def PSW : SystemZReg<"psw">; +let Namespace = "SystemZ" in { +def subreg_32bit : SubRegIndex; +def subreg_even32 : SubRegIndex; +def subreg_odd32 : SubRegIndex; +def subreg_even : SubRegIndex; +def subreg_odd : SubRegIndex; +} + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + /// Register classes def GR32 : RegisterClass<"SystemZ", [i32], 32, // Volatile registers diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 91cfaa9..7e17086 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -68,22 +68,17 @@ let Namespace = "X86" in { def BH : Register<"bh">, DwarfRegNum<[3, 3, 3]>; // 16-bit registers - let SubRegIndices = [sub_8bit, sub_8bit_hi] in { def AX : RegisterWithSubRegs<"ax", [AL,AH]>, DwarfRegNum<[0, 0, 0]>; def DX : RegisterWithSubRegs<"dx", [DL,DH]>, DwarfRegNum<[1, 2, 2]>; def CX : RegisterWithSubRegs<"cx", [CL,CH]>, DwarfRegNum<[2, 1, 1]>; def BX : RegisterWithSubRegs<"bx", [BL,BH]>, DwarfRegNum<[3, 3, 3]>; - } - let SubRegIndices = [sub_8bit] in { def SI : RegisterWithSubRegs<"si", [SIL]>, DwarfRegNum<[4, 6, 6]>; def DI : RegisterWithSubRegs<"di", [DIL]>, DwarfRegNum<[5, 7, 7]>; def BP : RegisterWithSubRegs<"bp", [BPL]>, DwarfRegNum<[6, 4, 5]>; def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>; - } def IP : Register<"ip">, DwarfRegNum<[16]>; // X86-64 only - let SubRegIndices = [sub_8bit] in { def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>; def R9W : RegisterWithSubRegs<"r9w", [R9B]>, DwarfRegNum<[9, -2, -2]>; def R10W : RegisterWithSubRegs<"r10w", [R10B]>, DwarfRegNum<[10, -2, -2]>; @@ -92,9 +87,8 @@ let Namespace = "X86" in { def R13W : RegisterWithSubRegs<"r13w", [R13B]>, DwarfRegNum<[13, -2, -2]>; def R14W : RegisterWithSubRegs<"r14w", [R14B]>, DwarfRegNum<[14, -2, -2]>; def R15W : RegisterWithSubRegs<"r15w", [R15B]>, DwarfRegNum<[15, -2, -2]>; - } + // 32-bit registers - let SubRegIndices = [sub_16bit] in { def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>; def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>; def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>; @@ -114,10 +108,8 @@ let Namespace = "X86" in { def R13D : RegisterWithSubRegs<"r13d", [R13W]>, DwarfRegNum<[13, -2, -2]>; def R14D : RegisterWithSubRegs<"r14d", [R14W]>, DwarfRegNum<[14, -2, -2]>; def R15D : RegisterWithSubRegs<"r15d", [R15W]>, DwarfRegNum<[15, -2, -2]>; - } // 64-bit registers, X86-64 only - let SubRegIndices = [sub_32bit] in { def RAX : RegisterWithSubRegs<"rax", [EAX]>, DwarfRegNum<[0, -2, -2]>; def RDX : RegisterWithSubRegs<"rdx", [EDX]>, DwarfRegNum<[1, -2, -2]>; def RCX : RegisterWithSubRegs<"rcx", [ECX]>, DwarfRegNum<[2, -2, -2]>; @@ -136,7 +128,6 @@ let Namespace = "X86" in { def R14 : RegisterWithSubRegs<"r14", [R14D]>, DwarfRegNum<[14, -2, -2]>; def R15 : RegisterWithSubRegs<"r15", [R15D]>, DwarfRegNum<[15, -2, -2]>; def RIP : RegisterWithSubRegs<"rip", [EIP]>, DwarfRegNum<[16, -2, -2]>; - } // MMX Registers. These are actually aliased to ST0 .. ST7 def MM0 : Register<"mm0">, DwarfRegNum<[41, 29, 29]>; @@ -157,9 +148,7 @@ let Namespace = "X86" in { def FP5 : Register<"fp5">; def FP6 : Register<"fp6">; - // XMM Registers, used by the various SSE instruction set extensions. - // The sub_ss and sub_sd subregs are the same registers with another regclass. - let CompositeIndices = [(sub_ss), (sub_sd)] in { + // XMM Registers, used by the various SSE instruction set extensions def XMM0: Register<"xmm0">, DwarfRegNum<[17, 21, 21]>; def XMM1: Register<"xmm1">, DwarfRegNum<[18, 22, 22]>; def XMM2: Register<"xmm2">, DwarfRegNum<[19, 23, 23]>; @@ -178,10 +167,8 @@ let Namespace = "X86" in { def XMM13: Register<"xmm13">, DwarfRegNum<[30, -2, -2]>; def XMM14: Register<"xmm14">, DwarfRegNum<[31, -2, -2]>; def XMM15: Register<"xmm15">, DwarfRegNum<[32, -2, -2]>; - } // YMM Registers, used by AVX instructions - let SubRegIndices = [sub_xmm] in { def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>; def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>; def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>; @@ -198,7 +185,6 @@ let Namespace = "X86" in { def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>; def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>; def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>; - } // Floating point stack registers def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>; @@ -245,6 +231,75 @@ let Namespace = "X86" in { //===----------------------------------------------------------------------===// +// Subregister Set Definitions... now that we have all of the pieces, define the +// sub registers for each register. +// + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +def : SubRegSet; + +//===----------------------------------------------------------------------===// // Register Class Definitions... now that we have all of the pieces, define the // top-level register classes. The order specified in the register list is // implicitly defined to be the register allocation order. -- cgit v1.1