From d85ed0caa1f780cbd13af1891d2a30fdfbad547a Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Sun, 1 Dec 2013 03:11:03 +0000 Subject: Merging r195843: ------------------------------------------------------------------------ r195843 | jiangning | 2013-11-27 06:02:25 -0800 (Wed, 27 Nov 2013) | 2 lines Fix the AArch64 NEON bug exposed by checking constant integer argument range of ACLE intrinsics. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195997 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AArch64/AArch64ISelLowering.cpp | 17 +++ lib/Target/AArch64/AArch64InstrNEON.td | 229 ++++++++--------------------- 2 files changed, 82 insertions(+), 164 deletions(-) (limited to 'lib') diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp index ee98b4c..7311d55 100644 --- a/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -4231,6 +4231,23 @@ AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, return DAG.getNode(AArch64ISD::NEON_VDUP, dl, VT, V1.getOperand(Lane)); } + + // Test if V1 is a EXTRACT_SUBVECTOR. + if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) { + int ExtLane = cast(V1.getOperand(1))->getZExtValue(); + return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0), + DAG.getConstant(Lane + ExtLane, MVT::i64)); + } + // Test if V1 is a CONCAT_VECTORS. + if (V1.getOpcode() == ISD::CONCAT_VECTORS) { + if (V1.getOperand(1).getOpcode() == ISD::UNDEF) { + int V1EltNum = V1.getOperand(0).getValueType().getVectorNumElements(); + assert((Lane < V1EltNum) && "Invalid vector lane access"); + return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1.getOperand(0), + DAG.getConstant(Lane, MVT::i64)); + } + } + return DAG.getNode(AArch64ISD::NEON_VDUPLANE, dl, VT, V1, DAG.getConstant(Lane, MVT::i64)); } diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td index b1fc8ba..461a3fe 100644 --- a/lib/Target/AArch64/AArch64InstrNEON.td +++ b/lib/Target/AArch64/AArch64InstrNEON.td @@ -6074,62 +6074,42 @@ defm MLSvve : NI_2VE_v1<0b1, 0b0100, "mls">; class NI_2VE_laneq + ValueType EleOpTy> : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn), - (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), + (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), (INST ResVPR:$src, OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>; // Pattern for lane in 64-bit vector class NI_2VE_lane + ValueType EleOpTy> : Pat<(ResTy (op (ResTy ResVPR:$src), (OpTy OpVPR:$Rn), - (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), + (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), (INST ResVPR:$src, OpVPR:$Rn, (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>; multiclass NI_2VE_v1_pat { def : NI_2VE_laneq(subop # "_2s4s"), neon_uimm2_bare, - op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32, - BinOpFrag<(Neon_vduplane - (Neon_Low4S node:$LHS), node:$RHS)>>; + op, VPR64, VPR64, VPR128, v2i32, v2i32, v4i32>; def : NI_2VE_laneq(subop # "_4s4s"), neon_uimm2_bare, - op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR128, VPR128, VPR128, v4i32, v4i32, v4i32>; def : NI_2VE_laneq(subop # "_4h8h"), neon_uimm3_bare, - op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16, - BinOpFrag<(Neon_vduplane - (Neon_Low8H node:$LHS), node:$RHS)>>; + op, VPR64, VPR64, VPR128Lo, v4i16, v4i16, v8i16>; def : NI_2VE_laneq(subop # "_8h8h"), neon_uimm3_bare, - op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR128, VPR128, VPR128Lo, v8i16, v8i16, v8i16>; // Index can only be half of the max value for lane in 64-bit vector def : NI_2VE_lane(subop # "_2s4s"), neon_uimm1_bare, - op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; - - def : NI_2VE_lane(subop # "_4s4s"), neon_uimm1_bare, - op, VPR128, VPR128, VPR64, v4i32, v4i32, v2i32, - BinOpFrag<(Neon_vduplane - (Neon_combine_4S node:$LHS, undef), - node:$RHS)>>; + op, VPR64, VPR64, VPR64, v2i32, v2i32, v2i32>; def : NI_2VE_lane(subop # "_4h8h"), neon_uimm2_bare, - op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; - - def : NI_2VE_lane(subop # "_8h8h"), neon_uimm2_bare, - op, VPR128, VPR128, VPR64Lo, v8i16, v8i16, v4i16, - BinOpFrag<(Neon_vduplane - (Neon_combine_8H node:$LHS, undef), - node:$RHS)>>; + op, VPR64, VPR64, VPR64Lo, v4i16, v4i16, v4i16>; } defm MLA_lane_v1 : NI_2VE_v1_pat<"MLAvve", Neon_mla>; @@ -6191,62 +6171,40 @@ defm SQRDMULHve : NI_2VE_v1_2op<0b0, 0b1101, "sqrdmulh">; // Pattern for lane in 128-bit vector class NI_2VE_mul_laneq + ValueType ResTy, ValueType OpTy, ValueType EleOpTy> : Pat<(ResTy (op (OpTy OpVPR:$Rn), - (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), + (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), (INST OpVPR:$Rn, EleOpVPR:$Re, OpImm:$Index)>; // Pattern for lane in 64-bit vector class NI_2VE_mul_lane + ValueType ResTy, ValueType OpTy, ValueType EleOpTy> : Pat<(ResTy (op (OpTy OpVPR:$Rn), - (OpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), + (OpTy (Neon_vduplane (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), (INST OpVPR:$Rn, (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>; multiclass NI_2VE_mul_v1_pat { def : NI_2VE_mul_laneq(subop # "_2s4s"), neon_uimm2_bare, - op, VPR64, VPR128, v2i32, v2i32, v4i32, - BinOpFrag<(Neon_vduplane - (Neon_Low4S node:$LHS), node:$RHS)>>; + op, VPR64, VPR128, v2i32, v2i32, v4i32>; def : NI_2VE_mul_laneq(subop # "_4s4s"), neon_uimm2_bare, - op, VPR128, VPR128, v4i32, v4i32, v4i32, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR128, VPR128, v4i32, v4i32, v4i32>; def : NI_2VE_mul_laneq(subop # "_4h8h"), neon_uimm3_bare, - op, VPR64, VPR128Lo, v4i16, v4i16, v8i16, - BinOpFrag<(Neon_vduplane - (Neon_Low8H node:$LHS), node:$RHS)>>; + op, VPR64, VPR128Lo, v4i16, v4i16, v8i16>; def : NI_2VE_mul_laneq(subop # "_8h8h"), neon_uimm3_bare, - op, VPR128, VPR128Lo, v8i16, v8i16, v8i16, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR128, VPR128Lo, v8i16, v8i16, v8i16>; // Index can only be half of the max value for lane in 64-bit vector def : NI_2VE_mul_lane(subop # "_2s4s"), neon_uimm1_bare, - op, VPR64, VPR64, v2i32, v2i32, v2i32, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; - - def : NI_2VE_mul_lane(subop # "_4s4s"), neon_uimm1_bare, - op, VPR128, VPR64, v4i32, v4i32, v2i32, - BinOpFrag<(Neon_vduplane - (Neon_combine_4S node:$LHS, undef), - node:$RHS)>>; + op, VPR64, VPR64, v2i32, v2i32, v2i32>; def : NI_2VE_mul_lane(subop # "_4h8h"), neon_uimm2_bare, - op, VPR64, VPR64Lo, v4i16, v4i16, v4i16, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; - - def : NI_2VE_mul_lane(subop # "_8h8h"), neon_uimm2_bare, - op, VPR128, VPR64Lo, v8i16, v8i16, v4i16, - BinOpFrag<(Neon_vduplane - (Neon_combine_8H node:$LHS, undef), - node:$RHS)>>; + op, VPR64, VPR64Lo, v4i16, v4i16, v4i16>; } defm MUL_lane_v1 : NI_2VE_mul_v1_pat<"MULve", mul>; @@ -6295,29 +6253,18 @@ class NI_2VE_mul_lane_2d { def : NI_2VE_mul_laneq(subop # "_2s4s"), neon_uimm2_bare, - op, VPR64, VPR128, v2f32, v2f32, v4f32, - BinOpFrag<(Neon_vduplane - (Neon_Low4float node:$LHS), node:$RHS)>>; + op, VPR64, VPR128, v2f32, v2f32, v4f32>; def : NI_2VE_mul_laneq(subop # "_4s4s"), neon_uimm2_bare, - op, VPR128, VPR128, v4f32, v4f32, v4f32, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR128, VPR128, v4f32, v4f32, v4f32>; def : NI_2VE_mul_laneq(subop # "_2d2d"), neon_uimm1_bare, - op, VPR128, VPR128, v2f64, v2f64, v2f64, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR128, VPR128, v2f64, v2f64, v2f64>; // Index can only be half of the max value for lane in 64-bit vector def : NI_2VE_mul_lane(subop # "_2s4s"), neon_uimm1_bare, - op, VPR64, VPR64, v2f32, v2f32, v2f32, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; - - def : NI_2VE_mul_lane(subop # "_4s4s"), neon_uimm1_bare, - op, VPR128, VPR64, v4f32, v4f32, v2f32, - BinOpFrag<(Neon_vduplane - (Neon_combine_4f node:$LHS, undef), - node:$RHS)>>; + op, VPR64, VPR64, v2f32, v2f32, v2f32>; def : NI_2VE_mul_lane_2d(subop # "_2d2d"), neon_uimm1_bare, op, VPR128, VPR64, v2f64, v2f64, v1f64, @@ -6393,8 +6340,7 @@ class NI_2VEswap_lane_2d2d { def : NI_2VEswap_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32, - BinOpFrag<(Neon_vduplane - (Neon_Low4float node:$LHS), node:$RHS)>>; + BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; def : NI_2VEswap_laneq(subop # "_4s4s"), neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32, @@ -6410,12 +6356,6 @@ multiclass NI_2VE_fma_v2_pat { neon_uimm1_bare, op, VPR64, VPR64, v2f32, v2f32, BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; - def : NI_2VEswap_lane(subop # "_4s4s"), - neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32, - BinOpFrag<(Neon_vduplane - (Neon_combine_4f node:$LHS, undef), - node:$RHS)>>; - def : NI_2VEswap_lane_2d2d(subop # "_2d2d"), neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64, BinOpFrag<(Neon_combine_2d node:$LHS, node:$RHS)>>; @@ -6427,14 +6367,12 @@ multiclass NI_2VE_fms_v2_pat { def : NI_2VEswap_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32, - BinOpFrag<(fneg (Neon_vduplane - (Neon_Low4float node:$LHS), node:$RHS))>>; + BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>; def : NI_2VEswap_laneq(subop # "_2s4s"), neon_uimm2_bare, op, VPR64, VPR128, v2f32, v4f32, BinOpFrag<(Neon_vduplane - (Neon_Low4float (fneg node:$LHS)), - node:$RHS)>>; + (fneg node:$LHS), node:$RHS)>>; def : NI_2VEswap_laneq(subop # "_4s4s"), neon_uimm2_bare, op, VPR128, VPR128, v4f32, v4f32, @@ -6470,15 +6408,11 @@ multiclass NI_2VE_fms_v2_pat def : NI_2VEswap_lane(subop # "_4s4s"), neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32, - BinOpFrag<(fneg (Neon_vduplane - (Neon_combine_4f node:$LHS, undef), - node:$RHS))>>; + BinOpFrag<(fneg (Neon_vduplane node:$LHS, node:$RHS))>>; def : NI_2VEswap_lane(subop # "_4s4s"), neon_uimm1_bare, op, VPR128, VPR64, v4f32, v2f32, - BinOpFrag<(Neon_vduplane - (Neon_combine_4f (fneg node:$LHS), undef), - node:$RHS)>>; + BinOpFrag<(Neon_vduplane (fneg node:$LHS), node:$RHS)>>; def : NI_2VEswap_lane_2d2d(subop # "_2d2d"), neon_uimm1_bare, op, VPR128, VPR64, v2f64, v1f64, @@ -6580,61 +6514,51 @@ defm SQDMULLve : NI_2VE_v3_2op<0b0, 0b1011, "sqdmull">; class NI_2VEL2_laneq + SDPatternOperator hiop> : Pat<(ResTy (op (ResTy VPR128:$src), (HalfOpTy (hiop (OpTy VPR128:$Rn))), - (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), + (HalfOpTy (Neon_vduplane + (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), (INST VPR128:$src, VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>; // Pattern for lane in 64-bit vector class NI_2VEL2_lane + SDPatternOperator hiop> : Pat<(ResTy (op (ResTy VPR128:$src), (HalfOpTy (hiop (OpTy VPR128:$Rn))), - (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), + (HalfOpTy (Neon_vduplane + (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), (INST VPR128:$src, VPR128:$Rn, (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>; multiclass NI_2VEL_v3_pat { def : NI_2VE_laneq(subop # "_4s4h"), neon_uimm3_bare, - op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16, - BinOpFrag<(Neon_vduplane - (Neon_Low8H node:$LHS), node:$RHS)>>; + op, VPR128, VPR64, VPR128Lo, v4i32, v4i16, v8i16>; def : NI_2VE_laneq(subop # "_2d2s"), neon_uimm2_bare, - op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32, - BinOpFrag<(Neon_vduplane - (Neon_Low4S node:$LHS), node:$RHS)>>; + op, VPR128, VPR64, VPR128, v2i64, v2i32, v4i32>; def : NI_2VEL2_laneq(subop # "_4s8h"), neon_uimm3_bare, - op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H, - BinOpFrag<(Neon_vduplane - (Neon_Low8H node:$LHS), node:$RHS)>>; + op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>; def : NI_2VEL2_laneq(subop # "_2d4s"), neon_uimm2_bare, - op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S, - BinOpFrag<(Neon_vduplane - (Neon_Low4S node:$LHS), node:$RHS)>>; + op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>; // Index can only be half of the max value for lane in 64-bit vector def : NI_2VE_lane(subop # "_4s4h"), neon_uimm2_bare, - op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR128, VPR64, VPR64Lo, v4i32, v4i16, v4i16>; def : NI_2VE_lane(subop # "_2d2s"), neon_uimm1_bare, - op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR128, VPR64, VPR64, v2i64, v2i32, v2i32>; def : NI_2VEL2_lane(subop # "_4s8h"), neon_uimm2_bare, - op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>; def : NI_2VEL2_lane(subop # "_2d4s"), neon_uimm1_bare, - op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>; } defm SMLAL_lane_v3 : NI_2VEL_v3_pat<"SMLALvve", Neon_smlal>; @@ -6646,62 +6570,51 @@ defm UMLSL_lane_v3 : NI_2VEL_v3_pat<"UMLSLvve", Neon_umlsl>; class NI_2VEL2_mul_laneq + SDPatternOperator hiop> : Pat<(ResTy (op (HalfOpTy (hiop (OpTy VPR128:$Rn))), - (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), + (HalfOpTy (Neon_vduplane + (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), (INST VPR128:$Rn, EleOpVPR:$Re, OpImm:$Index)>; // Pattern for lane in 64-bit vector class NI_2VEL2_mul_lane + SDPatternOperator hiop> : Pat<(ResTy (op (HalfOpTy (hiop (OpTy VPR128:$Rn))), - (HalfOpTy (coreop (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), + (HalfOpTy (Neon_vduplane + (EleOpTy EleOpVPR:$Re), (i64 OpImm:$Index))))), (INST VPR128:$Rn, (SUBREG_TO_REG (i64 0), EleOpVPR:$Re, sub_64), OpImm:$Index)>; multiclass NI_2VEL_mul_v3_pat { def : NI_2VE_mul_laneq(subop # "_4s4h"), neon_uimm3_bare, - op, VPR64, VPR128Lo, v4i32, v4i16, v8i16, - BinOpFrag<(Neon_vduplane - (Neon_Low8H node:$LHS), node:$RHS)>>; + op, VPR64, VPR128Lo, v4i32, v4i16, v8i16>; def : NI_2VE_mul_laneq(subop # "_2d2s"), neon_uimm2_bare, - op, VPR64, VPR128, v2i64, v2i32, v4i32, - BinOpFrag<(Neon_vduplane - (Neon_Low4S node:$LHS), node:$RHS)>>; + op, VPR64, VPR128, v2i64, v2i32, v4i32>; def : NI_2VEL2_mul_laneq(subop # "_4s8h"), neon_uimm3_bare, - op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, - Neon_High8H, - BinOpFrag<(Neon_vduplane - (Neon_Low8H node:$LHS), node:$RHS)>>; + op, VPR128Lo, v4i32, v8i16, v8i16, v4i16, Neon_High8H>; def : NI_2VEL2_mul_laneq(subop # "_2d4s"), neon_uimm2_bare, - op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S, - BinOpFrag<(Neon_vduplane - (Neon_Low4S node:$LHS), node:$RHS)>>; + op, VPR128, v2i64, v4i32, v4i32, v2i32, Neon_High4S>; // Index can only be half of the max value for lane in 64-bit vector def : NI_2VE_mul_lane(subop # "_4s4h"), neon_uimm2_bare, - op, VPR64, VPR64Lo, v4i32, v4i16, v4i16, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR64, VPR64Lo, v4i32, v4i16, v4i16>; def : NI_2VE_mul_lane(subop # "_2d2s"), neon_uimm1_bare, - op, VPR64, VPR64, v2i64, v2i32, v2i32, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR64, VPR64, v2i64, v2i32, v2i32>; def : NI_2VEL2_mul_lane(subop # "_4s8h"), neon_uimm2_bare, - op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR64Lo, v4i32, v8i16, v4i16, v4i16, Neon_High8H>; def : NI_2VEL2_mul_lane(subop # "_2d4s"), neon_uimm1_bare, - op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + op, VPR64, v2i64, v4i32, v2i32, v2i32, Neon_High4S>; } defm SMULL_lane_v3 : NI_2VEL_mul_v3_pat<"SMULLve", int_arm_neon_vmulls>; @@ -6724,49 +6637,37 @@ defm Neon_qdmlsl : NI_qdma; multiclass NI_2VEL_v3_qdma_pat { def : NI_2VE_laneq(subop # "_4s4h"), neon_uimm3_bare, !cast(op # "_4s"), VPR128, VPR64, VPR128Lo, - v4i32, v4i16, v8i16, - BinOpFrag<(Neon_vduplane - (Neon_Low8H node:$LHS), node:$RHS)>>; + v4i32, v4i16, v8i16>; def : NI_2VE_laneq(subop # "_2d2s"), neon_uimm2_bare, !cast(op # "_2d"), VPR128, VPR64, VPR128, - v2i64, v2i32, v4i32, - BinOpFrag<(Neon_vduplane - (Neon_Low4S node:$LHS), node:$RHS)>>; + v2i64, v2i32, v4i32>; def : NI_2VEL2_laneq(subop # "_4s8h"), neon_uimm3_bare, !cast(op # "_4s"), VPR128Lo, - v4i32, v8i16, v8i16, v4i16, Neon_High8H, - BinOpFrag<(Neon_vduplane - (Neon_Low8H node:$LHS), node:$RHS)>>; + v4i32, v8i16, v8i16, v4i16, Neon_High8H>; def : NI_2VEL2_laneq(subop # "_2d4s"), neon_uimm2_bare, !cast(op # "_2d"), VPR128, - v2i64, v4i32, v4i32, v2i32, Neon_High4S, - BinOpFrag<(Neon_vduplane - (Neon_Low4S node:$LHS), node:$RHS)>>; + v2i64, v4i32, v4i32, v2i32, Neon_High4S>; // Index can only be half of the max value for lane in 64-bit vector def : NI_2VE_lane(subop # "_4s4h"), neon_uimm2_bare, !cast(op # "_4s"), VPR128, VPR64, VPR64Lo, - v4i32, v4i16, v4i16, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + v4i32, v4i16, v4i16>; def : NI_2VE_lane(subop # "_2d2s"), neon_uimm1_bare, !cast(op # "_2d"), VPR128, VPR64, VPR64, - v2i64, v2i32, v2i32, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + v2i64, v2i32, v2i32>; def : NI_2VEL2_lane(subop # "_4s8h"), neon_uimm2_bare, !cast(op # "_4s"), VPR64Lo, - v4i32, v8i16, v4i16, v4i16, Neon_High8H, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + v4i32, v8i16, v4i16, v4i16, Neon_High8H>; def : NI_2VEL2_lane(subop # "_2d4s"), neon_uimm1_bare, !cast(op # "_2d"), VPR64, - v2i64, v4i32, v2i32, v2i32, Neon_High4S, - BinOpFrag<(Neon_vduplane node:$LHS, node:$RHS)>>; + v2i64, v4i32, v2i32, v2i32, Neon_High4S>; } defm SQDMLAL_lane_v3 : NI_2VEL_v3_qdma_pat<"SQDMLALvve", "Neon_qdmlal">; -- cgit v1.1