From e822f9450992774a2058163d0572538375e74051 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 13 Oct 2010 18:05:25 +0000 Subject: Fix encoding for compares. No Rd register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116414 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'lib') diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 3a0255b..e086aae 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -569,11 +569,10 @@ multiclass AI1_cmp_irs opcod, string opc, def ri : AI1 { - bits<4> Rd; bits<4> Rn; bits<12> imm; let Inst{25} = 1; - let Inst{15-12} = Rd; + let Inst{15-12} = 0b0000; let Inst{19-16} = Rn; let Inst{11-0} = imm; let Inst{20} = 1; @@ -582,26 +581,24 @@ multiclass AI1_cmp_irs opcod, string opc, def rr : AI1 { - bits<4> Rd; bits<4> Rn; bits<4> Rm; let Inst{11-4} = 0b00000000; let Inst{25} = 0; let isCommutable = Commutable; let Inst{3-0} = Rm; - let Inst{15-12} = Rd; + let Inst{15-12} = 0b0000; let Inst{19-16} = Rn; let Inst{20} = 1; } def rs : AI1 { - bits<4> Rd; bits<4> Rn; bits<12> shift; let Inst{25} = 0; let Inst{11-0} = shift; - let Inst{15-12} = Rd; + let Inst{15-12} = 0b0000; let Inst{19-16} = Rn; let Inst{20} = 1; } -- cgit v1.1