From 544b9b426f0dfa1beef6dc3640607dee3ca1160e Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Thu, 22 Mar 2012 00:21:17 +0000 Subject: [fast-isel] Fold "urem x, pow2" -> "and x, pow2-1". This should fix the 271% execution-time regression for nsieve-bits on the ARMv7 -O0 -g nightly tester. This may also improve compile-time on architectures that would otherwise generate a libcall for urem (e.g., ARM) or fall back to the DAG selector. rdar://10810716 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153230 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/fast-isel.ll | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'test/CodeGen/ARM') diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index 905543a..417e2d9 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -217,3 +217,12 @@ entry: ; THUMB: vcmpe.f32 s0, #0 ret i1 %4 } + +; ARM: @urem_fold +; THUMB: @urem_fold +; ARM: and r0, r0, #31 +; THUMB: and r0, r0, #31 +define i32 @urem_fold(i32 %a) nounwind { + %rem = urem i32 %a, 32 + ret i32 %rem +} -- cgit v1.1