From e5038e191db82d4d92fdeec1b5bce5cae21f6d8f Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Sat, 20 Aug 2011 00:17:25 +0000 Subject: VMOVQQQQs pseudo instructions are only created by ARMBaseInstrInfo::copyPhysReg. Therefore, rather then generate a pseudo instruction, which is later expanded, generate the necessary instructions in place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138163 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'test/CodeGen/ARM') diff --git a/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll b/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll index f8e6a4e..a7cdb4d 100644 --- a/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll +++ b/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll @@ -1,7 +1,6 @@ ; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0 -o - -; The following test is supposed to produce a VMOVQQQQ pseudo instruction. -; Make sure that it gets expanded; otherwise, the compile fails when trying -; to print the pseudo-instruction. +; Make sure that the VMOVQQQQ pseudo instruction is handled properly +; by codegen. define void @test_vmovqqqq_pseudo() nounwind ssp { entry: -- cgit v1.1