From c9c8b2a804b2cd3d33a6a965e06a21ff93968f97 Mon Sep 17 00:00:00 2001 From: Scott Michel Date: Mon, 26 Jan 2009 03:31:40 +0000 Subject: CellSPU: - Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/CellSPU/fcmp64.ll | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 test/CodeGen/CellSPU/fcmp64.ll (limited to 'test/CodeGen/CellSPU/fcmp64.ll') diff --git a/test/CodeGen/CellSPU/fcmp64.ll b/test/CodeGen/CellSPU/fcmp64.ll new file mode 100644 index 0000000..1906bfe --- /dev/null +++ b/test/CodeGen/CellSPU/fcmp64.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s + +define i1 @fcmp_eq_setcc_f64(double %arg1, double %arg2) nounwind { +entry: + %A = fcmp oeq double %arg1, %arg2 + ret i1 %A +} -- cgit v1.1