From 6b8d2026ba0b60a317fa239eacbcaeff5f2270f0 Mon Sep 17 00:00:00 2001
From: Jyotsna Verma <jverma@codeaurora.org>
Date: Tue, 12 Feb 2013 16:06:23 +0000
Subject: Hexagon: Add support to generate predicated absolute addressing mode
 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174973 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/Hexagon/pred-absolute-store.ll | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 test/CodeGen/Hexagon/pred-absolute-store.ll

(limited to 'test/CodeGen/Hexagon/pred-absolute-store.ll')

diff --git a/test/CodeGen/Hexagon/pred-absolute-store.ll b/test/CodeGen/Hexagon/pred-absolute-store.ll
new file mode 100644
index 0000000..b1b09f4
--- /dev/null
+++ b/test/CodeGen/Hexagon/pred-absolute-store.ll
@@ -0,0 +1,19 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
+; Check that we are able to predicate instructions with abosolute
+; addressing mode.
+
+; CHECK: if{{ *}}(p{{[0-3]+}}){{ *}}memw(##gvar){{ *}}={{ *}}r{{[0-9]+}}
+
+@gvar = external global i32
+define i32 @test2(i32 %a, i32 %b) nounwind {
+entry:
+  %cmp = icmp eq i32 %a, %b
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  store i32 %a, i32* @gvar, align 4
+  br label %if.end
+
+if.end:
+  ret i32 %b
+}
-- 
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