From 7bb9585c6e2528e3e4e928e7691dd97a106e3de0 Mon Sep 17 00:00:00 2001 From: Jyotsna Verma Date: Tue, 26 Mar 2013 15:43:57 +0000 Subject: Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Hexagon/ashift-left-right.ll | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 test/CodeGen/Hexagon/ashift-left-right.ll (limited to 'test/CodeGen/Hexagon') diff --git a/test/CodeGen/Hexagon/ashift-left-right.ll b/test/CodeGen/Hexagon/ashift-left-right.ll new file mode 100644 index 0000000..7c41bc7 --- /dev/null +++ b/test/CodeGen/Hexagon/ashift-left-right.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s + +define i32 @foo(i32 %a, i32 %b) nounwind readnone { +; CHECK: lsl +; CHECK: aslh +entry: + %shl1 = shl i32 16, %a + %shl2 = shl i32 %b, 16 + %ret = mul i32 %shl1, %shl2 + ret i32 %ret +} + +define i32 @bar(i32 %a, i32 %b) nounwind readnone { +; CHECK: asrh +; CHECK: lsr +entry: + %shl1 = ashr i32 16, %a + %shl2 = ashr i32 %b, 16 + %ret = mul i32 %shl1, %shl2 + ret i32 %ret +} -- cgit v1.1