From 92f24d403f16ab2ee4598e32c926acc9c2344140 Mon Sep 17 00:00:00 2001 From: Vincent Lejeune Date: Thu, 2 May 2013 21:52:30 +0000 Subject: R600: Prettier asmPrint of Alu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/R600/fsub.ll | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'test/CodeGen/R600/fsub.ll') diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll index 812388b..f784cde 100644 --- a/test/CodeGen/R600/fsub.ll +++ b/test/CodeGen/R600/fsub.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; CHECK: @fsub_f32 -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} define void @fsub_f32() { %r0 = call float @llvm.R600.load.input(i32 0) @@ -17,9 +17,9 @@ declare void @llvm.AMDGPU.store.output(float, i32) ; CHECK: @fsub_v4f32 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 -- cgit v1.1