From 3f5d63b95618860ca69eeab9be37cf26a253150e Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Tue, 23 Jul 2013 01:48:42 +0000 Subject: R600: Add support for 24-bit MUL instructions Reviewed-by: Vincent Lejeune git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186922 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/R600/mul_int24.ll | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 test/CodeGen/R600/mul_int24.ll (limited to 'test/CodeGen/R600/mul_int24.ll') diff --git a/test/CodeGen/R600/mul_int24.ll b/test/CodeGen/R600/mul_int24.ll new file mode 100644 index 0000000..16ae760 --- /dev/null +++ b/test/CodeGen/R600/mul_int24.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK +; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK + +; EG-CHECK: @i32_mul24 +; Signed 24-bit multiply is not supported on pre-Cayman GPUs. +; EG-CHECK: MULLO_INT +; CM-CHECK: MUL_INT24 {{[ *]*}}T{{[0-9].[XYZW]}}, KC0[2].Z, KC0[2].W +; SI-CHECK: V_MUL_I32_I24 +define void @i32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) { +entry: + %0 = shl i32 %a, 8 + %a_24 = ashr i32 %0, 8 + %1 = shl i32 %b, 8 + %b_24 = ashr i32 %1, 8 + %2 = mul i32 %a_24, %b_24 + store i32 %2, i32 addrspace(1)* %out + ret void +} -- cgit v1.1