From 4a03775777785ef758cff8c0699a6bf571a1f2b9 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 4 Sep 2008 22:59:58 +0000 Subject: For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55807 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/2007-08-13-SpillerReuse.ll | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'test/CodeGen/X86/2007-08-13-SpillerReuse.ll') diff --git a/test/CodeGen/X86/2007-08-13-SpillerReuse.ll b/test/CodeGen/X86/2007-08-13-SpillerReuse.ll index 8cc235b..edcb823 100644 --- a/test/CodeGen/X86/2007-08-13-SpillerReuse.ll +++ b/test/CodeGen/X86/2007-08-13-SpillerReuse.ll @@ -6,9 +6,9 @@ @rtx_format = external global [116 x i8*] ; <[116 x i8*]*> [#uses=1] @rtx_length = external global [117 x i32] ; <[117 x i32]*> [#uses=1] -declare fastcc %struct.rtx_def* @fixup_memory_subreg(%struct.rtx_def*, %struct.rtx_def*, i32) +declare %struct.rtx_def* @fixup_memory_subreg(%struct.rtx_def*, %struct.rtx_def*, i32) -define fastcc %struct.rtx_def* @walk_fixup_memory_subreg(%struct.rtx_def* %x, %struct.rtx_def* %insn) { +define %struct.rtx_def* @walk_fixup_memory_subreg(%struct.rtx_def* %x, %struct.rtx_def* %insn) { entry: %tmp2 = icmp eq %struct.rtx_def* %x, null ; [#uses=1] br i1 %tmp2, label %UnifiedReturnBlock, label %cond_next @@ -30,7 +30,7 @@ cond_true13: ; preds = %cond_next br i1 %tmp22, label %cond_true25, label %cond_next32 cond_true25: ; preds = %cond_true13 - %tmp29 = tail call fastcc %struct.rtx_def* @fixup_memory_subreg( %struct.rtx_def* %x, %struct.rtx_def* %insn, i32 1 ) ; <%struct.rtx_def*> [#uses=1] + %tmp29 = tail call %struct.rtx_def* @fixup_memory_subreg( %struct.rtx_def* %x, %struct.rtx_def* %insn, i32 1 ) ; <%struct.rtx_def*> [#uses=1] ret %struct.rtx_def* %tmp29 cond_next32: ; preds = %cond_true13, %cond_next @@ -56,7 +56,7 @@ cond_true47: ; preds = %bb %tmp52 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0 ; <%struct..0anon*> [#uses=1] %tmp5354 = bitcast %struct..0anon* %tmp52 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1] %tmp55 = load %struct.rtx_def** %tmp5354 ; <%struct.rtx_def*> [#uses=1] - %tmp58 = tail call fastcc %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp55, %struct.rtx_def* %insn ) ; <%struct.rtx_def*> [#uses=1] + %tmp58 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp55, %struct.rtx_def* %insn ) ; <%struct.rtx_def*> [#uses=1] %tmp62 = getelementptr %struct.rtx_def* %x, i32 0, i32 3, i32 %i.01.0, i32 0 ; [#uses=1] %tmp58.c = ptrtoint %struct.rtx_def* %tmp58 to i32 ; [#uses=1] store i32 %tmp58.c, i32* %tmp62 @@ -79,7 +79,7 @@ bb73: ; preds = %bb73, %bb105.preheader %tmp92 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019 ; <%struct..0anon*> [#uses=1] %tmp9394 = bitcast %struct..0anon* %tmp92 to %struct.rtx_def** ; <%struct.rtx_def**> [#uses=1] %tmp95 = load %struct.rtx_def** %tmp9394 ; <%struct.rtx_def*> [#uses=1] - %tmp98 = tail call fastcc %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp95, %struct.rtx_def* %insn ) ; <%struct.rtx_def*> [#uses=1] + %tmp98 = tail call %struct.rtx_def* @walk_fixup_memory_subreg( %struct.rtx_def* %tmp95, %struct.rtx_def* %insn ) ; <%struct.rtx_def*> [#uses=1] %tmp101 = getelementptr %struct.rtvec_def* %tmp81, i32 0, i32 1, i32 %j.019, i32 0 ; [#uses=1] %tmp98.c = ptrtoint %struct.rtx_def* %tmp98 to i32 ; [#uses=1] store i32 %tmp98.c, i32* %tmp101 -- cgit v1.1