From 5d088fee7cf20309669f85d2027e2b010b40025b Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Mon, 23 Mar 2009 22:57:19 +0000 Subject: Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. e.g. allocating for GR32, bh is not used, updating bl spill weight. bl should get the same spill weight otherwise it will be choosen as a spill candidate since spilling bh doesn't make ebx available. This fix PR2866. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67574 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/2009-03-23-LinearScanBug.ll | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 test/CodeGen/X86/2009-03-23-LinearScanBug.ll (limited to 'test/CodeGen/X86/2009-03-23-LinearScanBug.ll') diff --git a/test/CodeGen/X86/2009-03-23-LinearScanBug.ll b/test/CodeGen/X86/2009-03-23-LinearScanBug.ll new file mode 100644 index 0000000..0a4501e --- /dev/null +++ b/test/CodeGen/X86/2009-03-23-LinearScanBug.ll @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -fast + +define fastcc void @optimize_bit_field() nounwind { +bb4: + %a = load i32* null ; [#uses=1] + %s = load i32* getelementptr (i32* null, i32 1) ; [#uses=1] + %z = load i32* getelementptr (i32* null, i32 2) ; [#uses=1] + %r = bitcast i32 0 to i32 ; [#uses=1] + %q = trunc i32 %z to i8 ; [#uses=1] + %b = icmp eq i8 0, %q ; [#uses=1] + br i1 %b, label %bb73, label %bb72 + +bb72: ; preds = %bb4 + %f = tail call fastcc i32 @gen_lowpart(i32 %r, i32 %a) nounwind ; [#uses=1] + br label %bb73 + +bb73: ; preds = %bb72, %bb4 + %y = phi i32 [ %f, %bb72 ], [ %s, %bb4 ] ; [#uses=1] + store i32 %y, i32* getelementptr (i32* null, i32 3) + unreachable +} + +declare fastcc i32 @gen_lowpart(i32, i32) nounwind -- cgit v1.1