From 97121ba2afb8d566ff1bf5c4e8fc5d4077940a7f Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Wed, 8 Apr 2009 00:15:30 +0000 Subject: Implement support for using modeling implicit-zero-extension on x86-64 with SUBREG_TO_REG, teach SimpleRegisterCoalescing to coalesce SUBREG_TO_REG instructions (which are similar to INSERT_SUBREG instructions), and teach the DAGCombiner to take advantage of this on targets which support it. This eliminates many redundant zero-extension operations on x86-64. This adds a new TargetLowering hook, isZExtFree. It's similar to isTruncateFree, except it only applies to actual definitions, and not no-op truncates which may not zero the high bits. Also, this adds a new optimization to SimplifyDemandedBits: transform operations like x+y into (zext (add (trunc x), (trunc y))) on targets where all the casts are no-ops. In contexts where the high part of the add is explicitly masked off, this allows the mask operation to be eliminated. Fix the DAGCombiner to avoid undoing these transformations to eliminate casts on targets where the casts are no-ops. Also, this adds a new two-address lowering heuristic. Since two-address lowering runs before coalescing, it helps to be able to look through copies when deciding whether commuting and/or three-address conversion are profitable. Also, fix a bug in LiveInterval::MergeInClobberRanges. It didn't handle the case that a clobber range extended both before and beyond an existing live range. In that case, multiple live ranges need to be added. This was exposed by the new subreg coalescing code. Remove 2008-05-06-SpillerBug.ll. It was bugpoint-reduced, and the spiller behavior it was looking for no longer occurrs with the new instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68576 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/subreg-to-reg-5.ll | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 test/CodeGen/X86/subreg-to-reg-5.ll (limited to 'test/CodeGen/X86/subreg-to-reg-5.ll') diff --git a/test/CodeGen/X86/subreg-to-reg-5.ll b/test/CodeGen/X86/subreg-to-reg-5.ll new file mode 100644 index 0000000..eee751a --- /dev/null +++ b/test/CodeGen/X86/subreg-to-reg-5.ll @@ -0,0 +1,34 @@ +; RUN: llvm-as < %s | llc -march=x86-64 > %t +; RUN: grep addl %t +; RUN: not egrep {movl|movq} %t + +define float @foo(float* %B) nounwind { +entry: + br label %bb2 + +bb2: ; preds = %bb3, %entry + %B_addr.0.rec = phi i64 [ %indvar.next154, %bb3 ], [ 0, %entry ] ; [#uses=2] + br i1 false, label %bb3, label %bb4 + +bb3: ; preds = %bb2 + %indvar.next154 = add i64 %B_addr.0.rec, 1 ; [#uses=1] + br label %bb2 + +bb4: ; preds = %bb2 + %B_addr.0 = getelementptr float* %B, i64 %B_addr.0.rec ; [#uses=1] + %t1 = ptrtoint float* %B_addr.0 to i64 ; [#uses=1] + %t2 = and i64 %t1, 15 ; [#uses=1] + %t3 = icmp eq i64 %t2, 0 ; [#uses=1] + br i1 %t3, label %bb5, label %bb10.preheader + +bb10.preheader: ; preds = %bb4 + br label %bb9 + +bb5: ; preds = %bb4 + unreachable + +bb9: ; preds = %bb10.preheader + %t5 = getelementptr float* %B, i64 0 ; [#uses=1] + %t7 = load float* %t5 ; [#uses=1] + ret float %t7 +} -- cgit v1.1