From 7e2ff77ef05c23db6b9c82bc7a4110e170d7f94c Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 8 May 2008 00:57:18 +0000 Subject: Handle vector move / load which zero the destination register top bits (i.e. movd, movq, movss (addr), movsd (addr)) with X86 specific dag combine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50838 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/vec_set-D.ll | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 test/CodeGen/X86/vec_set-D.ll (limited to 'test/CodeGen/X86/vec_set-D.ll') diff --git a/test/CodeGen/X86/vec_set-D.ll b/test/CodeGen/X86/vec_set-D.ll new file mode 100644 index 0000000..71bdd84 --- /dev/null +++ b/test/CodeGen/X86/vec_set-D.ll @@ -0,0 +1,7 @@ +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | grep movq + +define <4 x i32> @t(i32 %x, i32 %y) nounwind { + %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0 + %tmp2 = insertelement <4 x i32> %tmp1, i32 %y, i32 1 + ret <4 x i32> %tmp2 +} -- cgit v1.1