From 056c51e59820c4c36d3b9d2f22acb6fd121b798e Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Wed, 11 Apr 2012 22:13:04 +0000 Subject: Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154540 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/fcopysign-f32-f64.ll | 50 ++++++++++++++++++++ test/CodeGen/Mips/fcopysign.ll | 85 +++++++++++++++++----------------- 2 files changed, 92 insertions(+), 43 deletions(-) create mode 100644 test/CodeGen/Mips/fcopysign-f32-f64.ll (limited to 'test/CodeGen') diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll new file mode 100644 index 0000000..b36473d --- /dev/null +++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -0,0 +1,50 @@ +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2 + +declare double @copysign(double, double) nounwind readnone + +declare float @copysignf(float, float) nounwind readnone + +define float @func2(float %d, double %f) nounwind readnone { +entry: +; 64: func2 +; 64: lui $[[T0:[0-9]+]], 32767 +; 64: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 64: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 63 +; 64: sll $[[SLL:[0-9]+]], ${{[0-9]+}}, 31 +; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL]] +; 64: mtc1 $[[OR]], $f0 + +; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1 +; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1 +; 64R2: mtc1 $[[INS]], $f0 + + %add = fadd float %d, 1.000000e+00 + %conv = fptrunc double %f to float + %call = tail call float @copysignf(float %add, float %conv) nounwind readnone + ret float %call +} + +define double @func3(double %d, float %f) nounwind readnone { +entry: + +; 64: daddiu $[[T0:[0-9]+]], $zero, 1 +; 64: dsll $[[T1:[0-9]+]], $[[T0]], 63 +; 64: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1 +; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 64: srl ${{[0-9]+}}, ${{[0-9]+}}, 31 +; 64: dsll $[[DSLL:[0-9]+]], ${{[0-9]+}}, 63 +; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] +; 64: dmtc1 $[[OR]], $f0 + +; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1 +; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1 +; 64R2: dmtc1 $[[INS]], $f0 + + %add = fadd double %d, 1.000000e+00 + %conv = fpext float %f to double + %call = tail call double @copysign(double %add, double %conv) nounwind readnone + ret double %call +} + diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll index e494fe2..1c57eca 100644 --- a/test/CodeGen/Mips/fcopysign.ll +++ b/test/CodeGen/Mips/fcopysign.ll @@ -1,40 +1,35 @@ -; RUN: llc < %s -march=mipsel | FileCheck %s -check-prefix=MIPS32-EL -; RUN: llc < %s -march=mips | FileCheck %s -check-prefix=MIPS32-EB -; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=MIPS64 +; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=32 +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s -check-prefix=64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -mattr=n64 | FileCheck %s -check-prefix=64R2 define double @func0(double %d0, double %d1) nounwind readnone { entry: -; MIPS32-EL: func0: -; MIPS32-EL: mfc1 $[[HI0:[0-9]+]], $f15 -; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768 -; MIPS32-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]] -; MIPS32-EL: lui $[[T0:[0-9]+]], 32767 -; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 -; MIPS32-EL: mfc1 $[[HI1:[0-9]+]], $f13 -; MIPS32-EL: and $[[AND0:[0-9]+]], $[[HI1]], $[[MSK0]] -; MIPS32-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] -; MIPS32-EL: mfc1 $[[LO0:[0-9]+]], $f12 -; MIPS32-EL: mtc1 $[[LO0]], $f0 -; MIPS32-EL: mtc1 $[[OR]], $f1 ; -; MIPS32-EB: mfc1 $[[HI1:[0-9]+]], $f14 -; MIPS32-EB: lui $[[MSK1:[0-9]+]], 32768 -; MIPS32-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]] -; MIPS32-EB: lui $[[T0:[0-9]+]], 32767 -; MIPS32-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 -; MIPS32-EB: mfc1 $[[HI0:[0-9]+]], $f12 -; MIPS32-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]] -; MIPS32-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] -; MIPS32-EB: mfc1 $[[LO0:[0-9]+]], $f13 -; MIPS32-EB: mtc1 $[[OR]], $f0 -; MIPS32-EB: mtc1 $[[LO0]], $f1 - -; MIPS64: dmfc1 $[[R0:[0-9]+]], $f13 -; MIPS64: and $[[R1:[0-9]+]], $[[R0]], ${{[0-9]+}} -; MIPS64: dmfc1 $[[R2:[0-9]+]], $f12 -; MIPS64: and $[[R3:[0-9]+]], $[[R2]], ${{[0-9]+}} -; MIPS64: or $[[R4:[0-9]+]], $[[R3]], $[[R1]] -; MIPS64: dmtc1 $[[R4]], $f0 +; 32: lui $[[MSK1:[0-9]+]], 32768 +; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] +; 32: lui $[[T0:[0-9]+]], 32767 +; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] +; 32: mtc1 $[[OR]], $f1 + +; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1 +; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1 +; 32R2: mtc1 $[[INS]], $f1 + +; 64: daddiu $[[T0:[0-9]+]], $zero, 1 +; 64: dsll $[[MSK1:[0-9]+]], $[[T0]], 63 +; 64: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] +; 64: daddiu $[[MSK0:[0-9]+]], $[[MSK1]], -1 +; 64: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] +; 64: dmtc1 $[[OR]], $f0 + +; 64R2: dext $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 +; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1 +; 64R2: dmtc1 $[[INS]], $f0 + %call = tail call double @copysign(double %d0, double %d1) nounwind readnone ret double %call } @@ -43,18 +38,22 @@ declare double @copysign(double, double) nounwind readnone define float @func1(float %f0, float %f1) nounwind readnone { entry: -; MIPS32-EL: func1: -; MIPS32-EL: mfc1 $[[ARG1:[0-9]+]], $f14 -; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768 -; MIPS32-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]] -; MIPS32-EL: lui $[[T0:[0-9]+]], 32767 -; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 -; MIPS32-EL: mfc1 $[[ARG0:[0-9]+]], $f12 -; MIPS32-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]] -; MIPS32-EL: or $[[T4:[0-9]+]], $[[T2]], $[[T3]] -; MIPS32-EL: mtc1 $[[T4]], $f0 + +; 32: lui $[[MSK1:[0-9]+]], 32768 +; 32: and $[[AND1:[0-9]+]], ${{[0-9]+}}, $[[MSK1]] +; 32: lui $[[T0:[0-9]+]], 32767 +; 32: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; 32: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] +; 32: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] +; 32: mtc1 $[[OR]], $f0 + +; 32R2: ext $[[EXT:[0-9]+]], ${{[0-9]+}}, 31, 1 +; 32R2: ins $[[INS:[0-9]+]], $[[EXT]], 31, 1 +; 32R2: mtc1 $[[INS]], $f0 + %call = tail call float @copysignf(float %f0, float %f1) nounwind readnone ret float %call } declare float @copysignf(float, float) nounwind readnone + -- cgit v1.1