From 1518afddea6c0a4275a9ac64a9ffe2b6b4c0600a Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Mon, 18 Apr 2011 06:22:33 +0000 Subject: Implement major new fastisel functionality: the matcher can now handle immediates with value constraints on them (when defined as ImmLeaf's). This is particularly important for X86-64, where almost all reg/imm instructions take a i64immSExt32 immediate operand, which has a value constraint. Before this patch we ended up iseling the examples into such amazing code as: movabsq $7, %rax imulq %rax, %rdi movq %rdi, %rax ret now we produce: imulq $7, %rdi, %rax ret This dramatically shrinks the generated code at -O0 on x86-64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129691 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/X86/fast-isel-x86-64.ll | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'test/CodeGen') diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll index e74fd30..b666e84 100644 --- a/test/CodeGen/X86/fast-isel-x86-64.ll +++ b/test/CodeGen/X86/fast-isel-x86-64.ll @@ -93,3 +93,21 @@ entry: ; CHECK: leal (,%rdi,8), %eax } + +; rdar://9289507 - folding of immediates into 64-bit operations. +define i64 @test8(i64 %x) nounwind ssp { +entry: + %add = add nsw i64 %x, 7 + ret i64 %add + +; CHECK: test8: +; CHECK: addq $7, %rdi +} + +define i64 @test9(i64 %x) nounwind ssp { +entry: + %add = mul nsw i64 %x, 7 + ret i64 %add +; CHECK: test9: +; CHECK: imulq $7, %rdi, %rax +} -- cgit v1.1