From 6ff1ef9931b50763a40e9ae8696cfab9e25cf4de Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 30 Oct 2013 14:45:14 +0000 Subject: [mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193687 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/msa/bitwise.ll | 104 ++++++++++++++++++--- test/CodeGen/Mips/msa/i5-b.ll | 196 +++++++++++++++++++++++++-------------- 2 files changed, 216 insertions(+), 84 deletions(-) (limited to 'test/CodeGen') diff --git a/test/CodeGen/Mips/msa/bitwise.ll b/test/CodeGen/Mips/msa/bitwise.ll index a606fdf..d0b13f6 100644 --- a/test/CodeGen/Mips/msa/bitwise.ll +++ b/test/CodeGen/Mips/msa/bitwise.ll @@ -1054,6 +1054,90 @@ define void @bsel_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind { ; CHECK: .size bsel_v2i64 } +define void @binsl_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind { + ; CHECK: binsl_v16i8_i: + + %1 = load <16 x i8>* %a + ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5) + %2 = load <16 x i8>* %b + ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6) + %3 = and <16 x i8> %1, + %4 = and <16 x i8> %2, + %5 = or <16 x i8> %3, %4 + ; CHECK-DAG: binsli.b [[R2]], [[R1]], 2 + store <16 x i8> %5, <16 x i8>* %c + ; CHECK-DAG: st.b [[R2]], 0($4) + + ret void + ; CHECK: .size binsl_v16i8_i +} + +define void @binsl_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind { + ; CHECK: binsl_v8i16_i: + + %1 = load <8 x i16>* %a + ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5) + %2 = load <8 x i16>* %b + ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6) + %3 = and <8 x i16> %1, + %4 = and <8 x i16> %2, + %5 = or <8 x i16> %3, %4 + ; CHECK-DAG: binsli.h [[R2]], [[R1]], 2 + store <8 x i16> %5, <8 x i16>* %c + ; CHECK-DAG: st.h [[R2]], 0($4) + + ret void + ; CHECK: .size binsl_v8i16_i +} + +define void @binsl_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind { + ; CHECK: binsl_v4i32_i: + + %1 = load <4 x i32>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = load <4 x i32>* %b + ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6) + %3 = and <4 x i32> %1, + %4 = and <4 x i32> %2, + %5 = or <4 x i32> %3, %4 + ; CHECK-DAG: binsli.w [[R2]], [[R1]], 2 + store <4 x i32> %5, <4 x i32>* %c + ; CHECK-DAG: st.w [[R2]], 0($4) + + ret void + ; CHECK: .size binsl_v4i32_i +} + +define void @binsl_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind { + ; CHECK: binsl_v2i64_i: + + %1 = load <2 x i64>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = load <2 x i64>* %b + ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6) + %3 = and <2 x i64> %1, + %4 = and <2 x i64> %2, + %5 = or <2 x i64> %3, %4 + ; TODO: We use a particularly wide mask here to work around a legalization + ; issue. If the mask doesn't fit within a 10-bit immediate, it gets + ; legalized into a constant pool. We should add a test to cover the + ; other cases once they correctly select binsli.d. + ; CHECK-DAG: binsli.d [[R2]], [[R1]], 61 + store <2 x i64> %5, <2 x i64>* %c + ; CHECK-DAG: st.d [[R2]], 0($4) + + ret void + ; CHECK: .size binsl_v2i64_i +} + define void @binsr_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind { ; CHECK: binsr_v16i8_i: @@ -1068,10 +1152,9 @@ define void @binsr_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252, i8 252> %5 = or <16 x i8> %3, %4 - ; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 3 - ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + ; CHECK-DAG: binsri.b [[R2]], [[R1]], 2 store <16 x i8> %5, <16 x i8>* %c - ; CHECK-DAG: st.b [[R3]], 0($4) + ; CHECK-DAG: st.b [[R2]], 0($4) ret void ; CHECK: .size binsr_v16i8_i @@ -1089,10 +1172,9 @@ define void @binsr_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind %4 = and <8 x i16> %2, %5 = or <8 x i16> %3, %4 - ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 3 - ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + ; CHECK-DAG: binsri.h [[R2]], [[R1]], 2 store <8 x i16> %5, <8 x i16>* %c - ; CHECK-DAG: st.h [[R3]], 0($4) + ; CHECK-DAG: st.h [[R2]], 0($4) ret void ; CHECK: .size binsr_v8i16_i @@ -1108,10 +1190,9 @@ define void @binsr_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind %3 = and <4 x i32> %1, %4 = and <4 x i32> %2, %5 = or <4 x i32> %3, %4 - ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 3 - ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + ; CHECK-DAG: binsri.w [[R2]], [[R1]], 2 store <4 x i32> %5, <4 x i32>* %c - ; CHECK-DAG: st.w [[R3]], 0($4) + ; CHECK-DAG: st.w [[R2]], 0($4) ret void ; CHECK: .size binsr_v4i32_i @@ -1127,10 +1208,9 @@ define void @binsr_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind %3 = and <2 x i64> %1, %4 = and <2 x i64> %2, %5 = or <2 x i64> %3, %4 - ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 3 - ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]] + ; CHECK-DAG: binsri.d [[R2]], [[R1]], 2 store <2 x i64> %5, <2 x i64>* %c - ; CHECK-DAG: st.d [[R3]], 0($4) + ; CHECK-DAG: st.d [[R2]], 0($4) ret void ; CHECK: .size binsr_v2i64_i diff --git a/test/CodeGen/Mips/msa/i5-b.ll b/test/CodeGen/Mips/msa/i5-b.ll index 4362625..14f2066 100644 --- a/test/CodeGen/Mips/msa/i5-b.ll +++ b/test/CodeGen/Mips/msa/i5-b.ll @@ -79,158 +79,210 @@ declare <2 x i64> @llvm.mips.bclri.d(<2 x i64>, i32) nounwind ; CHECK: st.d ; CHECK: .size llvm_mips_bclri_d_test ; -@llvm_mips_binsli_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_binsli_b_RES = global <16 x i8> , align 16 +@llvm_mips_binsli_b_ARG1 = global <16 x i8> zeroinitializer, align 16 +@llvm_mips_binsli_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_binsli_b_RES = global <16 x i8> zeroinitializer, align 16 define void @llvm_mips_binsli_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_binsli_b_ARG1 - %1 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, i32 7) - store <16 x i8> %1, <16 x i8>* @llvm_mips_binsli_b_RES + %1 = load <16 x i8>* @llvm_mips_binsli_b_ARG2 + %2 = tail call <16 x i8> @llvm.mips.binsli.b(<16 x i8> %0, <16 x i8> %1, i32 7) + store <16 x i8> %2, <16 x i8>* @llvm_mips_binsli_b_RES ret void } -declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, i32) nounwind +declare <16 x i8> @llvm.mips.binsli.b(<16 x i8>, <16 x i8>, i32) nounwind ; CHECK: llvm_mips_binsli_b_test: -; CHECK: ld.b -; CHECK: binsli.b -; CHECK: st.b +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_b_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_b_ARG2)( +; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: binsli.b [[R3]], [[R4]], 7 +; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_b_RES)( +; CHECK-DAG: st.b [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsli_b_test -; -@llvm_mips_binsli_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_binsli_h_RES = global <8 x i16> , align 16 + +@llvm_mips_binsli_h_ARG1 = global <8 x i16> zeroinitializer, align 16 +@llvm_mips_binsli_h_ARG2 = global <8 x i16> , align 16 +@llvm_mips_binsli_h_RES = global <8 x i16> zeroinitializer, align 16 define void @llvm_mips_binsli_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_binsli_h_ARG1 - %1 = tail call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %0, i32 7) - store <8 x i16> %1, <8 x i16>* @llvm_mips_binsli_h_RES + %1 = load <8 x i16>* @llvm_mips_binsli_h_ARG2 + %2 = tail call <8 x i16> @llvm.mips.binsli.h(<8 x i16> %0, <8 x i16> %1, i32 7) + store <8 x i16> %2, <8 x i16>* @llvm_mips_binsli_h_RES ret void } -declare <8 x i16> @llvm.mips.binsli.h(<8 x i16>, i32) nounwind +declare <8 x i16> @llvm.mips.binsli.h(<8 x i16>, <8 x i16>, i32) nounwind ; CHECK: llvm_mips_binsli_h_test: -; CHECK: ld.h -; CHECK: binsli.h -; CHECK: st.h +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_h_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_h_ARG2)( +; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: binsli.h [[R3]], [[R4]], 7 +; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_h_RES)( +; CHECK-DAG: st.h [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsli_h_test -; -@llvm_mips_binsli_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_binsli_w_RES = global <4 x i32> , align 16 + +@llvm_mips_binsli_w_ARG1 = global <4 x i32> zeroinitializer, align 16 +@llvm_mips_binsli_w_ARG2 = global <4 x i32> , align 16 +@llvm_mips_binsli_w_RES = global <4 x i32> zeroinitializer, align 16 define void @llvm_mips_binsli_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_binsli_w_ARG1 - %1 = tail call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %0, i32 7) - store <4 x i32> %1, <4 x i32>* @llvm_mips_binsli_w_RES + %1 = load <4 x i32>* @llvm_mips_binsli_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.binsli.w(<4 x i32> %0, <4 x i32> %1, i32 7) + store <4 x i32> %2, <4 x i32>* @llvm_mips_binsli_w_RES ret void } -declare <4 x i32> @llvm.mips.binsli.w(<4 x i32>, i32) nounwind +declare <4 x i32> @llvm.mips.binsli.w(<4 x i32>, <4 x i32>, i32) nounwind ; CHECK: llvm_mips_binsli_w_test: -; CHECK: ld.w -; CHECK: binsli.w -; CHECK: st.w +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_w_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_w_ARG2)( +; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: binsli.w [[R3]], [[R4]], 7 +; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_w_RES)( +; CHECK-DAG: st.w [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsli_w_test -; -@llvm_mips_binsli_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_binsli_d_RES = global <2 x i64> , align 16 + +@llvm_mips_binsli_d_ARG1 = global <2 x i64> zeroinitializer, align 16 +@llvm_mips_binsli_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_binsli_d_RES = global <2 x i64> zeroinitializer, align 16 define void @llvm_mips_binsli_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_binsli_d_ARG1 - %1 = tail call <2 x i64> @llvm.mips.binsli.d(<2 x i64> %0, i32 7) - store <2 x i64> %1, <2 x i64>* @llvm_mips_binsli_d_RES + %1 = load <2 x i64>* @llvm_mips_binsli_d_ARG2 + ; TODO: We use a particularly wide mask here to work around a legalization + ; issue. If the mask doesn't fit within a 10-bit immediate, it gets + ; legalized into a constant pool. We should add a test to cover the + ; other cases once they correctly select binsli.d. + %2 = tail call <2 x i64> @llvm.mips.binsli.d(<2 x i64> %0, <2 x i64> %1, i32 61) + store <2 x i64> %2, <2 x i64>* @llvm_mips_binsli_d_RES ret void } -declare <2 x i64> @llvm.mips.binsli.d(<2 x i64>, i32) nounwind +declare <2 x i64> @llvm.mips.binsli.d(<2 x i64>, <2 x i64>, i32) nounwind ; CHECK: llvm_mips_binsli_d_test: -; CHECK: ld.d -; CHECK: binsli.d -; CHECK: st.d +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsli_d_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsli_d_ARG2)( +; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: binsli.d [[R3]], [[R4]], 61 +; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsli_d_RES)( +; CHECK-DAG: st.d [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsli_d_test -; -@llvm_mips_binsri_b_ARG1 = global <16 x i8> , align 16 -@llvm_mips_binsri_b_RES = global <16 x i8> , align 16 + +@llvm_mips_binsri_b_ARG1 = global <16 x i8> zeroinitializer, align 16 +@llvm_mips_binsri_b_ARG2 = global <16 x i8> , align 16 +@llvm_mips_binsri_b_RES = global <16 x i8> zeroinitializer, align 16 define void @llvm_mips_binsri_b_test() nounwind { entry: %0 = load <16 x i8>* @llvm_mips_binsri_b_ARG1 - %1 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, i32 7) - store <16 x i8> %1, <16 x i8>* @llvm_mips_binsri_b_RES + %1 = load <16 x i8>* @llvm_mips_binsri_b_ARG2 + %2 = tail call <16 x i8> @llvm.mips.binsri.b(<16 x i8> %0, <16 x i8> %1, i32 7) + store <16 x i8> %2, <16 x i8>* @llvm_mips_binsri_b_RES ret void } -declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, i32) nounwind +declare <16 x i8> @llvm.mips.binsri.b(<16 x i8>, <16 x i8>, i32) nounwind ; CHECK: llvm_mips_binsri_b_test: -; CHECK: ld.b -; CHECK: binsri.b -; CHECK: st.b +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_b_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_b_ARG2)( +; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: binsri.b [[R3]], [[R4]], 7 +; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_b_RES)( +; CHECK-DAG: st.b [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsri_b_test -; -@llvm_mips_binsri_h_ARG1 = global <8 x i16> , align 16 -@llvm_mips_binsri_h_RES = global <8 x i16> , align 16 + +@llvm_mips_binsri_h_ARG1 = global <8 x i16> zeroinitializer, align 16 +@llvm_mips_binsri_h_ARG2 = global <8 x i16> , align 16 +@llvm_mips_binsri_h_RES = global <8 x i16> zeroinitializer, align 16 define void @llvm_mips_binsri_h_test() nounwind { entry: %0 = load <8 x i16>* @llvm_mips_binsri_h_ARG1 - %1 = tail call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %0, i32 7) - store <8 x i16> %1, <8 x i16>* @llvm_mips_binsri_h_RES + %1 = load <8 x i16>* @llvm_mips_binsri_h_ARG2 + %2 = tail call <8 x i16> @llvm.mips.binsri.h(<8 x i16> %0, <8 x i16> %1, i32 7) + store <8 x i16> %2, <8 x i16>* @llvm_mips_binsri_h_RES ret void } -declare <8 x i16> @llvm.mips.binsri.h(<8 x i16>, i32) nounwind +declare <8 x i16> @llvm.mips.binsri.h(<8 x i16>, <8 x i16>, i32) nounwind ; CHECK: llvm_mips_binsri_h_test: -; CHECK: ld.h -; CHECK: binsri.h -; CHECK: st.h +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_h_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_h_ARG2)( +; CHECK-DAG: ld.h [[R3:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.h [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: binsri.h [[R3]], [[R4]], 7 +; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_h_RES)( +; CHECK-DAG: st.h [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsri_h_test -; -@llvm_mips_binsri_w_ARG1 = global <4 x i32> , align 16 -@llvm_mips_binsri_w_RES = global <4 x i32> , align 16 + +@llvm_mips_binsri_w_ARG1 = global <4 x i32> zeroinitializer, align 16 +@llvm_mips_binsri_w_ARG2 = global <4 x i32> , align 16 +@llvm_mips_binsri_w_RES = global <4 x i32> zeroinitializer, align 16 define void @llvm_mips_binsri_w_test() nounwind { entry: %0 = load <4 x i32>* @llvm_mips_binsri_w_ARG1 - %1 = tail call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %0, i32 7) - store <4 x i32> %1, <4 x i32>* @llvm_mips_binsri_w_RES + %1 = load <4 x i32>* @llvm_mips_binsri_w_ARG2 + %2 = tail call <4 x i32> @llvm.mips.binsri.w(<4 x i32> %0, <4 x i32> %1, i32 7) + store <4 x i32> %2, <4 x i32>* @llvm_mips_binsri_w_RES ret void } -declare <4 x i32> @llvm.mips.binsri.w(<4 x i32>, i32) nounwind +declare <4 x i32> @llvm.mips.binsri.w(<4 x i32>, <4 x i32>, i32) nounwind ; CHECK: llvm_mips_binsri_w_test: -; CHECK: ld.w -; CHECK: binsri.w -; CHECK: st.w +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_w_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_w_ARG2)( +; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.w [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: binsri.w [[R3]], [[R4]], 7 +; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_w_RES)( +; CHECK-DAG: st.w [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsri_w_test -; -@llvm_mips_binsri_d_ARG1 = global <2 x i64> , align 16 -@llvm_mips_binsri_d_RES = global <2 x i64> , align 16 + +@llvm_mips_binsri_d_ARG1 = global <2 x i64> zeroinitializer, align 16 +@llvm_mips_binsri_d_ARG2 = global <2 x i64> , align 16 +@llvm_mips_binsri_d_RES = global <2 x i64> zeroinitializer, align 16 define void @llvm_mips_binsri_d_test() nounwind { entry: %0 = load <2 x i64>* @llvm_mips_binsri_d_ARG1 - %1 = tail call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %0, i32 7) - store <2 x i64> %1, <2 x i64>* @llvm_mips_binsri_d_RES + %1 = load <2 x i64>* @llvm_mips_binsri_d_ARG2 + %2 = tail call <2 x i64> @llvm.mips.binsri.d(<2 x i64> %0, <2 x i64> %1, i32 7) + store <2 x i64> %2, <2 x i64>* @llvm_mips_binsri_d_RES ret void } -declare <2 x i64> @llvm.mips.binsri.d(<2 x i64>, i32) nounwind +declare <2 x i64> @llvm.mips.binsri.d(<2 x i64>, <2 x i64>, i32) nounwind ; CHECK: llvm_mips_binsri_d_test: -; CHECK: ld.d -; CHECK: binsri.d -; CHECK: st.d +; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_binsri_d_ARG1)( +; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_binsri_d_ARG2)( +; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0([[R1]]) +; CHECK-DAG: ld.d [[R4:\$w[0-9]+]], 0([[R2]]) +; CHECK-DAG: binsri.d [[R3]], [[R4]], 7 +; CHECK-DAG: lw [[R5:\$[0-9]+]], %got(llvm_mips_binsri_d_RES)( +; CHECK-DAG: st.d [[R3]], 0([[R5]]) ; CHECK: .size llvm_mips_binsri_d_test -; + @llvm_mips_bnegi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bnegi_b_RES = global <16 x i8> , align 16 -- cgit v1.1