From ae692f2baedf53504af2715993b166950e185a55 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Mon, 12 Nov 2012 19:28:57 +0000 Subject: misched: Infrastructure for weak DAG edges. This adds support for weak DAG edges to the general scheduling infrastructure in preparation for MachineScheduler support for heuristics based on weak edges. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167738 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll | 2 ++ 1 file changed, 2 insertions(+) (limited to 'test/CodeGen') diff --git a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index b05ec63..ca0964a 100644 --- a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -13,6 +13,7 @@ ; CHECK-NOT: ch SU ; CHECK: ch SU(2): Latency=1 ; CHECK-NOT: ch SU +; CHECK: Successors: ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}} ; CHECK-NOT: ch SU @@ -22,6 +23,7 @@ ; CHECK-NOT: ch SU ; CHECK: ch SU(2): Latency=1 ; CHECK-NOT: ch SU +; CHECK: Successors: define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: store volatile i32 65540, i32* %p1, align 4, !tbaa !0 -- cgit v1.1