From ebe69fe11e48d322045d5949c83283927a0d790b Mon Sep 17 00:00:00 2001 From: Stephen Hines Date: Mon, 23 Mar 2015 12:10:34 -0700 Subject: Update aosp/master LLVM for rebase to r230699. Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9 --- .../aarch64-2014-08-11-MachineCombinerCrash.ll | 122 +- .../AArch64/aarch64-2014-12-02-combine-soften.ll | 16 + test/CodeGen/AArch64/addsub-shifted.ll | 14 +- test/CodeGen/AArch64/analyze-branch.ll | 4 +- test/CodeGen/AArch64/analyzecmp.ll | 8 +- test/CodeGen/AArch64/argument-blocks.ll | 197 ++ .../AArch64/arm64-2011-03-17-AsmPrinterCrash.ll | 46 +- .../CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll | 10 +- test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll | 8 +- test/CodeGen/AArch64/arm64-aapcs-be.ll | 18 +- test/CodeGen/AArch64/arm64-abi_align.ll | 10 +- test/CodeGen/AArch64/arm64-atomic-128.ll | 24 +- test/CodeGen/AArch64/arm64-ccmp-heuristics.ll | 8 +- test/CodeGen/AArch64/arm64-cse.ll | 2 +- test/CodeGen/AArch64/arm64-fastcc-tailcall.ll | 6 +- .../arm64-fixed-point-scalar-cvt-dagcombine.ll | 2 +- test/CodeGen/AArch64/arm64-fold-address.ll | 10 +- .../CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll | 8 +- test/CodeGen/AArch64/arm64-ldp.ll | 85 + test/CodeGen/AArch64/arm64-named-reg-alloc.ll | 2 +- test/CodeGen/AArch64/arm64-named-reg-notareg.ll | 2 +- test/CodeGen/AArch64/arm64-neon-copy.ll | 2 +- test/CodeGen/AArch64/arm64-neon-select_cc.ll | 15 + test/CodeGen/AArch64/arm64-platform-reg.ll | 15 +- test/CodeGen/AArch64/arm64-popcnt.ll | 20 +- test/CodeGen/AArch64/arm64-prefetch.ll | 8 +- test/CodeGen/AArch64/arm64-promote-const.ll | 118 +- test/CodeGen/AArch64/arm64-st1.ll | 192 ++ test/CodeGen/AArch64/arm64-stackmap-nops.ll | 15 + test/CodeGen/AArch64/arm64-stackpointer.ll | 2 +- test/CodeGen/AArch64/arm64-tls-dynamics.ll | 8 +- .../AArch64/arm64-triv-disjoint-mem-access.ll | 14 +- test/CodeGen/AArch64/arm64-variadic-aapcs.ll | 16 +- test/CodeGen/AArch64/arm64-vshuffle.ll | 26 +- test/CodeGen/AArch64/bitcast-v2i8.ll | 15 + test/CodeGen/AArch64/br-to-eh-lpad.ll | 78 + test/CodeGen/AArch64/combine-comparisons-by-cse.ll | 1 - test/CodeGen/AArch64/compiler-ident.ll | 2 +- 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test/CodeGen/AArch64/setcc-type-mismatch.ll | 11 + test/CodeGen/ARM/2007-05-09-tailmerge-2.ll | 9 +- test/CodeGen/ARM/2007-05-22-tailmerge-3.ll | 23 +- test/CodeGen/ARM/2009-10-16-Scope.ll | 22 +- test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll | 34 +- .../ARM/2010-06-25-Thumb2ITInvalidIterator.ll | 62 +- test/CodeGen/ARM/2010-08-04-StackVariable.ll | 110 +- test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll | 120 +- test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll | 2 +- .../ARM/2011-05-04-MultipleLandingPadSuccs.ll | 10 +- test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll | 114 +- test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll | 8 +- test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll | 2 +- .../ARM/2012-09-25-InlineAsmScalarToVectorConv.ll | 2 +- .../ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll | 2 +- test/CodeGen/ARM/2014-08-04-muls-it.ll | 4 +- test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll | 48 + test/CodeGen/ARM/Windows/read-only-data.ll | 2 +- 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test/CodeGen/ARM/named-reg-alloc.ll | 2 +- test/CodeGen/ARM/named-reg-notareg.ll | 2 +- test/CodeGen/ARM/none-macho-v4t.ll | 8 +- test/CodeGen/ARM/null-streamer.ll | 2 + test/CodeGen/ARM/odr_comdat.ll | 16 - test/CodeGen/ARM/out-of-registers.ll | 4 +- test/CodeGen/ARM/section-name.ll | 2 +- test/CodeGen/ARM/setcc-type-mismatch.ll | 11 + test/CodeGen/ARM/sjlj-prepare-critical-edge.ll | 128 +- test/CodeGen/ARM/spill-q.ll | 2 +- test/CodeGen/ARM/stack-alignment.ll | 164 ++ test/CodeGen/ARM/stack_guard_remat.ll | 2 +- test/CodeGen/ARM/stackpointer.ll | 2 +- test/CodeGen/ARM/sub-cmp-peephole.ll | 60 + test/CodeGen/ARM/tail-call-weak.ll | 19 + test/CodeGen/ARM/tail-call.ll | 5 +- test/CodeGen/ARM/tail-merge-branch-weight.ll | 6 +- test/CodeGen/ARM/taildup-branch-weight.ll | 4 +- test/CodeGen/ARM/thumb1-varalloc.ll | 32 +- test/CodeGen/ARM/thumb1_return_sequence.ll | 48 +- test/CodeGen/ARM/thumb_indirect_calls.ll | 40 + test/CodeGen/ARM/tls1.ll | 14 +- test/CodeGen/ARM/vdup.ll | 6 +- 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test/CodeGen/X86/atomic16.ll | 24 +- test/CodeGen/X86/avx-cvt.ll | 17 + test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll | 14 + test/CodeGen/X86/avx-intrinsics-x86.ll | 32 - test/CodeGen/X86/avx-splat.ll | 6 +- test/CodeGen/X86/avx-trunc.ll | 6 +- test/CodeGen/X86/avx-vperm2x128.ll | 19 +- test/CodeGen/X86/avx.ll | 2 +- test/CodeGen/X86/avx1-stack-reload-folding.ll | 68 - test/CodeGen/X86/avx2-conversions.ll | 2 +- test/CodeGen/X86/avx2-gather.ll | 27 + test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll | 31 + test/CodeGen/X86/avx2-intrinsics-x86.ll | 32 - test/CodeGen/X86/avx2-nontemporal.ll | 2 +- test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll | 110 + test/CodeGen/X86/avx2-vbroadcast.ll | 2 +- test/CodeGen/X86/avx512-arith.ll | 190 ++ test/CodeGen/X86/avx512-fma-intrinsics.ll | 351 +++ test/CodeGen/X86/avx512-i1test.ll | 45 + test/CodeGen/X86/avx512-insert-extract.ll | 19 +- test/CodeGen/X86/avx512-intel-ocl.ll | 105 + test/CodeGen/X86/avx512-intrinsics.ll | 692 ++++- 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test/CodeGen/X86/break-sse-dep.ll | 62 - test/CodeGen/X86/bswap-vector.ll | 366 ++- test/CodeGen/X86/chain_order.ll | 16 +- test/CodeGen/X86/clobber-fi0.ll | 2 +- test/CodeGen/X86/cmov.ll | 2 +- test/CodeGen/X86/cmpxchg-clobber-flags.ll | 29 +- test/CodeGen/X86/coalesce_commute_subreg.ll | 51 + test/CodeGen/X86/coalescer-dce.ll | 2 +- test/CodeGen/X86/codegen-prepare-extload.ll | 348 ++- test/CodeGen/X86/coff-comdat.ll | 50 +- test/CodeGen/X86/coff-comdat2.ll | 2 +- test/CodeGen/X86/coff-comdat3.ll | 2 +- test/CodeGen/X86/combine-and.ll | 148 +- test/CodeGen/X86/combine-or.ll | 46 +- test/CodeGen/X86/commute-clmul.ll | 60 + test/CodeGen/X86/commute-fcmp.ll | 340 +++ test/CodeGen/X86/commute-xop.ll | 184 ++ test/CodeGen/X86/compact-unwind.ll | 88 +- test/CodeGen/X86/constant-combines.ll | 35 + test/CodeGen/X86/constant-hoisting-optnone.ll | 21 + test/CodeGen/X86/copysign-constant-magnitude.ll | 105 + test/CodeGen/X86/copysign-zero.ll | 14 - test/CodeGen/X86/cppeh-catch-all.ll | 83 + test/CodeGen/X86/cppeh-catch-scalar.ll | 123 + test/CodeGen/X86/cppeh-frame-vars.ll | 261 ++ test/CodeGen/X86/cpus.ll | 35 + test/CodeGen/X86/crash-O0.ll | 22 +- test/CodeGen/X86/crash.ll | 4 +- .../X86/dbg-changes-codegen-branch-folding.ll | 214 +- test/CodeGen/X86/dbg-changes-codegen.ll | 14 +- test/CodeGen/X86/dbg-combine.ll | 113 + test/CodeGen/X86/dllexport-x86_64.ll | 7 +- test/CodeGen/X86/dllexport.ll | 12 +- test/CodeGen/X86/dwarf-comp-dir.ll | 14 +- test/CodeGen/X86/dwarf-eh-prepare.ll | 51 + test/CodeGen/X86/elf-comdat.ll | 4 +- test/CodeGen/X86/elf-comdat2.ll | 2 +- test/CodeGen/X86/equiv_with_fndef.ll | 10 + test/CodeGen/X86/equiv_with_vardef.ll | 8 + test/CodeGen/X86/extractelement-load.ll | 14 +- test/CodeGen/X86/f16c-intrinsics.ll | 17 + test/CodeGen/X86/fast-isel-branch_weights.ll | 2 +- test/CodeGen/X86/fast-isel-call-bool.ll | 18 + test/CodeGen/X86/fast-isel-cmp-branch.ll | 2 +- .../X86/fast-isel-double-half-convertion.ll | 23 + .../CodeGen/X86/fast-isel-float-half-convertion.ll | 28 + test/CodeGen/X86/fast-isel-fptrunc-fpext.ll | 65 + test/CodeGen/X86/fast-isel-gep.ll | 2 +- test/CodeGen/X86/fast-isel-int-float-conversion.ll | 45 + test/CodeGen/X86/fastmath-float-half-conversion.ll | 52 + test/CodeGen/X86/float-conv-elim.ll | 32 + test/CodeGen/X86/fold-load-unops.ll | 57 + test/CodeGen/X86/fold-tied-op.ll | 168 +- test/CodeGen/X86/fold-vex.ll | 39 +- test/CodeGen/X86/force-align-stack-alloca.ll | 4 +- test/CodeGen/X86/fp-double-rounding.ll | 31 + test/CodeGen/X86/fpstack-debuginstr-kill.ll | 54 +- test/CodeGen/X86/frameaddr.ll | 28 +- test/CodeGen/X86/frameallocate.ll | 43 + test/CodeGen/X86/gather-addresses.ll | 83 +- test/CodeGen/X86/gcc_except_table.ll | 2 +- test/CodeGen/X86/ghc-cc.ll | 10 +- test/CodeGen/X86/ghc-cc64.ll | 10 +- test/CodeGen/X86/global-sections-comdat.ll | 46 + test/CodeGen/X86/global-sections.ll | 92 +- test/CodeGen/X86/hoist-invariant-load.ll | 2 +- test/CodeGen/X86/huge-stack-offset.ll | 59 + test/CodeGen/X86/i1narrowfail.ll | 10 + test/CodeGen/X86/ident-metadata.ll | 4 +- test/CodeGen/X86/imul.ll | 110 + test/CodeGen/X86/imul64-lea.ll | 25 - test/CodeGen/X86/inalloca-ctor.ll | 8 +- test/CodeGen/X86/inalloca-invoke.ll | 4 +- test/CodeGen/X86/inalloca-stdcall.ll | 3 +- test/CodeGen/X86/init-priority.ll | 51 + test/CodeGen/X86/inline-asm-flag-clobber.ll | 2 +- test/CodeGen/X86/insertps-O0-bug.ll | 52 + test/CodeGen/X86/large-code-model-isel.ll | 13 + test/CodeGen/X86/lea-2.ll | 2 +- test/CodeGen/X86/logical-load-fold.ll | 53 + test/CodeGen/X86/lower-vec-shift-2.ll | 157 ++ test/CodeGen/X86/lzcnt-tzcnt.ll | 131 + test/CodeGen/X86/macho-comdat.ll | 2 +- test/CodeGen/X86/masked_memop.ll | 219 ++ test/CodeGen/X86/mem-intrin-base-reg.ll | 2 +- .../X86/misched-code-difference-with-debug.ll | 90 + test/CodeGen/X86/misched-copy.ll | 8 +- test/CodeGen/X86/misched-crash.ll | 2 +- test/CodeGen/X86/mmx-arg-passing-x86-64.ll | 56 + test/CodeGen/X86/mmx-arg-passing.ll | 45 +- test/CodeGen/X86/mmx-arg-passing2.ll | 28 - test/CodeGen/X86/mmx-arith.ll | 543 ++-- test/CodeGen/X86/mmx-bitcast-to-i64.ll | 31 - test/CodeGen/X86/mmx-bitcast.ll | 109 + test/CodeGen/X86/mmx-builtins.ll | 1349 ---------- test/CodeGen/X86/mmx-emms.ll | 11 - test/CodeGen/X86/mmx-fold-load.ll | 282 ++ test/CodeGen/X86/mmx-insert-element.ll | 9 - test/CodeGen/X86/mmx-intrinsics.ll | 1358 ++++++++++ test/CodeGen/X86/mmx-pinsrw.ll | 17 - test/CodeGen/X86/mmx-punpckhdq.ll | 31 - test/CodeGen/X86/mmx-s2v.ll | 15 - test/CodeGen/X86/mmx-shift.ll | 39 - test/CodeGen/X86/mmx-shuffle.ll | 31 - test/CodeGen/X86/movntdq-no-avx.ll | 2 +- test/CodeGen/X86/movtopush.ll | 346 +++ test/CodeGen/X86/musttail-fastcall.ll | 109 + test/CodeGen/X86/musttail-varargs.ll | 21 + test/CodeGen/X86/named-reg-alloc.ll | 2 +- test/CodeGen/X86/named-reg-notareg.ll | 2 +- test/CodeGen/X86/no-compact-unwind.ll | 64 - test/CodeGen/X86/non-unique-sections.ll | 15 + test/CodeGen/X86/nontemporal-2.ll | 2 +- test/CodeGen/X86/nontemporal.ll | 2 +- test/CodeGen/X86/norex-subreg.ll | 4 +- test/CodeGen/X86/nosse-varargs.ll | 7 +- test/CodeGen/X86/null-streamer.ll | 26 +- test/CodeGen/X86/objc-gc-module-flags.ll | 8 +- test/CodeGen/X86/odr_comdat.ll | 16 - test/CodeGen/X86/palignr.ll | 4 +- test/CodeGen/X86/peep-test-2.ll | 2 +- test/CodeGen/X86/phys_subreg_coalesce-3.ll | 2 +- test/CodeGen/X86/pic_jumptable.ll | 2 +- test/CodeGen/X86/pmul.ll | 121 +- test/CodeGen/X86/pointer-vector.ll | 3 +- test/CodeGen/X86/pr11468.ll | 2 +- test/CodeGen/X86/pr12360.ll | 2 +- test/CodeGen/X86/pr15267.ll | 75 +- test/CodeGen/X86/pr18846.ll | 12 +- test/CodeGen/X86/pr21792.ll | 41 + test/CodeGen/X86/pr22019.ll | 23 + test/CodeGen/X86/pr22103.ll | 19 + test/CodeGen/X86/pre-ra-sched.ll | 2 +- test/CodeGen/X86/prefixdata.ll | 9 +- test/CodeGen/X86/prologuedata.ll | 17 + test/CodeGen/X86/pshufb-mask-comments.ll | 22 + test/CodeGen/X86/psubus.ll | 316 +-- test/CodeGen/X86/ragreedy-bug.ll | 48 +- test/CodeGen/X86/ragreedy-hoist-spill.ll | 19 +- .../CodeGen/X86/regalloc-reconcile-broken-hints.ll | 145 + test/CodeGen/X86/remat-phys-dead.ll | 2 +- test/CodeGen/X86/scalar_sse_minmax.ll | 61 +- test/CodeGen/X86/scev-interchange.ll | 2 +- test/CodeGen/X86/segmented-stacks.ll | 123 + test/CodeGen/X86/seh-basic.ll | 175 ++ test/CodeGen/X86/seh-catch-all.ll | 33 + test/CodeGen/X86/seh-filter.ll | 21 + test/CodeGen/X86/seh-finally.ll | 45 + test/CodeGen/X86/seh-safe-div.ll | 197 ++ test/CodeGen/X86/selectiondag-crash.ll | 15 + test/CodeGen/X86/shrink-compare.ll | 148 ++ test/CodeGen/X86/sibcall-4.ll | 4 +- test/CodeGen/X86/sibcall-5.ll | 2 +- test/CodeGen/X86/sibcall-win64.ll | 42 + test/CodeGen/X86/sibcall.ll | 87 +- test/CodeGen/X86/sincos-opt.ll | 5 +- test/CodeGen/X86/sink-blockfreq.ll | 6 +- test/CodeGen/X86/sink-hoist.ll | 2 +- test/CodeGen/X86/sjlj-baseptr.ll | 37 + test/CodeGen/X86/slow-div.ll | 28 + test/CodeGen/X86/slow-incdec.ll | 8 +- test/CodeGen/X86/small-byval-memcpy.ll | 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test/CodeGen/X86/stack-probe-size.ll | 78 + test/CodeGen/X86/stack-protector-dbginfo.ll | 144 +- test/CodeGen/X86/stack-protector-weight.ll | 36 + test/CodeGen/X86/stackpointer.ll | 2 +- test/CodeGen/X86/statepoint-call-lowering.ll | 104 + test/CodeGen/X86/statepoint-forward.ll | 107 + test/CodeGen/X86/statepoint-stack-usage.ll | 60 + test/CodeGen/X86/statepoint-stackmap-format.ll | 109 + test/CodeGen/X86/switch-bt.ll | 58 + test/CodeGen/X86/switch-default-only.ll | 14 + test/CodeGen/X86/switch-jump-table.ll | 52 + test/CodeGen/X86/tail-call-win64.ll | 36 + test/CodeGen/X86/tailcall-64.ll | 4 +- test/CodeGen/X86/tailcall-returndup-void.ll | 10 +- test/CodeGen/X86/tls-models.ll | 8 + test/CodeGen/X86/trap.ll | 20 +- test/CodeGen/X86/uint_to_fp-2.ll | 2 +- test/CodeGen/X86/unaligned-32-byte-memops.ll | 288 ++ test/CodeGen/X86/unknown-location.ll | 26 +- test/CodeGen/X86/utf16-cfstrings.ll | 8 +- test/CodeGen/X86/v2f32.ll | 6 +- test/CodeGen/X86/vaargs.ll | 2 +- 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create mode 100644 test/CodeGen/X86/pr21792.ll create mode 100644 test/CodeGen/X86/pr22019.ll create mode 100644 test/CodeGen/X86/pr22103.ll create mode 100644 test/CodeGen/X86/prologuedata.ll create mode 100644 test/CodeGen/X86/regalloc-reconcile-broken-hints.ll create mode 100644 test/CodeGen/X86/seh-basic.ll create mode 100644 test/CodeGen/X86/seh-catch-all.ll create mode 100644 test/CodeGen/X86/seh-filter.ll create mode 100755 test/CodeGen/X86/seh-finally.ll create mode 100644 test/CodeGen/X86/seh-safe-div.ll create mode 100644 test/CodeGen/X86/selectiondag-crash.ll create mode 100644 test/CodeGen/X86/sibcall-win64.ll create mode 100644 test/CodeGen/X86/sjlj-baseptr.ll create mode 100644 test/CodeGen/X86/slow-div.ll create mode 100644 test/CodeGen/X86/splat-const.ll create mode 100644 test/CodeGen/X86/sret-implicit.ll create mode 100644 test/CodeGen/X86/sse-unaligned-mem-feature.ll create mode 100644 test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll create mode 100644 test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll create mode 100644 test/CodeGen/X86/stack-folding-fp-avx1.ll create mode 100644 test/CodeGen/X86/stack-folding-fp-sse42.ll create mode 100644 test/CodeGen/X86/stack-folding-int-avx1.ll create mode 100644 test/CodeGen/X86/stack-folding-int-avx2.ll create mode 100644 test/CodeGen/X86/stack-folding-int-sse42.ll create mode 100644 test/CodeGen/X86/stack-folding-xop.ll create mode 100644 test/CodeGen/X86/stack-probe-size.ll create mode 100644 test/CodeGen/X86/stack-protector-weight.ll create mode 100644 test/CodeGen/X86/statepoint-call-lowering.ll create mode 100644 test/CodeGen/X86/statepoint-forward.ll create mode 100644 test/CodeGen/X86/statepoint-stack-usage.ll create mode 100644 test/CodeGen/X86/statepoint-stackmap-format.ll create mode 100644 test/CodeGen/X86/switch-default-only.ll create mode 100644 test/CodeGen/X86/switch-jump-table.ll create mode 100644 test/CodeGen/X86/tail-call-win64.ll create mode 100644 test/CodeGen/X86/unaligned-32-byte-memops.ll create mode 100644 test/CodeGen/X86/vec-loadsingles-alignment.ll delete mode 100644 test/CodeGen/X86/vec_clear.ll create mode 100644 test/CodeGen/X86/vec_extract-avx.ll create mode 100644 test/CodeGen/X86/vec_extract-mmx.ll create mode 100644 test/CodeGen/X86/vec_insert-mmx.ll create mode 100644 test/CodeGen/X86/vector-ctpop.ll create mode 100644 test/CodeGen/X86/vector-shuffle-512-v16.ll create mode 100644 test/CodeGen/X86/vector-shuffle-mmx.ll create mode 100644 test/CodeGen/X86/vector-trunc.ll create mode 100644 test/CodeGen/X86/vector-zmov.ll create mode 100644 test/CodeGen/X86/win64_frame.ll create mode 100644 test/CodeGen/X86/win_eh_prepare.ll create mode 100644 test/CodeGen/X86/x32-lea-1.ll create mode 100644 test/CodeGen/X86/x86-64-baseptr.ll create mode 100644 test/CodeGen/X86/x86-inline-asm-validation.ll (limited to 'test/CodeGen') diff --git a/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll b/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll index 4da33a0..73ee522 100644 --- a/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll +++ b/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll @@ -16,7 +16,7 @@ for.body: ; preds = %for.body, %entry %add53 = add nsw i64 %n1, 0, !dbg !52 %add55 = add nsw i64 %n1, 0, !dbg !53 %mul63 = mul nsw i64 %add53, -20995, !dbg !54 - tail call void @llvm.dbg.value(metadata !{i64 %mul63}, i64 0, metadata !30, metadata !{metadata !"0x102"}), !dbg !55 + tail call void @llvm.dbg.value(metadata i64 %mul63, i64 0, metadata !30, metadata !{!"0x102"}), !dbg !55 %mul65 = mul nsw i64 %add55, -3196, !dbg !56 %add67 = add nsw i64 0, %mul65, !dbg !57 %add80 = add i64 0, 1024, !dbg !58 @@ -44,63 +44,63 @@ attributes #1 = { nounwind readnone } !llvm.module.flags = !{!36, !37} !llvm.ident = !{!38} -!0 = metadata !{metadata !"0x11\0012\00clang version 3.6.0 \001\00\000\00\001", metadata !1, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2} ; [ DW_TAG_compile_unit ] [] [] [] -!1 = metadata !{metadata !"test.c", metadata !""} -!2 = metadata !{} -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !"0x2e\00\00\00\00140\000\001\000\006\00256\001\00141", metadata !1, metadata !5, metadata !6, null, void ()* @test, null, null, metadata !12} ; [ DW_TAG_subprogram ] [] [] [def] [scope 141] [] -!5 = metadata !{metadata !"0x29", metadata !1} ; [ DW_TAG_file_type ] [] [] -!6 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !7, null, null, null} ; [ DW_TAG_subroutine_type ] [] [] [from ] -!7 = metadata !{null, metadata !8} -!8 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !9} ; [ DW_TAG_pointer_type ] [] [] [] -!9 = metadata !{metadata !"0x16\00\0030\000\000\000\000", metadata !10, null, metadata !11} ; [ DW_TAG_typedef ] [] [] [] [from int] -!10 = metadata !{metadata !"", metadata !""} -!11 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [] [int] [] -!12 = metadata !{metadata !13, metadata !14, metadata !18, metadata !19, metadata !20, metadata !21, metadata !22, metadata !23, metadata !24, metadata !25, metadata !26, metadata !27, metadata !28, metadata !29, metadata !30, metadata !31, metadata !32, metadata !33, metadata !34, metadata !35} -!13 = metadata !{metadata !"0x101\00\0016777356\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [] [data] [] -!14 = metadata !{metadata !"0x100\00\00142\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [] [] [] -!15 = metadata !{metadata !"0x16\00\00183\000\000\000\000", metadata !16, null, metadata !17} ; [ DW_TAG_typedef ] [] [INT32] [] [from long int] -!16 = metadata !{metadata !"", metadata !""} -!17 = metadata !{metadata !"0x24\00\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [] [long int] [] -!18 = metadata !{metadata !"0x100\00\00142\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [] [] [] -!19 = metadata !{metadata !"0x100\00\00142\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [] [] [] -!20 = metadata !{metadata !"0x100\00\00142\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [] [] [] -!21 = metadata !{metadata !"0x100\00\00142\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [] [] [] -!22 = metadata !{metadata !"0x100\00\00142\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [] [] [] -!23 = metadata !{metadata !"0x100\00\00142\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [] [] [] -!24 = metadata !{metadata !"0x100\00\00142\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!25 = metadata !{metadata !"0x100\00\00143\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!26 = metadata !{metadata !"0x100\00\00143\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!27 = metadata !{metadata !"0x100\00\00143\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!28 = metadata !{metadata !"0x100\00\00143\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!29 = metadata !{metadata !"0x100\00\00144\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!30 = metadata !{metadata !"0x100\00\00144\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!31 = metadata !{metadata !"0x100\00\00144\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!32 = metadata !{metadata !"0x100\00\00144\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!33 = metadata !{metadata !"0x100\00\00144\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [ ] [] [] -!34 = metadata !{metadata !"0x100\00\00145\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [ ] [] [] -!35 = metadata !{metadata !"0x100\00\00146\000", metadata !4, metadata !5, metadata !11} ; [ DW_TAG_auto_variable ] [ ] [] [] -!36 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} -!37 = metadata !{i32 2, metadata !"Debug Info Version", i32 2} -!38 = metadata !{metadata !"clang version 3.6.0 "} -!39 = metadata !{i32 154, i32 8, metadata !40, null} -!40 = metadata !{metadata !"0xb\00154\008\002", metadata !1, metadata !41} ; [ DW_TAG_lexical_block ] [ ] [] -!41 = metadata !{metadata !"0xb\00154\008\001", metadata !1, metadata !42} ; [ DW_TAG_lexical_block ] [ ] [] -!42 = metadata !{metadata !"0xb\00154\003\000", metadata !1, metadata !4} ; [ DW_TAG_lexical_block ] [ ] [] -!43 = metadata !{i32 157, i32 5, metadata !44, null} -!44 = metadata !{metadata !"0xb\00154\0042\000", metadata !1, metadata !42} ; [ DW_TAG_lexical_block ] [ ] [] -!45 = metadata !{i32 159, i32 5, metadata !44, null} -!46 = metadata !{metadata !47, metadata !47, i64 0} -!47 = metadata !{metadata !"int", metadata !48, i64 0} -!48 = metadata !{metadata !"omnipotent char", metadata !49, i64 0} -!49 = metadata !{metadata !"Simple C/C++ TBAA"} -!50 = metadata !{i32 160, i32 5, metadata !44, null} -!51 = metadata !{i32 161, i32 5, metadata !44, null} -!52 = metadata !{i32 188, i32 5, metadata !44, null} -!53 = metadata !{i32 190, i32 5, metadata !44, null} -!54 = metadata !{i32 198, i32 5, metadata !44, null} -!55 = metadata !{i32 144, i32 13, metadata !4, null} -!56 = metadata !{i32 200, i32 5, metadata !44, null} -!57 = metadata !{i32 203, i32 5, metadata !44, null} -!58 = metadata !{i32 207, i32 5, metadata !44, null} -!59 = metadata !{i32 208, i32 5, metadata !44, null} +!0 = !{!"0x11\0012\00clang version 3.6.0 \001\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [] [] [] +!1 = !{!"test.c", !""} +!2 = !{} +!3 = !{!4} +!4 = !{!"0x2e\00\00\00\00140\000\001\000\006\00256\001\00141", !1, !5, !6, null, void ()* @test, null, null, !12} ; [ DW_TAG_subprogram ] [] [] [def] [scope 141] [] +!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [] [] +!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [] [] [from ] +!7 = !{null, !8} +!8 = !{!"0xf\00\000\0064\0064\000\000", null, null, !9} ; [ DW_TAG_pointer_type ] [] [] [] +!9 = !{!"0x16\00\0030\000\000\000\000", !10, null, !11} ; [ DW_TAG_typedef ] [] [] [] [from int] +!10 = !{!"", !""} +!11 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [] [int] [] +!12 = !{!13, !14, !18, !19, !20, !21, !22, !23, !24, !25, !26, !27, !28, !29, !30, !31, !32, !33, !34, !35} +!13 = !{!"0x101\00\0016777356\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [] [data] [] +!14 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] +!15 = !{!"0x16\00\00183\000\000\000\000", !16, null, !17} ; [ DW_TAG_typedef ] [] [INT32] [] [from long int] +!16 = !{!"", !""} +!17 = !{!"0x24\00\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [] [long int] [] +!18 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] +!19 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] +!20 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] +!21 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] +!22 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] +!23 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [] [] [] +!24 = !{!"0x100\00\00142\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!25 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!26 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!27 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!28 = !{!"0x100\00\00143\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!29 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!30 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!31 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!32 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!33 = !{!"0x100\00\00144\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [ ] [] [] +!34 = !{!"0x100\00\00145\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [ ] [] [] +!35 = !{!"0x100\00\00146\000", !4, !5, !11} ; [ DW_TAG_auto_variable ] [ ] [] [] +!36 = !{i32 2, !"Dwarf Version", i32 4} +!37 = !{i32 2, !"Debug Info Version", i32 2} +!38 = !{!"clang version 3.6.0 "} +!39 = !MDLocation(line: 154, column: 8, scope: !40) +!40 = !{!"0xb\00154\008\002", !1, !41} ; [ DW_TAG_lexical_block ] [ ] [] +!41 = !{!"0xb\00154\008\001", !1, !42} ; [ DW_TAG_lexical_block ] [ ] [] +!42 = !{!"0xb\00154\003\000", !1, !4} ; [ DW_TAG_lexical_block ] [ ] [] +!43 = !MDLocation(line: 157, column: 5, scope: !44) +!44 = !{!"0xb\00154\0042\000", !1, !42} ; [ DW_TAG_lexical_block ] [ ] [] +!45 = !MDLocation(line: 159, column: 5, scope: !44) +!46 = !{!47, !47, i64 0} +!47 = !{!"int", !48, i64 0} +!48 = !{!"omnipotent char", !49, i64 0} +!49 = !{!"Simple C/C++ TBAA"} +!50 = !MDLocation(line: 160, column: 5, scope: !44) +!51 = !MDLocation(line: 161, column: 5, scope: !44) +!52 = !MDLocation(line: 188, column: 5, scope: !44) +!53 = !MDLocation(line: 190, column: 5, scope: !44) +!54 = !MDLocation(line: 198, column: 5, scope: !44) +!55 = !MDLocation(line: 144, column: 13, scope: !4) +!56 = !MDLocation(line: 200, column: 5, scope: !44) +!57 = !MDLocation(line: 203, column: 5, scope: !44) +!58 = !MDLocation(line: 207, column: 5, scope: !44) +!59 = !MDLocation(line: 208, column: 5, scope: !44) diff --git a/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll b/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll new file mode 100644 index 0000000..4553251 --- /dev/null +++ b/test/CodeGen/AArch64/aarch64-2014-12-02-combine-soften.ll @@ -0,0 +1,16 @@ +;RUN: llc <%s -mattr=-neon -mattr=-fp-armv8 | FileCheck %s +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64" + +@t = common global i32 0, align 4 +@x = common global i32 0, align 4 + +define void @foo() { +entry: +;CHECK-LABEL: foo: +;CHECK: __floatsisf + %0 = load i32* @x, align 4 + %conv = sitofp i32 %0 to float + store float %conv, float* bitcast (i32* @t to float*), align 4 + ret void +} diff --git a/test/CodeGen/AArch64/addsub-shifted.ll b/test/CodeGen/AArch64/addsub-shifted.ll index 0a93edd..1d963f4 100644 --- a/test/CodeGen/AArch64/addsub-shifted.ll +++ b/test/CodeGen/AArch64/addsub-shifted.ll @@ -190,7 +190,7 @@ define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { ; CHECK: ret } -define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { +define void @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64, i32 %v) { ; CHECK-LABEL: test_cmp: %shift1 = shl i32 %rhs32, 13 @@ -199,40 +199,46 @@ define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) { ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, lsl #13 t2: + store volatile i32 %v, i32* @var32 %shift2 = lshr i32 %rhs32, 20 %tst2 = icmp ne i32 %lhs32, %shift2 br i1 %tst2, label %t3, label %end ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, lsr #20 t3: + store volatile i32 %v, i32* @var32 %shift3 = ashr i32 %rhs32, 9 %tst3 = icmp ne i32 %lhs32, %shift3 br i1 %tst3, label %t4, label %end ; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}, asr #9 t4: + store volatile i32 %v, i32* @var32 %shift4 = shl i64 %rhs64, 43 %tst4 = icmp uge i64 %lhs64, %shift4 br i1 %tst4, label %t5, label %end ; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, lsl #43 t5: + store volatile i32 %v, i32* @var32 %shift5 = lshr i64 %rhs64, 20 %tst5 = icmp ne i64 %lhs64, %shift5 br i1 %tst5, label %t6, label %end ; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, lsr #20 t6: + store volatile i32 %v, i32* @var32 %shift6 = ashr i64 %rhs64, 59 %tst6 = icmp ne i64 %lhs64, %shift6 br i1 %tst6, label %t7, label %end ; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}, asr #59 t7: - ret i32 1 -end: + store volatile i32 %v, i32* @var32 + br label %end - ret i32 0 +end: + ret void ; CHECK: ret } diff --git a/test/CodeGen/AArch64/analyze-branch.ll b/test/CodeGen/AArch64/analyze-branch.ll index 6616b27..932cd75 100644 --- a/test/CodeGen/AArch64/analyze-branch.ll +++ b/test/CodeGen/AArch64/analyze-branch.ll @@ -7,8 +7,8 @@ declare void @test_true() declare void @test_false() ; !0 corresponds to a branch being taken, !1 to not being takne. -!0 = metadata !{metadata !"branch_weights", i32 64, i32 4} -!1 = metadata !{metadata !"branch_weights", i32 4, i32 64} +!0 = !{!"branch_weights", i32 64, i32 4} +!1 = !{!"branch_weights", i32 4, i32 64} define void @test_Bcc_fallthrough_taken(i32 %in) nounwind { ; CHECK-LABEL: test_Bcc_fallthrough_taken: diff --git a/test/CodeGen/AArch64/analyzecmp.ll b/test/CodeGen/AArch64/analyzecmp.ll index 8962505..0b3bcd8 100644 --- a/test/CodeGen/AArch64/analyzecmp.ll +++ b/test/CodeGen/AArch64/analyzecmp.ll @@ -1,9 +1,9 @@ ; RUN: llc -O3 -mcpu=cortex-a57 < %s | FileCheck %s -; CHECK-LABLE: @test -; CHECK: tst [[CMP:x[0-9]+]], #0x8000000000000000 -; CHECK: csel [[R0:x[0-9]+]], [[S0:x[0-9]+]], [[S1:x[0-9]+]], eq -; CHECK: csel [[R1:x[0-9]+]], [[S2:x[0-9]+]], [[S3:x[0-9]+]], eq +; CHECK-LABEL: @test +; CHECK: and +; CHECK: csel +; CHECK: csel target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target triple = "arm64--linux-gnueabi" diff --git a/test/CodeGen/AArch64/argument-blocks.ll b/test/CodeGen/AArch64/argument-blocks.ll new file mode 100644 index 0000000..f1dcfa6 --- /dev/null +++ b/test/CodeGen/AArch64/argument-blocks.ll @@ -0,0 +1,197 @@ +; RUN: llc -mtriple=aarch64-apple-ios7.0 -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-DARWINPCS +; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AAPCS + +declare void @callee(...) + +define float @test_hfa_regs(float, [2 x float] %in) { +; CHECK-LABEL: test_hfa_regs: +; CHECK: fadd s0, s1, s2 + + %lhs = extractvalue [2 x float] %in, 0 + %rhs = extractvalue [2 x float] %in, 1 + %sum = fadd float %lhs, %rhs + ret float %sum +} + +; Check that the array gets allocated to a contiguous block on the stack (rather +; than the default of 2 8-byte slots). +define float @test_hfa_block([7 x float], [2 x float] %in) { +; CHECK-LABEL: test_hfa_block: +; CHECK: ldp [[LHS:s[0-9]+]], [[RHS:s[0-9]+]], [sp] +; CHECK: fadd s0, [[LHS]], [[RHS]] + + %lhs = extractvalue [2 x float] %in, 0 + %rhs = extractvalue [2 x float] %in, 1 + %sum = fadd float %lhs, %rhs + ret float %sum +} + +; Check that an HFA prevents backfilling of VFP registers (i.e. %rhs must go on +; the stack rather than in s7). +define float @test_hfa_block_consume([7 x float], [2 x float] %in, float %rhs) { +; CHECK-LABEL: test_hfa_block_consume: +; CHECK-DAG: ldr [[LHS:s[0-9]+]], [sp] +; CHECK-DAG: ldr [[RHS:s[0-9]+]], [sp, #8] +; CHECK: fadd s0, [[LHS]], [[RHS]] + + %lhs = extractvalue [2 x float] %in, 0 + %sum = fadd float %lhs, %rhs + ret float %sum +} + +define float @test_hfa_stackalign([8 x float], [1 x float], [2 x float] %in) { +; CHECK-LABEL: test_hfa_stackalign: +; CHECK-AAPCS: ldp [[LHS:s[0-9]+]], [[RHS:s[0-9]+]], [sp, #8] +; CHECK-DARWINPCS: ldp [[LHS:s[0-9]+]], [[RHS:s[0-9]+]], [sp, #4] +; CHECK: fadd s0, [[LHS]], [[RHS]] + %lhs = extractvalue [2 x float] %in, 0 + %rhs = extractvalue [2 x float] %in, 1 + %sum = fadd float %lhs, %rhs + ret float %sum +} + +; An HFA that ends up on the stack should not have any effect on where +; integer-based arguments go. +define i64 @test_hfa_ignores_gprs([7 x float], [2 x float] %in, i64, i64 %res) { +; CHECK-LABEL: test_hfa_ignores_gprs: +; CHECK: mov x0, x1 + ret i64 %res +} + +; [2 x float] should not be promoted to double by the Darwin varargs handling, +; but should go in an 8-byte aligned slot. +define void @test_varargs_stackalign() { +; CHECK-LABEL: test_varargs_stackalign: +; CHECK-DARWINPCS: stp {{w[0-9]+}}, {{w[0-9]+}}, [sp, #16] + + call void(...)* @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0]) + ret void +} + +define i64 @test_smallstruct_block([7 x i64], [2 x i64] %in) { +; CHECK-LABEL: test_smallstruct_block: +; CHECK: ldp [[LHS:x[0-9]+]], [[RHS:x[0-9]+]], [sp] +; CHECK: add x0, [[LHS]], [[RHS]] + %lhs = extractvalue [2 x i64] %in, 0 + %rhs = extractvalue [2 x i64] %in, 1 + %sum = add i64 %lhs, %rhs + ret i64 %sum +} + +; Check that a small struct prevents backfilling of registers (i.e. %rhs +; must go on the stack rather than in x7). +define i64 @test_smallstruct_block_consume([7 x i64], [2 x i64] %in, i64 %rhs) { +; CHECK-LABEL: test_smallstruct_block_consume: +; CHECK-DAG: ldr [[LHS:x[0-9]+]], [sp] +; CHECK-DAG: ldr [[RHS:x[0-9]+]], [sp, #16] +; CHECK: add x0, [[LHS]], [[RHS]] + + %lhs = extractvalue [2 x i64] %in, 0 + %sum = add i64 %lhs, %rhs + ret i64 %sum +} + +define <1 x i64> @test_v1i64_blocked([7 x double], [2 x <1 x i64>] %in) { +; CHECK-LABEL: test_v1i64_blocked: +; CHECK: ldr d0, [sp] + %val = extractvalue [2 x <1 x i64>] %in, 0 + ret <1 x i64> %val +} + +define <1 x double> @test_v1f64_blocked([7 x double], [2 x <1 x double>] %in) { +; CHECK-LABEL: test_v1f64_blocked: +; CHECK: ldr d0, [sp] + %val = extractvalue [2 x <1 x double>] %in, 0 + ret <1 x double> %val +} + +define <2 x i32> @test_v2i32_blocked([7 x double], [2 x <2 x i32>] %in) { +; CHECK-LABEL: test_v2i32_blocked: +; CHECK: ldr d0, [sp] + %val = extractvalue [2 x <2 x i32>] %in, 0 + ret <2 x i32> %val +} + +define <2 x float> @test_v2f32_blocked([7 x double], [2 x <2 x float>] %in) { +; CHECK-LABEL: test_v2f32_blocked: +; CHECK: ldr d0, [sp] + %val = extractvalue [2 x <2 x float>] %in, 0 + ret <2 x float> %val +} + +define <4 x i16> @test_v4i16_blocked([7 x double], [2 x <4 x i16>] %in) { +; CHECK-LABEL: test_v4i16_blocked: +; CHECK: ldr d0, [sp] + %val = extractvalue [2 x <4 x i16>] %in, 0 + ret <4 x i16> %val +} + +define <4 x half> @test_v4f16_blocked([7 x double], [2 x <4 x half>] %in) { +; CHECK-LABEL: test_v4f16_blocked: +; CHECK: ldr d0, [sp] + %val = extractvalue [2 x <4 x half>] %in, 0 + ret <4 x half> %val +} + +define <8 x i8> @test_v8i8_blocked([7 x double], [2 x <8 x i8>] %in) { +; CHECK-LABEL: test_v8i8_blocked: +; CHECK: ldr d0, [sp] + %val = extractvalue [2 x <8 x i8>] %in, 0 + ret <8 x i8> %val +} + +define <2 x i64> @test_v2i64_blocked([7 x double], [2 x <2 x i64>] %in) { +; CHECK-LABEL: test_v2i64_blocked: +; CHECK: ldr q0, [sp] + %val = extractvalue [2 x <2 x i64>] %in, 0 + ret <2 x i64> %val +} + +define <2 x double> @test_v2f64_blocked([7 x double], [2 x <2 x double>] %in) { +; CHECK-LABEL: test_v2f64_blocked: +; CHECK: ldr q0, [sp] + %val = extractvalue [2 x <2 x double>] %in, 0 + ret <2 x double> %val +} + +define <4 x i32> @test_v4i32_blocked([7 x double], [2 x <4 x i32>] %in) { +; CHECK-LABEL: test_v4i32_blocked: +; CHECK: ldr q0, [sp] + %val = extractvalue [2 x <4 x i32>] %in, 0 + ret <4 x i32> %val +} + +define <4 x float> @test_v4f32_blocked([7 x double], [2 x <4 x float>] %in) { +; CHECK-LABEL: test_v4f32_blocked: +; CHECK: ldr q0, [sp] + %val = extractvalue [2 x <4 x float>] %in, 0 + ret <4 x float> %val +} + +define <8 x i16> @test_v8i16_blocked([7 x double], [2 x <8 x i16>] %in) { +; CHECK-LABEL: test_v8i16_blocked: +; CHECK: ldr q0, [sp] + %val = extractvalue [2 x <8 x i16>] %in, 0 + ret <8 x i16> %val +} + +define <8 x half> @test_v8f16_blocked([7 x double], [2 x <8 x half>] %in) { +; CHECK-LABEL: test_v8f16_blocked: +; CHECK: ldr q0, [sp] + %val = extractvalue [2 x <8 x half>] %in, 0 + ret <8 x half> %val +} + +define <16 x i8> @test_v16i8_blocked([7 x double], [2 x <16 x i8>] %in) { +; CHECK-LABEL: test_v16i8_blocked: +; CHECK: ldr q0, [sp] + %val = extractvalue [2 x <16 x i8>] %in, 0 + ret <16 x i8> %val +} + +define half @test_f16_blocked([7 x double], [2 x half] %in) { +; CHECK-LABEL: test_f16_blocked: +; CHECK: ldr h0, [sp] + %val = extractvalue [2 x half] %in, 0 + ret half %val +} diff --git a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll index e57a8c9..8b88c0b 100644 --- a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll +++ b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll @@ -11,7 +11,7 @@ if.then24: ; preds = %entry unreachable if.else295: ; preds = %entry - call void @llvm.dbg.declare(metadata !{i32* %do_tab_convert}, metadata !16, metadata !{metadata !"0x102"}), !dbg !18 + call void @llvm.dbg.declare(metadata i32* %do_tab_convert, metadata !16, metadata !{!"0x102"}), !dbg !18 store i32 0, i32* %do_tab_convert, align 4, !dbg !19 unreachable } @@ -21,25 +21,25 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone !llvm.dbg.gv = !{!0} !llvm.dbg.sp = !{!1, !7, !10, !11, !12} -!0 = metadata !{metadata !"0x34\00vsplive\00vsplive\00\00617\001\001", metadata !1, metadata !2, metadata !6, null, null} ; [ DW_TAG_variable ] -!1 = metadata !{metadata !"0x2e\00drt_vsprintf\00drt_vsprintf\00\00616\000\001\000\006\00256\000\000", metadata !20, metadata !2, metadata !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!2 = metadata !{metadata !"0x29", metadata !20} ; [ DW_TAG_file_type ] -!3 = metadata !{metadata !"0x11\0012\00clang version 3.0 (http://llvm.org/git/clang.git git:/git/puzzlebox/clang.git/ c4d1aea01c4444eb81bdbf391f1be309127c3cf1)\001\00\000\00\000", metadata !20, metadata !21, metadata !21, null, null, null} ; [ DW_TAG_compile_unit ] -!4 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !20, metadata !2, null, metadata !5, i32 0} ; [ DW_TAG_subroutine_type ] -!5 = metadata !{metadata !6} -!6 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, metadata !3} ; [ DW_TAG_base_type ] -!7 = metadata !{metadata !"0x2e\00putc_mem\00putc_mem\00\0030\001\001\000\006\00256\000\000", metadata !20, metadata !2, metadata !8, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!8 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !20, metadata !2, null, metadata !9, i32 0} ; [ DW_TAG_subroutine_type ] -!9 = metadata !{null} -!10 = metadata !{metadata !"0x2e\00print_double\00print_double\00\00203\001\001\000\006\00256\000\000", metadata !20, metadata !2, metadata !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!11 = metadata !{metadata !"0x2e\00print_number\00print_number\00\0075\001\001\000\006\00256\000\000", metadata !20, metadata !2, metadata !4, i32 0, null, null, null, null} ; [ DW_TAG_subprogram ] -!12 = metadata !{metadata !"0x2e\00get_flags\00get_flags\00\00508\001\001\000\006\00256\000\000", metadata !20, metadata !2, metadata !8, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!13 = metadata !{i32 653, i32 5, metadata !14, null} -!14 = metadata !{metadata !"0xb\00652\0035\002", metadata !20, metadata !15} ; [ DW_TAG_lexical_block ] -!15 = metadata !{metadata !"0xb\00616\001\000", metadata !20, metadata !1} ; [ DW_TAG_lexical_block ] -!16 = metadata !{metadata !"0x100\00do_tab_convert\00853\000", metadata !17, metadata !2, metadata !6} ; [ DW_TAG_auto_variable ] -!17 = metadata !{metadata !"0xb\00850\0012\0033", metadata !20, metadata !14} ; [ DW_TAG_lexical_block ] -!18 = metadata !{i32 853, i32 11, metadata !17, null} -!19 = metadata !{i32 853, i32 29, metadata !17, null} -!20 = metadata !{metadata !"print.i", metadata !"/Volumes/Ebi/echeng/radars/r9146594"} -!21 = metadata !{i32 0} +!0 = !{!"0x34\00vsplive\00vsplive\00\00617\001\001", !1, !2, !6, null, null} ; [ DW_TAG_variable ] +!1 = !{!"0x2e\00drt_vsprintf\00drt_vsprintf\00\00616\000\001\000\006\00256\000\000", !20, !2, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] +!2 = !{!"0x29", !20} ; [ DW_TAG_file_type ] +!3 = !{!"0x11\0012\00clang version 3.0 (http://llvm.org/git/clang.git git:/git/puzzlebox/clang.git/ c4d1aea01c4444eb81bdbf391f1be309127c3cf1)\001\00\000\00\000", !20, !21, !21, null, null, null} ; [ DW_TAG_compile_unit ] +!4 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !5, i32 0} ; [ DW_TAG_subroutine_type ] +!5 = !{!6} +!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !3} ; [ DW_TAG_base_type ] +!7 = !{!"0x2e\00putc_mem\00putc_mem\00\0030\001\001\000\006\00256\000\000", !20, !2, !8, null, null, null, null, null} ; [ DW_TAG_subprogram ] +!8 = !{!"0x15\00\000\000\000\000\000\000", !20, !2, null, !9, i32 0} ; [ DW_TAG_subroutine_type ] +!9 = !{null} +!10 = !{!"0x2e\00print_double\00print_double\00\00203\001\001\000\006\00256\000\000", !20, !2, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] +!11 = !{!"0x2e\00print_number\00print_number\00\0075\001\001\000\006\00256\000\000", !20, !2, !4, i32 0, null, null, null, null} ; [ DW_TAG_subprogram ] +!12 = !{!"0x2e\00get_flags\00get_flags\00\00508\001\001\000\006\00256\000\000", !20, !2, !8, null, null, null, null, null} ; [ DW_TAG_subprogram ] +!13 = !MDLocation(line: 653, column: 5, scope: !14) +!14 = !{!"0xb\00652\0035\002", !20, !15} ; [ DW_TAG_lexical_block ] +!15 = !{!"0xb\00616\001\000", !20, !1} ; [ DW_TAG_lexical_block ] +!16 = !{!"0x100\00do_tab_convert\00853\000", !17, !2, !6} ; [ DW_TAG_auto_variable ] +!17 = !{!"0xb\00850\0012\0033", !20, !14} ; [ DW_TAG_lexical_block ] +!18 = !MDLocation(line: 853, column: 11, scope: !17) +!19 = !MDLocation(line: 853, column: 29, scope: !17) +!20 = !{!"print.i", !"/Volumes/Ebi/echeng/radars/r9146594"} +!21 = !{i32 0} diff --git a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll index 4b037db..b5b1b70 100644 --- a/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll +++ b/test/CodeGen/AArch64/arm64-2012-05-22-LdStOptBug.ll @@ -43,8 +43,8 @@ entry: !llvm.module.flags = !{!0, !1, !2, !3} -!0 = metadata !{i32 1, metadata !"Objective-C Version", i32 2} -!1 = metadata !{i32 1, metadata !"Objective-C Image Info Version", i32 0} -!2 = metadata !{i32 1, metadata !"Objective-C Image Info Section", metadata !"__DATA, __objc_imageinfo, regular, no_dead_strip"} -!3 = metadata !{i32 4, metadata !"Objective-C Garbage Collection", i32 0} -!4 = metadata !{} +!0 = !{i32 1, !"Objective-C Version", i32 2} +!1 = !{i32 1, !"Objective-C Image Info Version", i32 0} +!2 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"} +!3 = !{i32 4, !"Objective-C Garbage Collection", i32 0} +!4 = !{} diff --git a/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll b/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll index 7d880f3..4db1f59 100644 --- a/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll +++ b/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll @@ -61,7 +61,7 @@ entry: !llvm.module.flags = !{!0, !1, !2, !3} -!0 = metadata !{i32 1, metadata !"Objective-C Version", i32 2} -!1 = metadata !{i32 1, metadata !"Objective-C Image Info Version", i32 0} -!2 = metadata !{i32 1, metadata !"Objective-C Image Info Section", metadata !"__DATA, __objc_imageinfo, regular, no_dead_strip"} -!3 = metadata !{i32 4, metadata !"Objective-C Garbage Collection", i32 0} +!0 = !{i32 1, !"Objective-C Version", i32 2} +!1 = !{i32 1, !"Objective-C Image Info Version", i32 0} +!2 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"} +!3 = !{i32 4, !"Objective-C Garbage Collection", i32 0} diff --git a/test/CodeGen/AArch64/arm64-aapcs-be.ll b/test/CodeGen/AArch64/arm64-aapcs-be.ll index 77e2b0f..f27570a 100644 --- a/test/CodeGen/AArch64/arm64-aapcs-be.ll +++ b/test/CodeGen/AArch64/arm64-aapcs-be.ll @@ -21,4 +21,20 @@ entry: ; CHECK-DAG: strh w{{[0-9]}}, [sp, #14] ; CHECK-DAG: strb w{{[0-9]}}, [sp, #7] ret i32 %call -} \ No newline at end of file +} + +define float @test_block_addr([8 x float], [1 x float] %in) { +; CHECK-LABEL: test_block_addr: +; CHECK: ldr s0, [sp] + %val = extractvalue [1 x float] %in, 0 + ret float %val +} + +define void @test_block_addr_callee() { +; CHECK-LABEL: test_block_addr_callee: +; CHECK: str {{[a-z0-9]+}}, [sp] +; CHECK: bl test_block_addr + %val = insertvalue [1 x float] undef, float 0.0, 0 + call float @test_block_addr([8 x float] undef, [1 x float] %val) + ret void +} diff --git a/test/CodeGen/AArch64/arm64-abi_align.ll b/test/CodeGen/AArch64/arm64-abi_align.ll index deb740e..e03d7fa 100644 --- a/test/CodeGen/AArch64/arm64-abi_align.ll +++ b/test/CodeGen/AArch64/arm64-abi_align.ll @@ -527,8 +527,8 @@ attributes #3 = { nounwind "fp-contract-model"="standard" "relocation-model"="pi attributes #4 = { nounwind } attributes #5 = { nobuiltin } -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"short", metadata !1} -!4 = metadata !{i64 0, i64 4, metadata !0, i64 4, i64 2, metadata !3, i64 8, i64 4, metadata !0, i64 12, i64 2, metadata !3, i64 16, i64 4, metadata !0, i64 20, i64 2, metadata !3} +!0 = !{!"int", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} +!3 = !{!"short", !1} +!4 = !{i64 0, i64 4, !0, i64 4, i64 2, !3, i64 8, i64 4, !0, i64 12, i64 2, !3, i64 16, i64 4, !0, i64 20, i64 2, !3} diff --git a/test/CodeGen/AArch64/arm64-atomic-128.ll b/test/CodeGen/AArch64/arm64-atomic-128.ll index 3377849..642d72a 100644 --- a/test/CodeGen/AArch64/arm64-atomic-128.ll +++ b/test/CodeGen/AArch64/arm64-atomic-128.ll @@ -29,8 +29,7 @@ define void @fetch_and_nand(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: str [[DEST_REGHI]] -; CHECK-DAG: str [[DEST_REGLO]] +; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] %val = atomicrmw nand i128* %p, i128 %bits release store i128 %val, i128* @var, align 16 ret void @@ -45,8 +44,7 @@ define void @fetch_and_or(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: str [[DEST_REGHI]] -; CHECK-DAG: str [[DEST_REGLO]] +; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] %val = atomicrmw or i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -61,8 +59,7 @@ define void @fetch_and_add(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: str [[DEST_REGHI]] -; CHECK-DAG: str [[DEST_REGLO]] +; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] %val = atomicrmw add i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -77,8 +74,7 @@ define void @fetch_and_sub(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: str [[DEST_REGHI]] -; CHECK-DAG: str [[DEST_REGLO]] +; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] %val = atomicrmw sub i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -99,8 +95,7 @@ define void @fetch_and_min(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: str [[DEST_REGHI]] -; CHECK-DAG: str [[DEST_REGLO]] +; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] %val = atomicrmw min i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -121,8 +116,7 @@ define void @fetch_and_max(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: str [[DEST_REGHI]] -; CHECK-DAG: str [[DEST_REGLO]] +; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] %val = atomicrmw max i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -143,8 +137,7 @@ define void @fetch_and_umin(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: str [[DEST_REGHI]] -; CHECK-DAG: str [[DEST_REGLO]] +; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] %val = atomicrmw umin i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void @@ -165,8 +158,7 @@ define void @fetch_and_umax(i128* %p, i128 %bits) { ; CHECK: stlxp [[SCRATCH_RES:w[0-9]+]], [[SCRATCH_REGLO]], [[SCRATCH_REGHI]], [x0] ; CHECK: cbnz [[SCRATCH_RES]], [[LABEL]] -; CHECK-DAG: str [[DEST_REGHI]] -; CHECK-DAG: str [[DEST_REGLO]] +; CHECK-DAG: stp [[DEST_REGLO]], [[DEST_REGHI]] %val = atomicrmw umax i128* %p, i128 %bits seq_cst store i128 %val, i128* @var, align 16 ret void diff --git a/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll b/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll index 664a26c..b032d9c 100644 --- a/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll +++ b/test/CodeGen/AArch64/arm64-ccmp-heuristics.ll @@ -184,7 +184,7 @@ declare hidden fastcc i32 @Maze1Mech(i64, i64, i64, i64, i64, i32, i32) nounwind ; Materializable declare hidden fastcc void @CleanNet(i64) nounwind ssp -!0 = metadata !{metadata !"long", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"any pointer", metadata !1} +!0 = !{!"long", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} +!3 = !{!"any pointer", !1} diff --git a/test/CodeGen/AArch64/arm64-cse.ll b/test/CodeGen/AArch64/arm64-cse.ll index b74ece8..508df7c 100644 --- a/test/CodeGen/AArch64/arm64-cse.ll +++ b/test/CodeGen/AArch64/arm64-cse.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 < %s -aarch64-atomic-cfg-tidy=0 -aarch64-gep-opt=false | FileCheck %s +; RUN: llc -O3 < %s -aarch64-atomic-cfg-tidy=0 -aarch64-gep-opt=false -verify-machineinstrs | FileCheck %s target triple = "arm64-apple-ios" ; rdar://12462006 diff --git a/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll b/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll index 8a744c5..a9b8024 100644 --- a/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll +++ b/test/CodeGen/AArch64/arm64-fastcc-tailcall.ll @@ -19,6 +19,6 @@ define internal fastcc void @callee(i32* nocapture %p, i32 %a) nounwind optsize ret void } -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!0 = !{!"int", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll b/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll index e51c38b..e41e19e 100644 --- a/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll +++ b/test/CodeGen/AArch64/arm64-fixed-point-scalar-cvt-dagcombine.ll @@ -6,7 +6,7 @@ ; rdar://11855286 define double @foo0(<2 x i64> %a) nounwind { ; CHECK: scvtf.2d [[REG:v[0-9]+]], v0, #9 -; CHECK-NEXT: ins.d v0[0], [[REG]][1] +; CHECK-NEXT: mov d0, [[REG]][1] %vecext = extractelement <2 x i64> %a, i32 1 %fcvt_n = tail call double @llvm.aarch64.neon.vcvtfxs2fp.f64.i64(i64 %vecext, i32 9) ret double %fcvt_n diff --git a/test/CodeGen/AArch64/arm64-fold-address.ll b/test/CodeGen/AArch64/arm64-fold-address.ll index 96cc3e9..1f0b918 100644 --- a/test/CodeGen/AArch64/arm64-fold-address.ll +++ b/test/CodeGen/AArch64/arm64-fold-address.ll @@ -72,8 +72,8 @@ entry: !llvm.module.flags = !{!0, !1, !2, !3} -!0 = metadata !{i32 1, metadata !"Objective-C Version", i32 2} -!1 = metadata !{i32 1, metadata !"Objective-C Image Info Version", i32 0} -!2 = metadata !{i32 1, metadata !"Objective-C Image Info Section", metadata !"__DATA, __objc_imageinfo, regular, no_dead_strip"} -!3 = metadata !{i32 4, metadata !"Objective-C Garbage Collection", i32 0} -!4 = metadata !{} +!0 = !{i32 1, !"Objective-C Version", i32 2} +!1 = !{i32 1, !"Objective-C Image Info Version", i32 0} +!2 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"} +!3 = !{i32 4, !"Objective-C Garbage Collection", i32 0} +!4 = !{} diff --git a/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll b/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll index c118f10..917911a 100644 --- a/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll +++ b/test/CodeGen/AArch64/arm64-indexed-vector-ldst-2.ll @@ -34,7 +34,7 @@ declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #1 attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } -!1 = metadata !{metadata !2, metadata !2, i64 0} -!2 = metadata !{metadata !"double", metadata !3, i64 0} -!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0} -!4 = metadata !{metadata !"Simple C/C++ TBAA"} +!1 = !{!2, !2, i64 0} +!2 = !{!"double", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/AArch64/arm64-ldp.ll b/test/CodeGen/AArch64/arm64-ldp.ll index 5a98626..a9fa4ca 100644 --- a/test/CodeGen/AArch64/arm64-ldp.ll +++ b/test/CodeGen/AArch64/arm64-ldp.ll @@ -12,6 +12,18 @@ define i32 @ldp_int(i32* %p) nounwind { ret i32 %add } +; CHECK: ldp_sext_int +; CHECK: ldpsw +define i64 @ldp_sext_int(i32* %p) nounwind { + %tmp = load i32* %p, align 4 + %add.ptr = getelementptr inbounds i32* %p, i64 1 + %tmp1 = load i32* %add.ptr, align 4 + %sexttmp = sext i32 %tmp to i64 + %sexttmp1 = sext i32 %tmp1 to i64 + %add = add nsw i64 %sexttmp1, %sexttmp + ret i64 %add +} + ; CHECK: ldp_long ; CHECK: ldp define i64 @ldp_long(i64* %p) nounwind { @@ -56,6 +68,21 @@ define i32 @ldur_int(i32* %a) nounwind { ret i32 %tmp3 } +define i64 @ldur_sext_int(i32* %a) nounwind { +; LDUR_CHK: ldur_sext_int +; LDUR_CHK: ldpsw [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-8] +; LDUR_CHK-NEXT: add x{{[0-9]+}}, [[DST2]], [[DST1]] +; LDUR_CHK-NEXT: ret + %p1 = getelementptr inbounds i32* %a, i32 -1 + %tmp1 = load i32* %p1, align 2 + %p2 = getelementptr inbounds i32* %a, i32 -2 + %tmp2 = load i32* %p2, align 2 + %sexttmp1 = sext i32 %tmp1 to i64 + %sexttmp2 = sext i32 %tmp2 to i64 + %tmp3 = add i64 %sexttmp1, %sexttmp2 + ret i64 %tmp3 +} + define i64 @ldur_long(i64* %a) nounwind ssp { ; LDUR_CHK: ldur_long ; LDUR_CHK: ldp [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-16] @@ -110,6 +137,22 @@ define i64 @pairUpBarelyIn(i64* %a) nounwind ssp { ret i64 %tmp3 } +define i64 @pairUpBarelyInSext(i32* %a) nounwind ssp { +; LDUR_CHK: pairUpBarelyInSext +; LDUR_CHK-NOT: ldur +; LDUR_CHK: ldpsw [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-256] +; LDUR_CHK-NEXT: add x{{[0-9]+}}, [[DST2]], [[DST1]] +; LDUR_CHK-NEXT: ret + %p1 = getelementptr inbounds i32* %a, i64 -63 + %tmp1 = load i32* %p1, align 2 + %p2 = getelementptr inbounds i32* %a, i64 -64 + %tmp2 = load i32* %p2, align 2 + %sexttmp1 = sext i32 %tmp1 to i64 + %sexttmp2 = sext i32 %tmp2 to i64 + %tmp3 = add i64 %sexttmp1, %sexttmp2 + ret i64 %tmp3 +} + define i64 @pairUpBarelyOut(i64* %a) nounwind ssp { ; LDUR_CHK: pairUpBarelyOut ; LDUR_CHK-NOT: ldp @@ -125,6 +168,23 @@ define i64 @pairUpBarelyOut(i64* %a) nounwind ssp { ret i64 %tmp3 } +define i64 @pairUpBarelyOutSext(i32* %a) nounwind ssp { +; LDUR_CHK: pairUpBarelyOutSext +; LDUR_CHK-NOT: ldp +; Don't be fragile about which loads or manipulations of the base register +; are used---just check that there isn't an ldp before the add +; LDUR_CHK: add +; LDUR_CHK-NEXT: ret + %p1 = getelementptr inbounds i32* %a, i64 -64 + %tmp1 = load i32* %p1, align 2 + %p2 = getelementptr inbounds i32* %a, i64 -65 + %tmp2 = load i32* %p2, align 2 + %sexttmp1 = sext i32 %tmp1 to i64 + %sexttmp2 = sext i32 %tmp2 to i64 + %tmp3 = add i64 %sexttmp1, %sexttmp2 + ret i64 %tmp3 +} + define i64 @pairUpNotAligned(i64* %a) nounwind ssp { ; LDUR_CHK: pairUpNotAligned ; LDUR_CHK-NOT: ldp @@ -147,3 +207,28 @@ define i64 @pairUpNotAligned(i64* %a) nounwind ssp { %tmp3 = add i64 %tmp1, %tmp2 ret i64 %tmp3 } + +define i64 @pairUpNotAlignedSext(i32* %a) nounwind ssp { +; LDUR_CHK: pairUpNotAlignedSext +; LDUR_CHK-NOT: ldp +; LDUR_CHK: ldursw +; LDUR_CHK-NEXT: ldursw +; LDUR_CHK-NEXT: add +; LDUR_CHK-NEXT: ret + %p1 = getelementptr inbounds i32* %a, i64 -18 + %bp1 = bitcast i32* %p1 to i8* + %bp1p1 = getelementptr inbounds i8* %bp1, i64 1 + %dp1 = bitcast i8* %bp1p1 to i32* + %tmp1 = load i32* %dp1, align 1 + + %p2 = getelementptr inbounds i32* %a, i64 -17 + %bp2 = bitcast i32* %p2 to i8* + %bp2p1 = getelementptr inbounds i8* %bp2, i64 1 + %dp2 = bitcast i8* %bp2p1 to i32* + %tmp2 = load i32* %dp2, align 1 + + %sexttmp1 = sext i32 %tmp1 to i64 + %sexttmp2 = sext i32 %tmp2 to i64 + %tmp3 = add i64 %sexttmp1, %sexttmp2 + ret i64 %tmp3 +} diff --git a/test/CodeGen/AArch64/arm64-named-reg-alloc.ll b/test/CodeGen/AArch64/arm64-named-reg-alloc.ll index d86d2e6..0c56454 100644 --- a/test/CodeGen/AArch64/arm64-named-reg-alloc.ll +++ b/test/CodeGen/AArch64/arm64-named-reg-alloc.ll @@ -11,4 +11,4 @@ entry: declare i32 @llvm.read_register.i32(metadata) nounwind -!0 = metadata !{metadata !"x5\00"} +!0 = !{!"x5\00"} diff --git a/test/CodeGen/AArch64/arm64-named-reg-notareg.ll b/test/CodeGen/AArch64/arm64-named-reg-notareg.ll index 3ca14c4..759bc15 100644 --- a/test/CodeGen/AArch64/arm64-named-reg-notareg.ll +++ b/test/CodeGen/AArch64/arm64-named-reg-notareg.ll @@ -10,4 +10,4 @@ entry: declare i32 @llvm.read_register.i32(metadata) nounwind -!0 = metadata !{metadata !"notareg\00"} +!0 = !{!"notareg\00"} diff --git a/test/CodeGen/AArch64/arm64-neon-copy.ll b/test/CodeGen/AArch64/arm64-neon-copy.ll index 1cfba82..4a92c3d 100644 --- a/test/CodeGen/AArch64/arm64-neon-copy.ll +++ b/test/CodeGen/AArch64/arm64-neon-copy.ll @@ -188,7 +188,7 @@ define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) { define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) { ; CHECK-LABEL: ins2f1: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] +; CHECK: mov {{d[0-9]+}}, {{v[0-9]+}}.d[1] %tmp3 = extractelement <2 x double> %tmp1, i32 1 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0 ret <1 x double> %tmp4 diff --git a/test/CodeGen/AArch64/arm64-neon-select_cc.ll b/test/CodeGen/AArch64/arm64-neon-select_cc.ll index 95c582a..d334c08 100644 --- a/test/CodeGen/AArch64/arm64-neon-select_cc.ll +++ b/test/CodeGen/AArch64/arm64-neon-select_cc.ll @@ -204,3 +204,18 @@ define <2 x double> @test_select_cc_v2f64(double %a, double %b, <2 x double> %c, %e = select i1 %cmp31, <2 x double> %c, <2 x double> %d ret <2 x double> %e } + +; Special case: when the select condition is an icmp with i1 operands, don't +; do the comparison on vectors. +; Part of PR21549. +define <2 x i32> @test_select_cc_v2i32_icmpi1(i1 %cc, <2 x i32> %a, <2 x i32> %b) { +; CHECK-LABEL: test_select_cc_v2i32_icmpi1: +; CHECK: tst w0, #0x1 +; CHECK: csetm [[MASK:w[0-9]+]], ne +; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]] +; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b +; CHECK: mov v0.16b, [[DUPMASK]].16b + %cmp = icmp ne i1 %cc, 0 + %e = select i1 %cmp, <2 x i32> %a, <2 x i32> %b + ret <2 x i32> %e +} diff --git a/test/CodeGen/AArch64/arm64-platform-reg.ll b/test/CodeGen/AArch64/arm64-platform-reg.ll index 651c793..b0d3ee0 100644 --- a/test/CodeGen/AArch64/arm64-platform-reg.ll +++ b/test/CodeGen/AArch64/arm64-platform-reg.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s --check-prefix=CHECK-DARWIN +; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE-X18 +; RUN: llc -mtriple=arm64-freebsd-gnu -aarch64-reserve-x18 -o - %s | FileCheck %s --check-prefix=CHECK-RESERVE-X18 ; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s ; x18 is reserved as a platform register on Darwin but not on other @@ -16,11 +17,11 @@ define void @keep_live() { ; CHECK: ldr x18 ; CHECK: str x18 -; CHECK-DARWIN-NOT: ldr fp -; CHECK-DARWIN-NOT: ldr x18 -; CHECK-DARWIN: Spill -; CHECK-DARWIN-NOT: ldr fp -; CHECK-DARWIN-NOT: ldr x18 -; CHECK-DARWIN: ret +; CHECK-RESERVE-X18-NOT: ldr fp +; CHECK-RESERVE-X18-NOT: ldr x18 +; CHECK-RESERVE-X18: Spill +; CHECK-RESERVE-X18-NOT: ldr fp +; CHECK-RESERVE-X18-NOT: ldr x18 +; CHECK-RESERVE-X18: ret ret void } diff --git a/test/CodeGen/AArch64/arm64-popcnt.ll b/test/CodeGen/AArch64/arm64-popcnt.ll index 117ab3a..b0b529a 100644 --- a/test/CodeGen/AArch64/arm64-popcnt.ll +++ b/test/CodeGen/AArch64/arm64-popcnt.ll @@ -4,7 +4,8 @@ define i32 @cnt32_advsimd(i32 %x) nounwind readnone { %cnt = tail call i32 @llvm.ctpop.i32(i32 %x) ret i32 %cnt -; CHECK: fmov s0, w0 +; CHECK: ubfx x{{[0-9]+}} +; CHECK: fmov d0, x{{[0-9]+}} ; CHECK: cnt.8b v0, v0 ; CHECK: uaddlv.8b h0, v0 ; CHECK: fmov w0, s0 @@ -15,7 +16,24 @@ define i32 @cnt32_advsimd(i32 %x) nounwind readnone { ; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x33333333 ; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0xf0f0f0f ; CHECK-NONEON: mul +} +define i32 @cnt32_advsimd_2(<2 x i32> %x) { + %1 = extractelement <2 x i32> %x, i64 0 + %2 = tail call i32 @llvm.ctpop.i32(i32 %1) + ret i32 %2 +; CHECK: fmov w0, s0 +; CHECK: fmov d0, x0 +; CHECK: cnt.8b v0, v0 +; CHECK: uaddlv.8b h0, v0 +; CHECK: fmov w0, s0 +; CHECK: ret +; CHECK-NONEON-LABEL: cnt32_advsimd_2 +; CHECK-NONEON-NOT: 8b +; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x55555555 +; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0x33333333 +; CHECK-NONEON: and w{{[0-9]+}}, w{{[0-9]+}}, #0xf0f0f0f +; CHECK-NONEON: mul } define i64 @cnt64_advsimd(i64 %x) nounwind readnone { diff --git a/test/CodeGen/AArch64/arm64-prefetch.ll b/test/CodeGen/AArch64/arm64-prefetch.ll index 9dc6301..aac3515 100644 --- a/test/CodeGen/AArch64/arm64-prefetch.ll +++ b/test/CodeGen/AArch64/arm64-prefetch.ll @@ -117,7 +117,7 @@ entry: declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"any pointer", metadata !1} +!0 = !{!"int", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} +!3 = !{!"any pointer", !1} diff --git a/test/CodeGen/AArch64/arm64-promote-const.ll b/test/CodeGen/AArch64/arm64-promote-const.ll index 380ff55..5dd92a7 100644 --- a/test/CodeGen/AArch64/arm64-promote-const.ll +++ b/test/CodeGen/AArch64/arm64-promote-const.ll @@ -41,8 +41,7 @@ entry: ; PROMOTED-LABEL: test2: ; In stress mode, constant vector are promoted ; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1:__PromotedConst[0-9]+]]@PAGE -; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF -; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]] +; PROMOTED: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTV1]]@PAGEOFF] ; Destination register is defined by ABI ; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] ; PROMOTED-NEXT: mla.16b v0, v0, v[[REGNUM]] @@ -64,51 +63,23 @@ entry: ret <16 x i8> %add.i9 } -; Two different uses of the sane constant in two different basic blocks, +; Two different uses of the same constant in two different basic blocks, ; one dominates the other define <16 x i8> @test3(<16 x i8> %arg, i32 %path) { ; PROMOTED-LABEL: test3: ; In stress mode, constant vector are promoted ; Since, the constant is the same as the previous function, ; the same address must be used -; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE -; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF -; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]] -; Destination register is defined by ABI -; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] -; PROMOTED-NEXT: cbnz w0, [[LABEL:LBB.*]] -; Next BB -; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV2:__PromotedConst[0-9]+]]@PAGE -; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV2]]@PAGEOFF -; PROMOTED-NEXT: ldr q[[REGNUM]], {{\[}}[[BASEADDR]]] -; Next BB -; PROMOTED-NEXT: [[LABEL]]: -; PROMOTED-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] -; PROMOTED-NEXT: add.16b v0, v0, [[DESTV]] -; PROMOTED-NEXT: ret +; PROMOTED: ldr +; PROMOTED: ldr +; PROMOTED-NOT: ldr +; PROMOTED: ret ; REGULAR-LABEL: test3: -; Regular mode does not elimitate common sub expression by its own. -; In other words, the same loads appears several times. -; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1:lCP.*]]@PAGE -; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF] -; Destination register is defined by ABI -; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]] -; REGULAR-NEXT: cbz w0, [[LABELelse:LBB.*]] -; Next BB -; Redundant load -; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL1]]@PAGE -; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL1]]@PAGEOFF] -; REGULAR-NEXT: b [[LABELend:LBB.*]] -; Next BB -; REGULAR-NEXT: [[LABELelse]] -; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL2:lCP.*]]@PAGE -; REGULAR-NEXT: ldr q[[REGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL2]]@PAGEOFF] -; Next BB -; REGULAR-NEXT: [[LABELend]]: -; REGULAR-NEXT: mul.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] -; REGULAR-NEXT: add.16b v0, v0, [[DESTV]] -; REGULAR-NEXT: ret +; REGULAR: ldr +; REGULAR: ldr +; REGULAR-NOT: ldr +; REGULAR: ret entry: %add.i = add <16 x i8> %arg, %tobool = icmp eq i32 %path, 0 @@ -135,34 +106,14 @@ define <16 x i8> @test4(<16 x i8> %arg, i32 %path) { ; In stress mode, constant vector are promoted ; Since, the constant is the same as the previous function, ; the same address must be used -; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE -; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF -; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]] -; Destination register is defined by ABI -; PROMOTED-NEXT: add.16b v0, v0, v[[REGNUM]] -; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]] -; Next BB -; PROMOTED: mul.16b v0, v0, v[[REGNUM]] -; Next BB -; PROMOTED-NEXT: [[LABEL]]: -; PROMOTED-NEXT: ret - +; PROMOTED: ldr +; PROMOTED-NOT: ldr +; PROMOTED: ret ; REGULAR-LABEL: test4: -; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3:lCP.*]]@PAGE -; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF] -; Destination register is defined by ABI -; REGULAR-NEXT: add.16b v0, v0, v[[REGNUM]] -; REGULAR-NEXT: cbz w0, [[LABEL:LBB.*]] -; Next BB -; Redundant expression -; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL3]]@PAGE -; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL3]]@PAGEOFF] -; Destination register is defined by ABI -; REGULAR-NEXT: mul.16b v0, v0, v[[REGNUM]] -; Next BB -; REGULAR-NEXT: [[LABEL]]: -; REGULAR-NEXT: ret +; REGULAR: ldr +; REGULAR-NOT: ldr +; REGULAR: ret entry: %add.i = add <16 x i8> %arg, %tobool = icmp eq i32 %path, 0 @@ -184,40 +135,13 @@ define <16 x i8> @test5(<16 x i8> %arg, i32 %path) { ; In stress mode, constant vector are promoted ; Since, the constant is the same as the previous function, ; the same address must be used -; PROMOTED: adrp [[PAGEADDR:x[0-9]+]], [[CSTV1]]@PAGE -; PROMOTED: add [[BASEADDR:x[0-9]+]], [[PAGEADDR]], [[CSTV1]]@PAGEOFF -; PROMOTED-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[BASEADDR]]] -; PROMOTED-NEXT: cbz w0, [[LABEL:LBB.*]] -; Next BB -; PROMOTED: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] -; PROMOTED-NEXT: mul.16b v[[REGNUM]], [[DESTV]], v[[REGNUM]] -; Next BB -; PROMOTED-NEXT: [[LABEL]]: -; PROMOTED-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[REGNUM]], v[[REGNUM]] -; PROMOTED-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]] -; PROMOTED-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]] -; PROMOTED-NEXT: mul.16b v0, [[TMP3]], [[TMP3]] -; PROMOTED-NEXT: ret +; PROMOTED: ldr +; PROMOTED-NOT: ldr +; PROMOTED: ret ; REGULAR-LABEL: test5: -; REGULAR: cbz w0, [[LABELelse:LBB.*]] -; Next BB -; REGULAR: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE -; REGULAR-NEXT: ldr q[[REGNUM:[0-9]+]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] -; REGULAR-NEXT: add.16b [[DESTV:v[0-9]+]], v0, v[[REGNUM]] -; REGULAR-NEXT: mul.16b v[[DESTREGNUM:[0-9]+]], [[DESTV]], v[[REGNUM]] -; REGULAR-NEXT: b [[LABELend:LBB.*]] -; Next BB -; REGULAR-NEXT: [[LABELelse]] -; REGULAR-NEXT: adrp [[PAGEADDR:x[0-9]+]], [[CSTLABEL:lCP.*]]@PAGE -; REGULAR-NEXT: ldr q[[DESTREGNUM]], {{\[}}[[PAGEADDR]], [[CSTLABEL]]@PAGEOFF] -; Next BB -; REGULAR-NEXT: [[LABELend]]: -; REGULAR-NEXT: mul.16b [[TMP1:v[0-9]+]], v[[DESTREGNUM]], v[[DESTREGNUM]] -; REGULAR-NEXT: mul.16b [[TMP2:v[0-9]+]], [[TMP1]], [[TMP1]] -; REGULAR-NEXT: mul.16b [[TMP3:v[0-9]+]], [[TMP2]], [[TMP2]] -; REGULAR-NEXT: mul.16b v0, [[TMP3]], [[TMP3]] -; REGULAR-NEXT: ret +; REGULAR: ldr +; REGULAR: ret entry: %tobool = icmp eq i32 %path, 0 br i1 %tobool, label %if.end, label %if.then diff --git a/test/CodeGen/AArch64/arm64-st1.ll b/test/CodeGen/AArch64/arm64-st1.ll index 4370484..76d52f4 100644 --- a/test/CodeGen/AArch64/arm64-st1.ll +++ b/test/CodeGen/AArch64/arm64-st1.ll @@ -8,6 +8,26 @@ define void @st1lane_16b(<16 x i8> %A, i8* %D) { ret void } +define void @st1lane_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_16b +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.b { v0 }[1], [x[[XREG]]] + %ptr = getelementptr i8* %D, i64 %offset + %tmp = extractelement <16 x i8> %A, i32 1 + store i8 %tmp, i8* %ptr + ret void +} + +define void @st1lane0_ro_16b(<16 x i8> %A, i8* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_16b +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.b { v0 }[0], [x[[XREG]]] + %ptr = getelementptr i8* %D, i64 %offset + %tmp = extractelement <16 x i8> %A, i32 0 + store i8 %tmp, i8* %ptr + ret void +} + define void @st1lane_8h(<8 x i16> %A, i16* %D) { ; CHECK-LABEL: st1lane_8h ; CHECK: st1.h @@ -16,6 +36,25 @@ define void @st1lane_8h(<8 x i16> %A, i16* %D) { ret void } +define void @st1lane_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_8h +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.h { v0 }[1], [x[[XREG]]] + %ptr = getelementptr i16* %D, i64 %offset + %tmp = extractelement <8 x i16> %A, i32 1 + store i16 %tmp, i16* %ptr + ret void +} + +define void @st1lane0_ro_8h(<8 x i16> %A, i16* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_8h +; CHECK: str h0, [x0, x1, lsl #1] + %ptr = getelementptr i16* %D, i64 %offset + %tmp = extractelement <8 x i16> %A, i32 0 + store i16 %tmp, i16* %ptr + ret void +} + define void @st1lane_4s(<4 x i32> %A, i32* %D) { ; CHECK-LABEL: st1lane_4s ; CHECK: st1.s @@ -24,6 +63,25 @@ define void @st1lane_4s(<4 x i32> %A, i32* %D) { ret void } +define void @st1lane_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_4s +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.s { v0 }[1], [x[[XREG]]] + %ptr = getelementptr i32* %D, i64 %offset + %tmp = extractelement <4 x i32> %A, i32 1 + store i32 %tmp, i32* %ptr + ret void +} + +define void @st1lane0_ro_4s(<4 x i32> %A, i32* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_4s +; CHECK: str s0, [x0, x1, lsl #2] + %ptr = getelementptr i32* %D, i64 %offset + %tmp = extractelement <4 x i32> %A, i32 0 + store i32 %tmp, i32* %ptr + ret void +} + define void @st1lane_4s_float(<4 x float> %A, float* %D) { ; CHECK-LABEL: st1lane_4s_float ; CHECK: st1.s @@ -32,6 +90,25 @@ define void @st1lane_4s_float(<4 x float> %A, float* %D) { ret void } +define void @st1lane_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_4s_float +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.s { v0 }[1], [x[[XREG]]] + %ptr = getelementptr float* %D, i64 %offset + %tmp = extractelement <4 x float> %A, i32 1 + store float %tmp, float* %ptr + ret void +} + +define void @st1lane0_ro_4s_float(<4 x float> %A, float* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_4s_float +; CHECK: str s0, [x0, x1, lsl #2] + %ptr = getelementptr float* %D, i64 %offset + %tmp = extractelement <4 x float> %A, i32 0 + store float %tmp, float* %ptr + ret void +} + define void @st1lane_2d(<2 x i64> %A, i64* %D) { ; CHECK-LABEL: st1lane_2d ; CHECK: st1.d @@ -40,6 +117,25 @@ define void @st1lane_2d(<2 x i64> %A, i64* %D) { ret void } +define void @st1lane_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_2d +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.d { v0 }[1], [x[[XREG]]] + %ptr = getelementptr i64* %D, i64 %offset + %tmp = extractelement <2 x i64> %A, i32 1 + store i64 %tmp, i64* %ptr + ret void +} + +define void @st1lane0_ro_2d(<2 x i64> %A, i64* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_2d +; CHECK: str d0, [x0, x1, lsl #3] + %ptr = getelementptr i64* %D, i64 %offset + %tmp = extractelement <2 x i64> %A, i32 0 + store i64 %tmp, i64* %ptr + ret void +} + define void @st1lane_2d_double(<2 x double> %A, double* %D) { ; CHECK-LABEL: st1lane_2d_double ; CHECK: st1.d @@ -48,6 +144,25 @@ define void @st1lane_2d_double(<2 x double> %A, double* %D) { ret void } +define void @st1lane_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_2d_double +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.d { v0 }[1], [x[[XREG]]] + %ptr = getelementptr double* %D, i64 %offset + %tmp = extractelement <2 x double> %A, i32 1 + store double %tmp, double* %ptr + ret void +} + +define void @st1lane0_ro_2d_double(<2 x double> %A, double* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_2d_double +; CHECK: str d0, [x0, x1, lsl #3] + %ptr = getelementptr double* %D, i64 %offset + %tmp = extractelement <2 x double> %A, i32 0 + store double %tmp, double* %ptr + ret void +} + define void @st1lane_8b(<8 x i8> %A, i8* %D) { ; CHECK-LABEL: st1lane_8b ; CHECK: st1.b @@ -56,6 +171,26 @@ define void @st1lane_8b(<8 x i8> %A, i8* %D) { ret void } +define void @st1lane_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_8b +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.b { v0 }[1], [x[[XREG]]] + %ptr = getelementptr i8* %D, i64 %offset + %tmp = extractelement <8 x i8> %A, i32 1 + store i8 %tmp, i8* %ptr + ret void +} + +define void @st1lane0_ro_8b(<8 x i8> %A, i8* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_8b +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.b { v0 }[0], [x[[XREG]]] + %ptr = getelementptr i8* %D, i64 %offset + %tmp = extractelement <8 x i8> %A, i32 0 + store i8 %tmp, i8* %ptr + ret void +} + define void @st1lane_4h(<4 x i16> %A, i16* %D) { ; CHECK-LABEL: st1lane_4h ; CHECK: st1.h @@ -64,6 +199,25 @@ define void @st1lane_4h(<4 x i16> %A, i16* %D) { ret void } +define void @st1lane_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_4h +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.h { v0 }[1], [x[[XREG]]] + %ptr = getelementptr i16* %D, i64 %offset + %tmp = extractelement <4 x i16> %A, i32 1 + store i16 %tmp, i16* %ptr + ret void +} + +define void @st1lane0_ro_4h(<4 x i16> %A, i16* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_4h +; CHECK: str h0, [x0, x1, lsl #1] + %ptr = getelementptr i16* %D, i64 %offset + %tmp = extractelement <4 x i16> %A, i32 0 + store i16 %tmp, i16* %ptr + ret void +} + define void @st1lane_2s(<2 x i32> %A, i32* %D) { ; CHECK-LABEL: st1lane_2s ; CHECK: st1.s @@ -72,6 +226,25 @@ define void @st1lane_2s(<2 x i32> %A, i32* %D) { ret void } +define void @st1lane_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_2s +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.s { v0 }[1], [x[[XREG]]] + %ptr = getelementptr i32* %D, i64 %offset + %tmp = extractelement <2 x i32> %A, i32 1 + store i32 %tmp, i32* %ptr + ret void +} + +define void @st1lane0_ro_2s(<2 x i32> %A, i32* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_2s +; CHECK: str s0, [x0, x1, lsl #2] + %ptr = getelementptr i32* %D, i64 %offset + %tmp = extractelement <2 x i32> %A, i32 0 + store i32 %tmp, i32* %ptr + ret void +} + define void @st1lane_2s_float(<2 x float> %A, float* %D) { ; CHECK-LABEL: st1lane_2s_float ; CHECK: st1.s @@ -80,6 +253,25 @@ define void @st1lane_2s_float(<2 x float> %A, float* %D) { ret void } +define void @st1lane_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) { +; CHECK-LABEL: st1lane_ro_2s_float +; CHECK: add x[[XREG:[0-9]+]], x0, x1 +; CHECK: st1.s { v0 }[1], [x[[XREG]]] + %ptr = getelementptr float* %D, i64 %offset + %tmp = extractelement <2 x float> %A, i32 1 + store float %tmp, float* %ptr + ret void +} + +define void @st1lane0_ro_2s_float(<2 x float> %A, float* %D, i64 %offset) { +; CHECK-LABEL: st1lane0_ro_2s_float +; CHECK: str s0, [x0, x1, lsl #2] + %ptr = getelementptr float* %D, i64 %offset + %tmp = extractelement <2 x float> %A, i32 0 + store float %tmp, float* %ptr + ret void +} + define void @st2lane_16b(<16 x i8> %A, <16 x i8> %B, i8* %D) { ; CHECK-LABEL: st2lane_16b ; CHECK: st2.b diff --git a/test/CodeGen/AArch64/arm64-stackmap-nops.ll b/test/CodeGen/AArch64/arm64-stackmap-nops.ll new file mode 100644 index 0000000..5915b64 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-stackmap-nops.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=arm64-apple-darwin | FileCheck %s + +define void @test_shadow_optimization() { +entry: +; Expect 8 bytes worth of nops here rather than 16: With the shadow optimization +; in place, 8 bytes will be consumed by the frame teardown and return instr. +; CHECK-LABEL: test_shadow_optimization: +; CHECK: nop +; CHECK-NEXT: nop +; CHECK-NOT: nop + tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 16) + ret void +} + +declare void @llvm.experimental.stackmap(i64, i32, ...) diff --git a/test/CodeGen/AArch64/arm64-stackpointer.ll b/test/CodeGen/AArch64/arm64-stackpointer.ll index 581faf1..a33de8c 100644 --- a/test/CodeGen/AArch64/arm64-stackpointer.ll +++ b/test/CodeGen/AArch64/arm64-stackpointer.ll @@ -21,4 +21,4 @@ declare void @llvm.write_register.i64(metadata, i64) nounwind ; register unsigned long current_stack_pointer asm("sp"); ; CHECK-NOT: .asciz "sp" -!0 = metadata !{metadata !"sp\00"} +!0 = !{!"sp\00"} diff --git a/test/CodeGen/AArch64/arm64-tls-dynamics.ll b/test/CodeGen/AArch64/arm64-tls-dynamics.ll index e8a83fd..30ea63b 100644 --- a/test/CodeGen/AArch64/arm64-tls-dynamics.ll +++ b/test/CodeGen/AArch64/arm64-tls-dynamics.ll @@ -20,7 +20,7 @@ define i32 @test_generaldynamic() { ; CHECK: mrs x[[TP:[0-9]+]], TPIDR_EL0 ; CHECK: ldr w0, [x[[TP]], x0] -; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE +; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL @@ -43,7 +43,7 @@ define i32* @test_generaldynamic_addr() { ; CHECK: mrs [[TP:x[0-9]+]], TPIDR_EL0 ; CHECK: add x0, [[TP]], x0 -; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE +; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL @@ -73,7 +73,7 @@ define i32 @test_localdynamic() { ; CHECK: ldr w0, [x[[TPIDR]], x[[TPREL]]] -; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE +; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL @@ -101,7 +101,7 @@ define i32* @test_localdynamic_addr() { ; CHECK: add x0, [[TPIDR]], [[TPREL]] -; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE +; CHECK-RELOC: R_AARCH64_TLSDESC_ADR_PAGE21 ; CHECK-RELOC: R_AARCH64_TLSDESC_ADD_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_LD64_LO12_NC ; CHECK-RELOC: R_AARCH64_TLSDESC_CALL diff --git a/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll b/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll index a7f5215..923742d 100644 --- a/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll +++ b/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll @@ -22,10 +22,10 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"= !llvm.ident = !{!0} -!0 = metadata !{metadata !"clang version 3.6.0 "} -!1 = metadata !{metadata !2, metadata !2, i64 0} -!2 = metadata !{metadata !"any pointer", metadata !3, i64 0} -!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0} -!4 = metadata !{metadata !"Simple C/C++ TBAA"} -!5 = metadata !{metadata !6, metadata !6, i64 0} -!6 = metadata !{metadata !"int", metadata !3, i64 0} +!0 = !{!"clang version 3.6.0 "} +!1 = !{!2, !2, i64 0} +!2 = !{!"any pointer", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} +!5 = !{!6, !6, i64 0} +!6 = !{!"int", !3, i64 0} diff --git a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll index 36a7bfd..44f2af1 100644 --- a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll +++ b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll @@ -12,6 +12,7 @@ define void @test_simple(i32 %n, ...) { ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]] ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var +; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var ; CHECK: stp x1, x2, [sp, #[[GR_BASE:[0-9]+]]] ; ... omit middle ones ... @@ -21,11 +22,10 @@ define void @test_simple(i32 %n, ...) { ; ... omit middle ones ... ; CHECK: stp q6, q7, [sp, # -; CHECK: str [[STACK_TOP]], [x[[VA_LIST_HI]], :lo12:var] +; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]] ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]] ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #56 -; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8] ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp @@ -50,6 +50,7 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #[[STACKSIZE]] ; CHECK: adrp x[[VA_LIST_HI:[0-9]+]], var +; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var ; CHECK: stp x3, x4, [sp, #[[GR_BASE:[0-9]+]]] ; ... omit middle ones ... @@ -59,11 +60,10 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { ; ... omit middle ones ... ; CHECK: str q7, [sp, # -; CHECK: str [[STACK_TOP]], [x[[VA_LIST_HI]], :lo12:var] +; CHECK: str [[STACK_TOP]], [x[[VA_LIST]]] ; CHECK: add [[GR_TOPTMP:x[0-9]+]], sp, #[[GR_BASE]] ; CHECK: add [[GR_TOP:x[0-9]+]], [[GR_TOPTMP]], #40 -; CHECK: add x[[VA_LIST:[0-9]+]], {{x[0-9]+}}, :lo12:var ; CHECK: str [[GR_TOP]], [x[[VA_LIST]], #8] ; CHECK: mov [[VR_TOPTMP:x[0-9]+]], sp @@ -89,18 +89,20 @@ define void @test_nospare([8 x i64], [8 x float], ...) { call void @llvm.va_start(i8* %addr) ; CHECK-NOT: sub sp, sp ; CHECK: mov [[STACK:x[0-9]+]], sp -; CHECK: str [[STACK]], [{{x[0-9]+}}, :lo12:var] +; CHECK: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var +; CHECK: str [[STACK]], [x[[VAR]]] ret void } ; If there are non-variadic arguments on the stack (here two i64s) then the ; __stack field should point just past them. -define void @test_offsetstack([10 x i64], [3 x float], ...) { +define void @test_offsetstack([8 x i64], [2 x i64], [3 x float], ...) { ; CHECK-LABEL: test_offsetstack: ; CHECK: sub sp, sp, #80 ; CHECK: add [[STACK_TOP:x[0-9]+]], sp, #96 -; CHECK: str [[STACK_TOP]], [{{x[0-9]+}}, :lo12:var] +; CHECK: add x[[VAR:[0-9]+]], {{x[0-9]+}}, :lo12:var +; CHECK: str [[STACK_TOP]], [x[[VAR]]] %addr = bitcast %va_list* @var to i8* call void @llvm.va_start(i8* %addr) diff --git a/test/CodeGen/AArch64/arm64-vshuffle.ll b/test/CodeGen/AArch64/arm64-vshuffle.ll index 62fd961..75e0d80 100644 --- a/test/CodeGen/AArch64/arm64-vshuffle.ll +++ b/test/CodeGen/AArch64/arm64-vshuffle.ll @@ -29,14 +29,14 @@ entry: } ; CHECK: lCPI1_0: -; CHECK: .byte 2 ; 0x2 +; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 255 ; 0xff -; CHECK: .byte 6 ; 0x6 +; CHECK: .byte 2 ; 0x2 ; CHECK: .byte 255 ; 0xff ; CHECK: .byte 10 ; 0xa ; CHECK: .byte 12 ; 0xc ; CHECK: .byte 14 ; 0xe -; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 7 ; 0x7 ; CHECK: test2 ; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI1_0@PAGEOFF] ; CHECK: adrp x[[REG2:[0-9]+]], lCPI1_1@PAGE @@ -82,22 +82,22 @@ bb: ret <16 x i1> %Shuff } ; CHECK: lCPI3_1: -; CHECK: .byte 2 ; 0x2 -; CHECK: .byte 1 ; 0x1 -; CHECK: .byte 6 ; 0x6 -; CHECK: .byte 18 ; 0x12 -; CHECK: .byte 10 ; 0xa -; CHECK: .byte 12 ; 0xc -; CHECK: .byte 14 ; 0xe ; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 1 ; 0x1 ; CHECK: .byte 2 ; 0x2 -; CHECK: .byte 31 ; 0x1f +; CHECK: .byte 18 ; 0x12 +; CHECK: .byte 4 ; 0x4 +; CHECK: .byte 5 ; 0x5 ; CHECK: .byte 6 ; 0x6 -; CHECK: .byte 30 ; 0x1e +; CHECK: .byte 7 ; 0x7 +; CHECK: .byte 8 ; 0x8 +; CHECK: .byte 31 ; 0x1f ; CHECK: .byte 10 ; 0xa +; CHECK: .byte 30 ; 0x1e ; CHECK: .byte 12 ; 0xc +; CHECK: .byte 13 ; 0xd ; CHECK: .byte 14 ; 0xe -; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 15 ; 0xf ; CHECK: _test4: ; CHECK: ldr q[[REG1:[0-9]+]] ; CHECK: movi.2d v[[REG0:[0-9]+]], #0000000000000000 diff --git a/test/CodeGen/AArch64/bitcast-v2i8.ll b/test/CodeGen/AArch64/bitcast-v2i8.ll new file mode 100644 index 0000000..4bdac64 --- /dev/null +++ b/test/CodeGen/AArch64/bitcast-v2i8.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=aarch64-apple-ios | FileCheck %s + +; Part of PR21549: going through the stack isn't ideal but is correct. + +define i16 @test_bitcast_v2i8_to_i16(<2 x i8> %a) { +; CHECK-LABEL: test_bitcast_v2i8_to_i16 +; CHECK: mov.s [[WREG_HI:w[0-9]+]], v0[1] +; CHECK-NEXT: fmov [[WREG_LO:w[0-9]+]], s0 +; CHECK-NEXT: strb [[WREG_HI]], [sp, #15] +; CHECK-NEXT: strb [[WREG_LO]], [sp, #14] +; CHECK-NEXT: ldrh w0, [sp, #14] + + %aa = bitcast <2 x i8> %a to i16 + ret i16 %aa +} diff --git a/test/CodeGen/AArch64/br-to-eh-lpad.ll b/test/CodeGen/AArch64/br-to-eh-lpad.ll new file mode 100644 index 0000000..20bffd9 --- /dev/null +++ b/test/CodeGen/AArch64/br-to-eh-lpad.ll @@ -0,0 +1,78 @@ +; RUN: llc < %s -mtriple=aarch64-apple-ios -verify-machineinstrs + +; This function tests that the machine verifier accepts an unconditional +; branch from an invoke basic block, to its EH landing pad basic block. +; The test is brittle and isn't ideally reduced, because in most cases the +; branch would be removed (for instance, turned into a fallthrough), and in +; that case, the machine verifier, which relies on analyzing branches for this +; kind of verification, is unable to check anything, so accepts the CFG. + +define void @test_branch_to_landingpad() { +entry: + br i1 undef, label %if.end50.thread, label %if.then6 + +lpad: + %0 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__objc_personality_v0 to i8*) + catch %struct._objc_typeinfo.12.129.194.285.350.493.519.532.571.597.623.765* @"OBJC_EHTYPE_$_NSString" + catch %struct._objc_typeinfo.12.129.194.285.350.493.519.532.571.597.623.765* @OBJC_EHTYPE_id + catch i8* null + br i1 undef, label %invoke.cont33, label %catch.fallthrough + +catch.fallthrough: + %matches31 = icmp eq i32 undef, 0 + br i1 %matches31, label %invoke.cont41, label %finally.catchall + +if.then6: + invoke void @objc_exception_throw() + to label %invoke.cont7 unwind label %lpad + +invoke.cont7: + unreachable + +if.end50.thread: + tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 125) + tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 128) + unreachable + +invoke.cont33: + tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 119) + unreachable + +invoke.cont41: + invoke void @objc_exception_rethrow() + to label %invoke.cont43 unwind label %lpad40 + +invoke.cont43: + unreachable + +lpad40: + %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__objc_personality_v0 to i8*) + catch i8* null + br label %finally.catchall + +finally.catchall: + tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8]* @.str1, i64 0, i64 0), i32 125) + unreachable +} + +%struct._objc_typeinfo.12.129.194.285.350.493.519.532.571.597.623.765 = type { i8**, i8*, %struct._class_t.10.127.192.283.348.491.517.530.569.595.621.764* } +%struct._class_t.10.127.192.283.348.491.517.530.569.595.621.764 = type { %struct._class_t.10.127.192.283.348.491.517.530.569.595.621.764*, %struct._class_t.10.127.192.283.348.491.517.530.569.595.621.764*, %struct._objc_cache.0.117.182.273.338.481.507.520.559.585.611.754*, i8* (i8*, i8*)**, %struct._class_ro_t.9.126.191.282.347.490.516.529.568.594.620.763* } +%struct._objc_cache.0.117.182.273.338.481.507.520.559.585.611.754 = type opaque +%struct._class_ro_t.9.126.191.282.347.490.516.529.568.594.620.763 = type { i32, i32, i32, i8*, i8*, %struct.__method_list_t.2.119.184.275.340.483.509.522.561.587.613.756*, %struct._objc_protocol_list.6.123.188.279.344.487.513.526.565.591.617.760*, %struct._ivar_list_t.8.125.190.281.346.489.515.528.567.593.619.762*, i8*, %struct._prop_list_t.4.121.186.277.342.485.511.524.563.589.615.758* } +%struct.__method_list_t.2.119.184.275.340.483.509.522.561.587.613.756 = type { i32, i32, [0 x %struct._objc_method.1.118.183.274.339.482.508.521.560.586.612.755] } +%struct._objc_method.1.118.183.274.339.482.508.521.560.586.612.755 = type { i8*, i8*, i8* } +%struct._objc_protocol_list.6.123.188.279.344.487.513.526.565.591.617.760 = type { i64, [0 x %struct._protocol_t.5.122.187.278.343.486.512.525.564.590.616.759*] } +%struct._protocol_t.5.122.187.278.343.486.512.525.564.590.616.759 = type { i8*, i8*, %struct._objc_protocol_list.6.123.188.279.344.487.513.526.565.591.617.760*, %struct.__method_list_t.2.119.184.275.340.483.509.522.561.587.613.756*, %struct.__method_list_t.2.119.184.275.340.483.509.522.561.587.613.756*, %struct.__method_list_t.2.119.184.275.340.483.509.522.561.587.613.756*, %struct.__method_list_t.2.119.184.275.340.483.509.522.561.587.613.756*, %struct._prop_list_t.4.121.186.277.342.485.511.524.563.589.615.758*, i32, i32, i8** } +%struct._ivar_list_t.8.125.190.281.346.489.515.528.567.593.619.762 = type { i32, i32, [0 x %struct._ivar_t.7.124.189.280.345.488.514.527.566.592.618.761] } +%struct._ivar_t.7.124.189.280.345.488.514.527.566.592.618.761 = type { i32*, i8*, i8*, i32, i32 } +%struct._prop_list_t.4.121.186.277.342.485.511.524.563.589.615.758 = type { i32, i32, [0 x %struct._prop_t.3.120.185.276.341.484.510.523.562.588.614.757] } +%struct._prop_t.3.120.185.276.341.484.510.523.562.588.614.757 = type { i8*, i8* } + +@.str1 = external unnamed_addr constant [17 x i8], align 1 +@OBJC_EHTYPE_id = external global %struct._objc_typeinfo.12.129.194.285.350.493.519.532.571.597.623.765 +@"OBJC_EHTYPE_$_NSString" = external global %struct._objc_typeinfo.12.129.194.285.350.493.519.532.571.597.623.765, section "__DATA,__datacoal_nt,coalesced", align 8 + +declare void @objc_exception_throw() +declare void @objc_exception_rethrow() +declare i32 @__objc_personality_v0(...) +declare void @printf(i8* nocapture readonly, ...) diff --git a/test/CodeGen/AArch64/combine-comparisons-by-cse.ll b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll index df8dc87..3686a1f 100644 --- a/test/CodeGen/AArch64/combine-comparisons-by-cse.ll +++ b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll @@ -366,7 +366,6 @@ define i32 @fcmpri(i32 %argc, i8** nocapture readonly %argv) { ; CHECK-LABEL-DAG: .LBB9_3 ; CHECK: cmp w19, #0 ; CHECK: fcmp d8, #0.0 -; CHECK: b.gt .LBB9_5 ; CHECK-NOT: cmp w19, #1 ; CHECK-NOT: b.ge .LBB9_5 diff --git a/test/CodeGen/AArch64/compiler-ident.ll b/test/CodeGen/AArch64/compiler-ident.ll index 0350571..217340d 100644 --- a/test/CodeGen/AArch64/compiler-ident.ll +++ b/test/CodeGen/AArch64/compiler-ident.ll @@ -8,5 +8,5 @@ target triple = "aarch64--linux-gnu" !llvm.ident = !{!0} -!0 = metadata !{metadata !"some LLVM version"} +!0 = !{!"some LLVM version"} diff --git a/test/CodeGen/AArch64/cpus.ll b/test/CodeGen/AArch64/cpus.ll index f0f36bd..1266842 100644 --- a/test/CodeGen/AArch64/cpus.ll +++ b/test/CodeGen/AArch64/cpus.ll @@ -4,6 +4,7 @@ ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID ; CHECK-NOT: {{.*}} is not a recognized processor for this target diff --git a/test/CodeGen/AArch64/dp-3source.ll b/test/CodeGen/AArch64/dp-3source.ll index 22bd4a8..bd96ec7 100644 --- a/test/CodeGen/AArch64/dp-3source.ll +++ b/test/CodeGen/AArch64/dp-3source.ll @@ -161,3 +161,18 @@ define i64 @test_umnegl(i32 %lhs, i32 %rhs) { ; CHECK: umnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} ret i64 %res } + +@a = common global i32 0, align 4 +@b = common global i32 0, align 4 +@c = common global i32 0, align 4 + +define void @test_mneg(){ +; CHECK-LABEL: test_mneg: + %1 = load i32* @a, align 4 + %2 = load i32* @b, align 4 + %3 = sub i32 0, %1 + %4 = mul i32 %2, %3 + store i32 %4, i32* @c, align 4 +; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + ret void +} diff --git a/test/CodeGen/AArch64/f16-convert.ll b/test/CodeGen/AArch64/f16-convert.ll index 12412d4..d1f49a91 100644 --- a/test/CodeGen/AArch64/f16-convert.ll +++ b/test/CodeGen/AArch64/f16-convert.ll @@ -133,7 +133,8 @@ define void @store0(i16* nocapture %a, float %val) nounwind { define void @store1(i16* nocapture %a, double %val) nounwind { ; CHECK-LABEL: store1: -; CHECK-NEXT: fcvt h0, d0 +; CHECK-NEXT: fcvt s0, d0 +; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: str h0, [x0] ; CHECK-NEXT: ret @@ -158,7 +159,8 @@ define void @store2(i16* nocapture %a, i32 %i, float %val) nounwind { define void @store3(i16* nocapture %a, i32 %i, double %val) nounwind { ; CHECK-LABEL: store3: -; CHECK-NEXT: fcvt h0, d0 +; CHECK-NEXT: fcvt s0, d0 +; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: str h0, [x0, w1, sxtw #1] ; CHECK-NEXT: ret @@ -184,7 +186,8 @@ define void @store4(i16* nocapture %a, i64 %i, float %val) nounwind { define void @store5(i16* nocapture %a, i64 %i, double %val) nounwind { ; CHECK-LABEL: store5: -; CHECK-NEXT: fcvt h0, d0 +; CHECK-NEXT: fcvt s0, d0 +; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: str h0, [x0, x1, lsl #1] ; CHECK-NEXT: ret @@ -209,7 +212,8 @@ define void @store6(i16* nocapture %a, float %val) nounwind { define void @store7(i16* nocapture %a, double %val) nounwind { ; CHECK-LABEL: store7: -; CHECK-NEXT: fcvt h0, d0 +; CHECK-NEXT: fcvt s0, d0 +; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: str h0, [x0, #20] ; CHECK-NEXT: ret @@ -234,7 +238,8 @@ define void @store8(i16* nocapture %a, float %val) nounwind { define void @store9(i16* nocapture %a, double %val) nounwind { ; CHECK-LABEL: store9: -; CHECK-NEXT: fcvt h0, d0 +; CHECK-NEXT: fcvt s0, d0 +; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: stur h0, [x0, #-20] ; CHECK-NEXT: ret diff --git a/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll b/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll new file mode 100644 index 0000000..bc4a210 --- /dev/null +++ b/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll @@ -0,0 +1,42 @@ +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s + +; CHECK-label: test_or +; CHECK: cbnz w0, {{LBB[0-9]+_2}} +; CHECK: cbz w1, {{LBB[0-9]+_1}} +define i64 @test_or(i32 %a, i32 %b) { +bb1: + %0 = icmp eq i32 %a, 0 + %1 = icmp eq i32 %b, 0 + %or.cond = or i1 %0, %1 + br i1 %or.cond, label %bb3, label %bb4, !prof !0 + +bb3: + ret i64 0 + +bb4: + %2 = call i64 @bar() + ret i64 %2 +} + +; CHECK-label: test_ans +; CHECK: cbz w0, {{LBB[0-9]+_2}} +; CHECK: cbnz w1, {{LBB[0-9]+_3}} +define i64 @test_and(i32 %a, i32 %b) { +bb1: + %0 = icmp ne i32 %a, 0 + %1 = icmp ne i32 %b, 0 + %or.cond = and i1 %0, %1 + br i1 %or.cond, label %bb4, label %bb3, !prof !1 + +bb3: + ret i64 0 + +bb4: + %2 = call i64 @bar() + ret i64 %2 +} + +declare i64 @bar() + +!0 = !{!"branch_weights", i32 5128, i32 32} +!1 = !{!"branch_weights", i32 1024, i32 4136} diff --git a/test/CodeGen/AArch64/fast-isel-branch_weights.ll b/test/CodeGen/AArch64/fast-isel-branch_weights.ll index 5b22476..70dbdf2 100644 --- a/test/CodeGen/AArch64/fast-isel-branch_weights.ll +++ b/test/CodeGen/AArch64/fast-isel-branch_weights.ll @@ -16,4 +16,4 @@ success: ret i64 0 } -!0 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647} +!0 = !{!"branch_weights", i32 0, i32 2147483647} diff --git a/test/CodeGen/AArch64/fast-isel-memcpy.ll b/test/CodeGen/AArch64/fast-isel-memcpy.ll new file mode 100644 index 0000000..9161dad --- /dev/null +++ b/test/CodeGen/AArch64/fast-isel-memcpy.ll @@ -0,0 +1,15 @@ +; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s + +; Test that we don't segfault. +; CHECK-LABEL: test +; CHECK: ldr [[REG1:x[0-9]+]], [x1] +; CHECK-NEXT: and [[REG2:x[0-9]+]], x0, #0x7fffffffffffffff +; CHECK-NEXT: str [[REG1]], {{\[}}[[REG2]]{{\]}} +define void @test(i64 %a, i8* %b) { + %1 = and i64 %a, 9223372036854775807 + %2 = inttoptr i64 %1 to i8* + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %b, i64 8, i32 8, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) diff --git a/test/CodeGen/AArch64/fast-isel-tbz.ll b/test/CodeGen/AArch64/fast-isel-tbz.ll index d7f46b2..a5f02ff 100644 --- a/test/CodeGen/AArch64/fast-isel-tbz.ll +++ b/test/CodeGen/AArch64/fast-isel-tbz.ll @@ -1,5 +1,5 @@ -; RUN: llc -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s -; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s +; RUN: llc -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -fast-isel -fast-isel-abort -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s define i32 @icmp_eq_i8(i8 zeroext %a) { ; CHECK-LABEL: icmp_eq_i8 @@ -121,6 +121,160 @@ bb2: ret i32 0 } +define i32 @icmp_slt_i8(i8 zeroext %a) { +; FAST-LABEL: icmp_slt_i8 +; FAST: tbnz w0, #7, {{LBB.+_2}} + %1 = icmp slt i8 %a, 0 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_slt_i16(i16 zeroext %a) { +; FAST-LABEL: icmp_slt_i16 +; FAST: tbnz w0, #15, {{LBB.+_2}} + %1 = icmp slt i16 %a, 0 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_slt_i32(i32 %a) { +; CHECK-LABEL: icmp_slt_i32 +; CHECK: tbnz w0, #31, {{LBB.+_2}} + %1 = icmp slt i32 %a, 0 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_slt_i64(i64 %a) { +; CHECK-LABEL: icmp_slt_i64 +; CHECK: tbnz x0, #63, {{LBB.+_2}} + %1 = icmp slt i64 %a, 0 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sge_i8(i8 zeroext %a) { +; FAST-LABEL: icmp_sge_i8 +; FAST: tbz w0, #7, {{LBB.+_2}} + %1 = icmp sge i8 %a, 0 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sge_i16(i16 zeroext %a) { +; FAST-LABEL: icmp_sge_i16 +; FAST: tbz w0, #15, {{LBB.+_2}} + %1 = icmp sge i16 %a, 0 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sle_i8(i8 zeroext %a) { +; FAST-LABEL: icmp_sle_i8 +; FAST: tbnz w0, #7, {{LBB.+_2}} + %1 = icmp sle i8 %a, -1 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sle_i16(i16 zeroext %a) { +; FAST-LABEL: icmp_sle_i16 +; FAST: tbnz w0, #15, {{LBB.+_2}} + %1 = icmp sle i16 %a, -1 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sle_i32(i32 %a) { +; CHECK-LABEL: icmp_sle_i32 +; CHECK: tbnz w0, #31, {{LBB.+_2}} + %1 = icmp sle i32 %a, -1 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sle_i64(i64 %a) { +; CHECK-LABEL: icmp_sle_i64 +; CHECK: tbnz x0, #63, {{LBB.+_2}} + %1 = icmp sle i64 %a, -1 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sgt_i8(i8 zeroext %a) { +; FAST-LABEL: icmp_sgt_i8 +; FAST: tbz w0, #7, {{LBB.+_2}} + %1 = icmp sgt i8 %a, -1 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sgt_i16(i16 zeroext %a) { +; FAST-LABEL: icmp_sgt_i16 +; FAST: tbz w0, #15, {{LBB.+_2}} + %1 = icmp sgt i16 %a, -1 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sgt_i32(i32 %a) { +; CHECK-LABEL: icmp_sgt_i32 +; CHECK: tbz w0, #31, {{LBB.+_2}} + %1 = icmp sgt i32 %a, -1 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + +define i32 @icmp_sgt_i64(i64 %a) { +; FAST-LABEL: icmp_sgt_i64 +; FAST: tbz x0, #63, {{LBB.+_2}} + %1 = icmp sgt i64 %a, -1 + br i1 %1, label %bb1, label %bb2, !prof !0 +bb1: + ret i32 1 +bb2: + ret i32 0 +} + ; Test that we don't fold the 'and' instruction into the compare. define i32 @icmp_eq_and_i32(i32 %a, i1 %c) { ; CHECK-LABEL: icmp_eq_and_i32 @@ -137,5 +291,5 @@ bb2: ret i32 0 } -!0 = metadata !{metadata !"branch_weights", i32 0, i32 2147483647} -!1 = metadata !{metadata !"branch_weights", i32 2147483647, i32 0} +!0 = !{!"branch_weights", i32 0, i32 2147483647} +!1 = !{!"branch_weights", i32 2147483647, i32 0} diff --git a/test/CodeGen/AArch64/fdiv-combine.ll b/test/CodeGen/AArch64/fdiv-combine.ll new file mode 100644 index 0000000..389eefd --- /dev/null +++ b/test/CodeGen/AArch64/fdiv-combine.ll @@ -0,0 +1,94 @@ +; RUN: llc -march=aarch64 < %s | FileCheck %s + +; Following test cases check: +; a / D; b / D; c / D; +; => +; recip = 1.0 / D; a * recip; b * recip; c * recip; +define void @three_fdiv_float(float %D, float %a, float %b, float %c) #0 { +; CHECK-LABEL: three_fdiv_float: +; CHECK: fdiv +; CHECK-NEXT-NOT: fdiv +; CHECK: fmul +; CHECK: fmul +; CHECK: fmul + %div = fdiv float %a, %D + %div1 = fdiv float %b, %D + %div2 = fdiv float %c, %D + tail call void @foo_3f(float %div, float %div1, float %div2) + ret void +} + +define void @three_fdiv_double(double %D, double %a, double %b, double %c) #0 { +; CHECK-LABEL: three_fdiv_double: +; CHECK: fdiv +; CHECK-NEXT-NOT: fdiv +; CHECK: fmul +; CHECK: fmul +; CHECK: fmul + %div = fdiv double %a, %D + %div1 = fdiv double %b, %D + %div2 = fdiv double %c, %D + tail call void @foo_3d(double %div, double %div1, double %div2) + ret void +} + +define void @three_fdiv_4xfloat(<4 x float> %D, <4 x float> %a, <4 x float> %b, <4 x float> %c) #0 { +; CHECK-LABEL: three_fdiv_4xfloat: +; CHECK: fdiv +; CHECK-NEXT-NOT: fdiv +; CHECK: fmul +; CHECK: fmul +; CHECK: fmul + %div = fdiv <4 x float> %a, %D + %div1 = fdiv <4 x float> %b, %D + %div2 = fdiv <4 x float> %c, %D + tail call void @foo_3_4xf(<4 x float> %div, <4 x float> %div1, <4 x float> %div2) + ret void +} + +define void @three_fdiv_2xdouble(<2 x double> %D, <2 x double> %a, <2 x double> %b, <2 x double> %c) #0 { +; CHECK-LABEL: three_fdiv_2xdouble: +; CHECK: fdiv +; CHECK-NEXT-NOT: fdiv +; CHECK: fmul +; CHECK: fmul +; CHECK: fmul + %div = fdiv <2 x double> %a, %D + %div1 = fdiv <2 x double> %b, %D + %div2 = fdiv <2 x double> %c, %D + tail call void @foo_3_2xd(<2 x double> %div, <2 x double> %div1, <2 x double> %div2) + ret void +} + +; Following test cases check we never combine two FDIVs if neither of them +; calculates a reciprocal. +define void @two_fdiv_float(float %D, float %a, float %b) #0 { +; CHECK-LABEL: two_fdiv_float: +; CHECK: fdiv +; CHECK: fdiv +; CHECK-NEXT-NOT: fmul + %div = fdiv float %a, %D + %div1 = fdiv float %b, %D + tail call void @foo_2f(float %div, float %div1) + ret void +} + +define void @two_fdiv_double(double %D, double %a, double %b) #0 { +; CHECK-LABEL: two_fdiv_double: +; CHECK: fdiv +; CHECK: fdiv +; CHECK-NEXT-NOT: fmul + %div = fdiv double %a, %D + %div1 = fdiv double %b, %D + tail call void @foo_2d(double %div, double %div1) + ret void +} + +declare void @foo_3f(float, float, float) +declare void @foo_3d(double, double, double) +declare void @foo_3_4xf(<4 x float>, <4 x float>, <4 x float>) +declare void @foo_3_2xd(<2 x double>, <2 x double>, <2 x double>) +declare void @foo_2f(float, float) +declare void @foo_2d(double, double) + +attributes #0 = { "unsafe-fp-math"="true" } diff --git a/test/CodeGen/AArch64/fp16-v8-instructions.ll b/test/CodeGen/AArch64/fp16-v8-instructions.ll index 9ee2296..b75f160 100644 --- a/test/CodeGen/AArch64/fp16-v8-instructions.ll +++ b/test/CodeGen/AArch64/fp16-v8-instructions.ll @@ -188,10 +188,10 @@ define <8 x half> @s_to_h(<8 x float> %a) { define <8 x half> @d_to_h(<8 x double> %a) { ; CHECK-LABEL: d_to_h: -; CHECK-DAG: ins v{{[0-9]+}}.d -; CHECK-DAG: ins v{{[0-9]+}}.d -; CHECK-DAG: ins v{{[0-9]+}}.d -; CHECK-DAG: ins v{{[0-9]+}}.d +; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] +; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] +; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] +; CHECK-DAG: mov d{{[0-9]+}}, v{{[0-9]+}}.d[1] ; CHECK-DAG: fcvt h ; CHECK-DAG: fcvt h ; CHECK-DAG: fcvt h diff --git a/test/CodeGen/AArch64/fpimm.ll b/test/CodeGen/AArch64/fpimm.ll index e59520c..b7db918 100644 --- a/test/CodeGen/AArch64/fpimm.ll +++ b/test/CodeGen/AArch64/fpimm.ll @@ -1,4 +1,6 @@ -; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE +; RUN: llc -mtriple=aarch64-apple-darwin -code-model=large -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s --check-prefix=LARGE @varf32 = global float 0.0 @varf64 = global double 0.0 @@ -34,3 +36,22 @@ define void @check_double() { ; CHECK: ret ret void } + +; LARGE-LABEL: check_float2 +; LARGE: movz [[REG:w[0-9]+]], #0x4049, lsl #16 +; LARGE-NEXT: movk [[REG]], #0xfdb +; LARGE-NEXT: fmov s0, [[REG]] +define float @check_float2() { + ret float 3.14159274101257324218750 +} + +; LARGE-LABEL: check_double2 +; LARGE: movz [[REG:x[0-9]+]], #0x4009, lsl #48 +; LARGE-NEXT: movk [[REG]], #0x21fb, lsl #32 +; LARGE-NEXT: movk [[REG]], #0x5444, lsl #16 +; LARGE-NEXT: movk [[REG]], #0x2d18 +; LARGE-NEXT: fmov d0, [[REG]] +define double @check_double2() { + ret double 3.1415926535897931159979634685441851615905761718750 +} + diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll index abb732c..9fc9a5f 100644 --- a/test/CodeGen/AArch64/func-argpassing.ll +++ b/test/CodeGen/AArch64/func-argpassing.ll @@ -96,10 +96,8 @@ define [2 x i64] @return_struct() { %addr = bitcast %myStruct* @varstruct to [2 x i64]* %val = load [2 x i64]* %addr ret [2 x i64] %val -; CHECK-DAG: ldr x0, [{{x[0-9]+}}, {{#?}}:lo12:varstruct] - ; Odd register regex below disallows x0 which we want to be live now. -; CHECK-DAG: add {{x[1-9][0-9]*}}, {{x[1-9][0-9]*}}, {{#?}}:lo12:varstruct -; CHECK: ldr x1, [{{x[1-9][0-9]*}}, #8] +; CHECK: add x[[VARSTRUCT:[0-9]+]], {{x[0-9]+}}, :lo12:varstruct +; CHECK: ldp x0, x1, [x[[VARSTRUCT]]] ; Make sure epilogue immediately follows ; CHECK-NEXT: ret } @@ -166,8 +164,8 @@ define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3, define i64 @check_i128_regalign(i32 %val0, i128 %val1, i64 %val2) { ; CHECK-LABEL: check_i128_regalign store i128 %val1, i128* @var128 -; CHECK-DAG: str x2, [{{x[0-9]+}}, {{#?}}:lo12:var128] -; CHECK-DAG: str x3, [{{x[0-9]+}}, #8] +; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128 +; CHECK-DAG: stp x2, x3, [x[[VAR128]]] ret i64 %val2 ; CHECK: mov x0, x4 diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll index 51979f0..16157f8 100644 --- a/test/CodeGen/AArch64/func-calls.ll +++ b/test/CodeGen/AArch64/func-calls.ll @@ -62,8 +62,8 @@ define void @simple_rets() { %arr = call [2 x i64] @return_smallstruct() store [2 x i64] %arr, [2 x i64]* @varsmallstruct ; CHECK: bl return_smallstruct -; CHECK: str x1, [{{x[0-9]+}}, #8] -; CHECK: str x0, [{{x[0-9]+}}, {{#?}}:lo12:varsmallstruct] +; CHECK: add x[[VARSMALLSTRUCT:[0-9]+]], {{x[0-9]+}}, :lo12:varsmallstruct +; CHECK: stp x0, x1, [x[[VARSMALLSTRUCT]]] call void @return_large_struct(%myStruct* sret @varstruct) ; CHECK: add x8, {{x[0-9]+}}, {{#?}}:lo12:varstruct @@ -128,12 +128,12 @@ define void @check_i128_align() { call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 42, i128 %val) -; CHECK: ldr [[I128LO:x[0-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:var128] -; CHECK: ldr [[I128HI:x[0-9]+]], [{{x[0-9]+}}, #8] +; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128 +; CHECK: ldp [[I128LO:x[0-9]+]], [[I128HI:x[0-9]+]], [x[[VAR128]]] ; CHECK: stp [[I128LO]], [[I128HI]], [sp, #16] -; CHECK-NONEON: ldr [[I128LO:x[0-9]+]], [{{x[0-9]+}}, :lo12:var128] -; CHECK-NONEON: ldr [[I128HI:x[0-9]+]], [{{x[0-9]+}}, #8] +; CHECK-NONEON: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128 +; CHECK-NONEON: ldp [[I128LO:x[0-9]+]], [[I128HI:x[0-9]+]], [x[[VAR128]]] ; CHECK-NONEON: stp [[I128LO]], [[I128HI]], [sp, #16] ; CHECK: bl check_i128_stackalign diff --git a/test/CodeGen/AArch64/ghc-cc.ll b/test/CodeGen/AArch64/ghc-cc.ll new file mode 100644 index 0000000..505bd5f --- /dev/null +++ b/test/CodeGen/AArch64/ghc-cc.ll @@ -0,0 +1,89 @@ +; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s + +; Check the GHC call convention works (aarch64) + +@base = external global i64 ; assigned to register: r19 +@sp = external global i64 ; assigned to register: r20 +@hp = external global i64 ; assigned to register: r21 +@r1 = external global i64 ; assigned to register: r22 +@r2 = external global i64 ; assigned to register: r23 +@r3 = external global i64 ; assigned to register: r24 +@r4 = external global i64 ; assigned to register: r25 +@r5 = external global i64 ; assigned to register: r26 +@r6 = external global i64 ; assigned to register: r27 +@splim = external global i64 ; assigned to register: r28 + +@f1 = external global float ; assigned to register: s8 +@f2 = external global float ; assigned to register: s9 +@f3 = external global float ; assigned to register: s10 +@f4 = external global float ; assigned to register: s11 + +@d1 = external global double ; assigned to register: d12 +@d2 = external global double ; assigned to register: d13 +@d3 = external global double ; assigned to register: d14 +@d4 = external global double ; assigned to register: d15 + +define ghccc i64 @addtwo(i64 %x, i64 %y) nounwind { +entry: + ; CHECK-LABEL: addtwo + ; CHECK: add x0, x19, x20 + ; CHECK-NEXT: ret + %0 = add i64 %x, %y + ret i64 %0 +} + +define void @zap(i64 %a, i64 %b) nounwind { +entry: + ; CHECK-LABEL: zap + ; CHECK-NOT: mov {{x[0-9]+}}, sp + ; CHECK: bl addtwo + ; CHECK-NEXT: bl foo + %0 = call ghccc i64 @addtwo(i64 %a, i64 %b) + call void @foo() nounwind + ret void +} + +define ghccc void @foo_i64 () nounwind { +entry: + ; CHECK-LABEL: foo_i64 + ; CHECK: adrp {{x[0-9]+}}, base + ; CHECK-NEXT: ldr x19, [{{x[0-9]+}}, :lo12:base] + ; CHECK-NEXT: bl bar_i64 + ; CHECK-NEXT: ret + + %0 = load i64* @base + tail call ghccc void @bar_i64( i64 %0 ) nounwind + ret void +} + +define ghccc void @foo_float () nounwind { +entry: + ; CHECK-LABEL: foo_float + ; CHECK: adrp {{x[0-9]+}}, f1 + ; CHECK-NEXT: ldr s8, [{{x[0-9]+}}, :lo12:f1] + ; CHECK-NEXT: bl bar_float + ; CHECK-NEXT: ret + + %0 = load float* @f1 + tail call ghccc void @bar_float( float %0 ) nounwind + ret void +} + +define ghccc void @foo_double () nounwind { +entry: + ; CHECK-LABEL: foo_double + ; CHECK: adrp {{x[0-9]+}}, d1 + ; CHECK-NEXT: ldr d12, [{{x[0-9]+}}, :lo12:d1] + ; CHECK-NEXT: bl bar_double + ; CHECK-NEXT: ret + + %0 = load double* @d1 + tail call ghccc void @bar_double( double %0 ) nounwind + ret void +} + +declare ghccc void @foo () + +declare ghccc void @bar_i64 (i64) +declare ghccc void @bar_float (float) +declare ghccc void @bar_double (double) diff --git a/test/CodeGen/AArch64/global-merge-1.ll b/test/CodeGen/AArch64/global-merge-1.ll index 68aba5e..7dc8da1 100644 --- a/test/CodeGen/AArch64/global-merge-1.ll +++ b/test/CodeGen/AArch64/global-merge-1.ll @@ -11,6 +11,7 @@ @n = internal global i32 0, align 4 define void @f1(i32 %a1, i32 %a2) { +;CHECK-APPLE-IOS-NOT: adrp ;CHECK-APPLE-IOS: adrp x8, __MergedGlobals@PAGE ;CHECK-APPLE-IOS-NOT: adrp ;CHECK-APPLE-IOS: add x8, x8, __MergedGlobals@PAGEOFF diff --git a/test/CodeGen/AArch64/global-merge-2.ll b/test/CodeGen/AArch64/global-merge-2.ll index a773566..70b700c 100644 --- a/test/CodeGen/AArch64/global-merge-2.ll +++ b/test/CodeGen/AArch64/global-merge-2.ll @@ -8,6 +8,7 @@ define void @f1(i32 %a1, i32 %a2) { ;CHECK-APPLE-IOS-LABEL: _f1: +;CHECK-APPLE-IOS-NOT: adrp ;CHECK-APPLE-IOS: adrp x8, __MergedGlobals_x@PAGE ;CHECK-APPLE-IOS: add x8, x8, __MergedGlobals_x@PAGEOFF ;CHECK-APPLE-IOS-NOT: adrp diff --git a/test/CodeGen/AArch64/implicit-sret.ll b/test/CodeGen/AArch64/implicit-sret.ll new file mode 100644 index 0000000..264d519 --- /dev/null +++ b/test/CodeGen/AArch64/implicit-sret.ll @@ -0,0 +1,13 @@ +; RUN: llc %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s +; +; Handle implicit sret arguments that are generated on-the-fly during lowering. +; Null pointer assertion in AArch64TargetLowering + +; CHECK-LABEL: big_retval +; ... str or stp for the first 1024 bits +; CHECK: strb wzr, [x8, #128] +; CHECK: ret +define i1032 @big_retval() { +entry: + ret i1032 0 +} diff --git a/test/CodeGen/AArch64/large_shift.ll b/test/CodeGen/AArch64/large_shift.ll new file mode 100644 index 0000000..f72c97d --- /dev/null +++ b/test/CodeGen/AArch64/large_shift.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=aarch64 -o - %s +target triple = "arm64-unknown-unknown" + +; Make sure we don't run into an assert in the aarch64 code selection when +; DAGCombining fails. + +declare void @t() + +define void @foo() { + %c = bitcast i64 270458 to i64 + %t0 = lshr i64 %c, 422383 + %t1 = trunc i64 %t0 to i1 + br i1 %t1, label %BB1, label %BB0 + +BB0: + call void @t() + br label %BB1 + +BB1: + ret void +} diff --git a/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll b/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll new file mode 100644 index 0000000..e77824f --- /dev/null +++ b/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -mtriple=aarch64-apple-ios -fast-isel -verify-machineinstrs | FileCheck %s + +; Check that the kill flag is cleared between CSE'd instructions on their +; imp-def'd registers. +; The verifier would complain otherwise. +define i64 @csed-impdef-killflag(i64 %a) { +; CHECK-LABEL: csed-impdef-killflag +; CHECK-DAG: mov [[REG0:w[0-9]+]], wzr +; CHECK-DAG: orr [[REG1:w[0-9]+]], wzr, #0x1 +; CHECK-DAG: orr [[REG2:x[0-9]+]], xzr, #0x2 +; CHECK-DAG: orr [[REG3:x[0-9]+]], xzr, #0x3 +; CHECK: cmp x0, #0 +; CHECK-DAG: csel w[[SELECT_WREG_1:[0-9]+]], [[REG0]], [[REG1]], ne +; CHECK-DAG: csel [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne +; CHECK: ubfx [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32 +; CHECK-NEXT: add x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]] +; CHECK-NEXT: ret + + %1 = icmp ne i64 %a, 0 + %2 = select i1 %1, i32 0, i32 1 + %3 = icmp ne i64 %a, 0 + %4 = select i1 %3, i64 2, i64 3 + %5 = zext i32 %2 to i64 + %6 = add i64 %4, %5 + ret i64 %6 +} diff --git a/test/CodeGen/AArch64/neon-scalar-copy.ll b/test/CodeGen/AArch64/neon-scalar-copy.ll index 6afac31..3f77060 100644 --- a/test/CodeGen/AArch64/neon-scalar-copy.ll +++ b/test/CodeGen/AArch64/neon-scalar-copy.ll @@ -1,101 +1,145 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -asm-verbose=false < %s | FileCheck %s - -define float @test_dup_sv2S(<2 x float> %v) { - ; CHECK-LABEL: test_dup_sv2S - ; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +define float @test_dup_sv2S(<2 x float> %v) #0 { + ; CHECK-LABEL: test_dup_sv2S: + ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1] + ; CHECK-NEXT: ret %tmp1 = extractelement <2 x float> %v, i32 1 ret float %tmp1 } -define float @test_dup_sv2S_0(<2 x float> %v) { - ; CHECK-LABEL: test_dup_sv2S_0 +define float @test_dup_sv2S_0(<2 x float> %v) #0 { + ; CHECK-LABEL: test_dup_sv2S_0: ; CHECK-NOT: dup {{[vsd][0-9]+}} ; CHECK-NOT: ins {{[vsd][0-9]+}} - ; CHECK: ret + ; CHECK-NEXT: ret %tmp1 = extractelement <2 x float> %v, i32 0 ret float %tmp1 } -define float @test_dup_sv4S(<4 x float> %v) { - ; CHECK-LABEL: test_dup_sv4S +define float @test_dup_sv4S(<4 x float> %v) #0 { + ; CHECK-LABEL: test_dup_sv4S: + ; CHECK-NEXT: mov s{{[0-9]+}}, {{v[0-9]+}}.s[1] + ; CHECK-NEXT: ret + %tmp1 = extractelement <4 x float> %v, i32 1 + ret float %tmp1 +} + +define float @test_dup_sv4S_0(<4 x float> %v) #0 { + ; CHECK-LABEL: test_dup_sv4S_0: ; CHECK-NOT: dup {{[vsd][0-9]+}} ; CHECK-NOT: ins {{[vsd][0-9]+}} - ; CHECK: ret + ; CHECK-NEXT: ret %tmp1 = extractelement <4 x float> %v, i32 0 ret float %tmp1 } -define double @test_dup_dvD(<1 x double> %v) { - ; CHECK-LABEL: test_dup_dvD +define double @test_dup_dvD(<1 x double> %v) #0 { + ; CHECK-LABEL: test_dup_dvD: ; CHECK-NOT: dup {{[vsd][0-9]+}} ; CHECK-NOT: ins {{[vsd][0-9]+}} - ; CHECK: ret + ; CHECK-NEXT: ret %tmp1 = extractelement <1 x double> %v, i32 0 ret double %tmp1 } -define double @test_dup_dv2D(<2 x double> %v) { - ; CHECK-LABEL: test_dup_dv2D - ; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] +define double @test_dup_dv2D(<2 x double> %v) #0 { + ; CHECK-LABEL: test_dup_dv2D: + ; CHECK-NEXT: mov d{{[0-9]+}}, {{v[0-9]+}}.d[1] + ; CHECK-NEXT: ret %tmp1 = extractelement <2 x double> %v, i32 1 ret double %tmp1 } -define double @test_dup_dv2D_0(<2 x double> %v) { - ; CHECK-LABEL: test_dup_dv2D_0 - ; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] - ; CHECK: ret - %tmp1 = extractelement <2 x double> %v, i32 1 +define double @test_dup_dv2D_0(<2 x double> %v) #0 { + ; CHECK-LABEL: test_dup_dv2D_0: + ; CHECK-NOT: dup {{[vsd][0-9]+}} + ; CHECK-NOT: ins {{[vsd][0-9]+}} + ; CHECK-NEXT: ret + %tmp1 = extractelement <2 x double> %v, i32 0 ret double %tmp1 } -define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) { - ; CHECK-LABEL: test_vector_dup_bv16B +define half @test_dup_hv8H(<8 x half> %v) #0 { + ; CHECK-LABEL: test_dup_hv8H: + ; CHECK-NEXT: mov h{{[0-9]+}}, {{v[0-9]+}}.h[1] + ; CHECK-NEXT: ret + %tmp1 = extractelement <8 x half> %v, i32 1 + ret half %tmp1 +} + +define half @test_dup_hv8H_0(<8 x half> %v) #0 { + ; CHECK-LABEL: test_dup_hv8H_0: + ; CHECK-NOT: dup {{[vsdh][0-9]+}} + ; CHECK-NOT: ins {{[vsdh][0-9]+}} + ; CHECK-NEXT: ret + %tmp1 = extractelement <8 x half> %v, i32 0 + ret half %tmp1 +} + +define <1 x i8> @test_vector_dup_bv16B(<16 x i8> %v1) #0 { + ; CHECK-LABEL: test_vector_dup_bv16B: + ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.b[14] + ; CHECK-NEXT: fmov s0, [[W]] + ; CHECK-NEXT: ret %shuffle.i = shufflevector <16 x i8> %v1, <16 x i8> undef, <1 x i32> ret <1 x i8> %shuffle.i } -define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) { - ; CHECK-LABEL: test_vector_dup_bv8B +define <1 x i8> @test_vector_dup_bv8B(<8 x i8> %v1) #0 { + ; CHECK-LABEL: test_vector_dup_bv8B: + ; CHECK-NEXT: dup v0.8b, v0.b[7] + ; CHECK-NEXT: ret %shuffle.i = shufflevector <8 x i8> %v1, <8 x i8> undef, <1 x i32> ret <1 x i8> %shuffle.i } -define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) { - ; CHECK-LABEL: test_vector_dup_hv8H +define <1 x i16> @test_vector_dup_hv8H(<8 x i16> %v1) #0 { + ; CHECK-LABEL: test_vector_dup_hv8H: + ; CHECK-NEXT: umov [[W:w[0-9]+]], v0.h[7] + ; CHECK-NEXT: fmov s0, [[W]] + ; CHECK-NEXT: ret %shuffle.i = shufflevector <8 x i16> %v1, <8 x i16> undef, <1 x i32> ret <1 x i16> %shuffle.i } -define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) { - ; CHECK-LABEL: test_vector_dup_hv4H +define <1 x i16> @test_vector_dup_hv4H(<4 x i16> %v1) #0 { + ; CHECK-LABEL: test_vector_dup_hv4H: + ; CHECK-NEXT: dup v0.4h, v0.h[3] + ; CHECK-NEXT: ret %shuffle.i = shufflevector <4 x i16> %v1, <4 x i16> undef, <1 x i32> ret <1 x i16> %shuffle.i } -define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) { - ; CHECK-LABEL: test_vector_dup_sv4S +define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 { + ; CHECK-LABEL: test_vector_dup_sv4S: + ; CHECK-NEXT: mov [[W:w[0-9]+]], v0.s[3] + ; CHECK-NEXT: fmov s0, [[W]] + ; CHECK-NEXT: ret %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> ret <1 x i32> %shuffle } -define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) { - ; CHECK-LABEL: test_vector_dup_sv2S +define <1 x i32> @test_vector_dup_sv2S(<2 x i32> %v1) #0 { + ; CHECK-LABEL: test_vector_dup_sv2S: + ; CHECK-NEXT: dup v0.2s, v0.s[1] + ; CHECK-NEXT: ret %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <1 x i32> ret <1 x i32> %shuffle } -define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) { - ; CHECK-LABEL: test_vector_dup_dv2D - ; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8 +define <1 x i64> @test_vector_dup_dv2D(<2 x i64> %v1) #0 { + ; CHECK-LABEL: test_vector_dup_dv2D: + ; CHECK-NEXT: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #8 + ; CHECK-NEXT: ret %shuffle.i = shufflevector <2 x i64> %v1, <2 x i64> undef, <1 x i32> ret <1 x i64> %shuffle.i } -define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) { - ; CHECK-LABEL: test_vector_copy_dup_dv2D - ; CHECK: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1] +define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 { + ; CHECK-LABEL: test_vector_copy_dup_dv2D: + ; CHECK-NEXT: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1] + ; CHECK-NEXT: ret %vget_lane = extractelement <2 x i64> %c, i32 1 %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0 ret <1 x i64> %vset_lane @@ -118,3 +162,5 @@ define void @test_out_of_range_insert(<4 x i32> %vec, i32 %elt) { insertelement <4 x i32> %vec, i32 %elt, i32 4 ret void } + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/or-combine.ll b/test/CodeGen/AArch64/or-combine.ll new file mode 100644 index 0000000..c6c343a --- /dev/null +++ b/test/CodeGen/AArch64/or-combine.ll @@ -0,0 +1,44 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s + +define i32 @test_consts(i32 %in) { +; CHECK-LABEL: test_consts: +; CHECK-NOT: bfxil +; CHECK-NOT: and +; CHECK-NOT: orr +; CHECK: ret + + %lo = and i32 %in, 65535 + %hi = and i32 %in, -65536 + %res = or i32 %lo, %hi + ret i32 %res +} + +define i32 @test_generic(i32 %in, i32 %mask1, i32 %mask2) { +; CHECK-LABEL: test_generic: +; CHECK: orr [[FULL_MASK:w[0-9]+]], w1, w2 +; CHECK: and w0, w0, [[FULL_MASK]] + + %lo = and i32 %in, %mask1 + %hi = and i32 %in, %mask2 + %res = or i32 %lo, %hi + ret i32 %res +} + +; In this case the transformation isn't profitable, since %lo and %hi +; are used more than once. +define [3 x i32] @test_reuse(i32 %in, i32 %mask1, i32 %mask2) { +; CHECK-LABEL: test_reuse: +; CHECK-DAG: and w1, w0, w1 +; CHECK-DAG: and w2, w0, w2 +; CHECK-DAG: orr w0, w1, w2 + + %lo = and i32 %in, %mask1 + %hi = and i32 %in, %mask2 + %recombine = or i32 %lo, %hi + + %res.tmp0 = insertvalue [3 x i32] undef, i32 %recombine, 0 + %res.tmp1 = insertvalue [3 x i32] %res.tmp0, i32 %lo, 1 + %res = insertvalue [3 x i32] %res.tmp1, i32 %hi, 2 + + ret [3 x i32] %res +} diff --git a/test/CodeGen/AArch64/ragreedy-csr.ll b/test/CodeGen/AArch64/ragreedy-csr.ll index de29b1b..31ff543 100644 --- a/test/CodeGen/AArch64/ragreedy-csr.ll +++ b/test/CodeGen/AArch64/ragreedy-csr.ll @@ -271,27 +271,27 @@ return: %retval.0 = phi i32 [ 0, %entry ], [ 1, %land.lhs.true52 ], [ 1, %land.lhs.true43 ], [ 0, %if.else123 ], [ 1, %while.cond59.preheader ], [ 1, %while.cond95.preheader ], [ 1, %while.cond130.preheader ], [ 1, %land.lhs.true28 ], [ 1, %if.then83 ], [ 0, %lor.lhs.false74 ], [ 1, %land.rhs ], [ 1, %if.then117 ], [ 0, %while.body104 ], [ 1, %land.rhs99 ], [ 1, %if.then152 ], [ 0, %while.body139 ], [ 1, %land.rhs134 ], [ 0, %while.body ] ret i32 %retval.0 } -!181 = metadata !{metadata !"branch_weights", i32 662038, i32 1} -!988 = metadata !{metadata !"branch_weights", i32 12091450, i32 1916} -!989 = metadata !{metadata !"branch_weights", i32 7564670, i32 4526781} -!990 = metadata !{metadata !"branch_weights", i32 7484958, i32 13283499} -!991 = metadata !{metadata !"branch_weights", i32 8677007, i32 4606493} -!992 = metadata !{metadata !"branch_weights", i32 -1172426948, i32 145094705} -!993 = metadata !{metadata !"branch_weights", i32 1468914, i32 5683688} -!994 = metadata !{metadata !"branch_weights", i32 114025221, i32 -1217548794, i32 -1199521551, i32 87712616} -!995 = metadata !{metadata !"branch_weights", i32 1853716452, i32 -444717951, i32 932776759} -!996 = metadata !{metadata !"branch_weights", i32 1004870, i32 20259} -!997 = metadata !{metadata !"branch_weights", i32 20071, i32 189} -!998 = metadata !{metadata !"branch_weights", i32 -1020255939, i32 572177766} -!999 = metadata !{metadata !"branch_weights", i32 2666513, i32 3466431} -!1000 = metadata !{metadata !"branch_weights", i32 5117635, i32 1859780} -!1001 = metadata !{metadata !"branch_weights", i32 354902465, i32 -1444604407} -!1002 = metadata !{metadata !"branch_weights", i32 -1762419279, i32 1592770684} -!1003 = metadata !{metadata !"branch_weights", i32 1435905930, i32 -1951930624} -!1004 = metadata !{metadata !"branch_weights", i32 1, i32 504888} -!1005 = metadata !{metadata !"branch_weights", i32 94662, i32 504888} -!1006 = metadata !{metadata !"branch_weights", i32 -1897793104, i32 160196332} -!1007 = metadata !{metadata !"branch_weights", i32 2074643678, i32 -29579071} -!1008 = metadata !{metadata !"branch_weights", i32 1, i32 226163} -!1009 = metadata !{metadata !"branch_weights", i32 58357, i32 226163} -!1010 = metadata !{metadata !"branch_weights", i32 -2072848646, i32 92907517} +!181 = !{!"branch_weights", i32 662038, i32 1} +!988 = !{!"branch_weights", i32 12091450, i32 1916} +!989 = !{!"branch_weights", i32 7564670, i32 4526781} +!990 = !{!"branch_weights", i32 7484958, i32 13283499} +!991 = !{!"branch_weights", i32 8677007, i32 4606493} +!992 = !{!"branch_weights", i32 -1172426948, i32 145094705} +!993 = !{!"branch_weights", i32 1468914, i32 5683688} +!994 = !{!"branch_weights", i32 114025221, i32 -1217548794, i32 -1199521551, i32 87712616} +!995 = !{!"branch_weights", i32 1853716452, i32 -444717951, i32 932776759} +!996 = !{!"branch_weights", i32 1004870, i32 20259} +!997 = !{!"branch_weights", i32 20071, i32 189} +!998 = !{!"branch_weights", i32 -1020255939, i32 572177766} +!999 = !{!"branch_weights", i32 2666513, i32 3466431} +!1000 = !{!"branch_weights", i32 5117635, i32 1859780} +!1001 = !{!"branch_weights", i32 354902465, i32 -1444604407} +!1002 = !{!"branch_weights", i32 -1762419279, i32 1592770684} +!1003 = !{!"branch_weights", i32 1435905930, i32 -1951930624} +!1004 = !{!"branch_weights", i32 1, i32 504888} +!1005 = !{!"branch_weights", i32 94662, i32 504888} +!1006 = !{!"branch_weights", i32 -1897793104, i32 160196332} +!1007 = !{!"branch_weights", i32 2074643678, i32 -29579071} +!1008 = !{!"branch_weights", i32 1, i32 226163} +!1009 = !{!"branch_weights", i32 58357, i32 226163} +!1010 = !{!"branch_weights", i32 -2072848646, i32 92907517} diff --git a/test/CodeGen/AArch64/remat.ll b/test/CodeGen/AArch64/remat.ll index 32b3ed2..8b3e6dd 100644 --- a/test/CodeGen/AArch64/remat.ll +++ b/test/CodeGen/AArch64/remat.ll @@ -1,5 +1,6 @@ ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s %X = type { i64, i64, i64 } declare void @f(%X*) diff --git a/test/CodeGen/AArch64/setcc-type-mismatch.ll b/test/CodeGen/AArch64/setcc-type-mismatch.ll new file mode 100644 index 0000000..86817fa --- /dev/null +++ b/test/CodeGen/AArch64/setcc-type-mismatch.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s + +define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) { +; CHECK-LABEL: test_mismatched_setcc: +; CHECK: cmeq [[CMP128:v[0-9]+]].4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +; CHECK: xtn {{v[0-9]+}}.4h, [[CMP128]].4s + + %tst = icmp eq <4 x i22> %l, %r + store <4 x i1> %tst, <4 x i1>* %addr + ret void +} diff --git a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll index 4894116..37e41ec 100644 --- a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll +++ b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll @@ -1,6 +1,11 @@ -; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*baz | count 1 -; RUN: llc < %s -march=arm -enable-tail-merge | grep bl.*quux | count 1 +; RUN: llc < %s -march=arm | FileCheck %s + ; Check that calls to baz and quux are tail-merged. +; CHECK: bl _baz +; CHECK-NOT: bl _baz +; CHECK: bl _quux +; CHECK-NOT: bl _quux + ; PR1628 ; ModuleID = 'tail.c' diff --git a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll index acbab8a..30ae723 100644 --- a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll +++ b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll @@ -1,10 +1,23 @@ -; RUN: llc < %s -march=arm | grep bl.*baz | count 1 -; RUN: llc < %s -march=arm | grep bl.*quux | count 1 -; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*baz | count 2 -; RUN: llc < %s -march=arm -enable-tail-merge=0 | grep bl.*quux | count 2 -; Check that tail merging is the default on ARM, and that -enable-tail-merge=0 works. +; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -enable-tail-merge=0 | \ +; RUN: FileCheck --check-prefix=NOMERGE %s + +; Check that tail merging is the default on ARM, and that -enable-tail-merge=0 +; works. ; PR1628 +; CHECK: bl _baz +; CHECK-NOT: bl _baz + +; CHECK: bl _quux +; CHECK-NOT: bl _quux + +; NOMERGE: bl _baz +; NOMERGE: bl _baz + +; NOMERGE: bl _quux +; NOMERGE: bl _quux + ; ModuleID = 'tail.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" target triple = "i686-apple-darwin8" diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll index b4e758d..de05644 100644 --- a/test/CodeGen/ARM/2009-10-16-Scope.ll +++ b/test/CodeGen/ARM/2009-10-16-Scope.ll @@ -9,7 +9,7 @@ entry: br label %do.body, !dbg !0 do.body: ; preds = %entry - call void @llvm.dbg.declare(metadata !{i32* %count_}, metadata !4, metadata !{metadata !"0x102"}) + call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !{!"0x102"}) %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; [#uses=1] %call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; [#uses=0] br label %do.end, !dbg !0 @@ -22,13 +22,13 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare i32 @foo(i32) ssp -!0 = metadata !{i32 5, i32 2, metadata !1, null} -!1 = metadata !{metadata !"0xb\001\001\000", null, metadata !2}; [DW_TAG_lexical_block ] -!2 = metadata !{metadata !"0x2e\00bar\00bar\00bar\004\000\001\000\006\000\000\000", i32 0, metadata !3, null, null, null, null, null, null}; [DW_TAG_subprogram ] -!3 = metadata !{metadata !"0x11\0012\00clang 1.1\001\00\000\00\000", metadata !8, null, metadata !9, null, null, null}; [DW_TAG_compile_unit ] -!4 = metadata !{metadata !"0x100\00count_\005\000", metadata !5, metadata !3, metadata !6}; [ DW_TAG_auto_variable ] -!5 = metadata !{metadata !"0xb\001\001\000", null, metadata !1}; [DW_TAG_lexical_block ] -!6 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, metadata !3}; [DW_TAG_base_type ] -!7 = metadata !{i32 6, i32 1, metadata !2, null} -!8 = metadata !{metadata !"genmodes.i", metadata !"/Users/yash/Downloads"} -!9 = metadata !{i32 0} +!0 = !MDLocation(line: 5, column: 2, scope: !1) +!1 = !{!"0xb\001\001\000", null, !2}; [DW_TAG_lexical_block ] +!2 = !{!"0x2e\00bar\00bar\00bar\004\000\001\000\006\000\000\000", i32 0, !3, null, null, null, null, null, null}; [DW_TAG_subprogram ] +!3 = !{!"0x11\0012\00clang 1.1\001\00\000\00\000", !8, null, !9, null, null, null}; [DW_TAG_compile_unit ] +!4 = !{!"0x100\00count_\005\000", !5, !3, !6}; [ DW_TAG_auto_variable ] +!5 = !{!"0xb\001\001\000", null, !1}; [DW_TAG_lexical_block ] +!6 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !3}; [DW_TAG_base_type ] +!7 = !MDLocation(line: 6, column: 1, scope: !2) +!8 = !{!"genmodes.i", !"/Users/yash/Downloads"} +!9 = !{i32 0} diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll index bce3120..6f7db93 100644 --- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -5,7 +5,7 @@ target triple = "armv4t-apple-darwin10" define hidden i32 @__addvsi3(i32 %a, i32 %b) nounwind { entry: - tail call void @llvm.dbg.value(metadata !{i32 %b}, i64 0, metadata !0, metadata !{metadata !"0x102"}) + tail call void @llvm.dbg.value(metadata i32 %b, i64 0, metadata !0, metadata !{!"0x102"}) %0 = add nsw i32 %b, %a, !dbg !9 ; [#uses=1] ret i32 %0, !dbg !11 } @@ -14,19 +14,19 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!15} -!0 = metadata !{metadata !"0x101\00b\0093\000", metadata !1, metadata !2, metadata !6} ; [ DW_TAG_arg_variable ] -!1 = metadata !{metadata !"0x2e\00__addvsi3\00__addvsi3\00__addvsi3\0094\000\001\000\006\000\000\000", metadata !12, null, metadata !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!2 = metadata !{metadata !"0x29", metadata !12} ; [ DW_TAG_file_type ] -!12 = metadata !{metadata !"libgcc2.c", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc"} -!3 = metadata !{metadata !"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)\001\00\000\00\000", metadata !12, metadata !13, metadata !13, metadata !14, null, null} ; [ DW_TAG_compile_unit ] -!4 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !12, metadata !2, null, metadata !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!5 = metadata !{metadata !6, metadata !6, metadata !6} -!6 = metadata !{metadata !"0x16\00SItype\00152\000\000\000\000", metadata !12, null, metadata !8} ; [ DW_TAG_typedef ] -!7 = metadata !{metadata !"0x29", metadata !"libgcc2.h", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !3} ; [ DW_TAG_file_type ] -!8 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", metadata !12, metadata !2} ; [ DW_TAG_base_type ] -!9 = metadata !{i32 95, i32 0, metadata !10, null} -!10 = metadata !{metadata !"0xb\0094\000\000", metadata !12, metadata !1} ; [ DW_TAG_lexical_block ] -!11 = metadata !{i32 100, i32 0, metadata !10, null} -!13 = metadata !{i32 0} -!14 = metadata !{metadata !1} -!15 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x101\00b\0093\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] +!1 = !{!"0x2e\00__addvsi3\00__addvsi3\00__addvsi3\0094\000\001\000\006\000\000\000", !12, null, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] +!2 = !{!"0x29", !12} ; [ DW_TAG_file_type ] +!12 = !{!"libgcc2.c", !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc"} +!3 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)\001\00\000\00\000", !12, !13, !13, !14, null, null} ; [ DW_TAG_compile_unit ] +!4 = !{!"0x15\00\000\000\000\000\000\000", !12, !2, null, !5, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!5 = !{!6, !6, !6} +!6 = !{!"0x16\00SItype\00152\000\000\000\000", !12, null, !8} ; [ DW_TAG_typedef ] +!7 = !{!"0x29", !"libgcc2.h", !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", !3} ; [ DW_TAG_file_type ] +!8 = !{!"0x24\00int\000\0032\0032\000\000\005", !12, !2} ; [ DW_TAG_base_type ] +!9 = !MDLocation(line: 95, scope: !10) +!10 = !{!"0xb\0094\000\000", !12, !1} ; [ DW_TAG_lexical_block ] +!11 = !MDLocation(line: 100, scope: !10) +!13 = !{i32 0} +!14 = !{!1} +!15 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll index efe1ab5..18b3be0 100644 --- a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll +++ b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll @@ -7,16 +7,16 @@ target triple = "thumbv7-apple-darwin3.0.0-iphoneos" define void @x0(i8* nocapture %buf, i32 %nbytes) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8* %buf}, i64 0, metadata !0, metadata !{metadata !"0x102"}), !dbg !15 - tail call void @llvm.dbg.value(metadata !{i32 %nbytes}, i64 0, metadata !8, metadata !{metadata !"0x102"}), !dbg !16 + tail call void @llvm.dbg.value(metadata i8* %buf, i64 0, metadata !0, metadata !{!"0x102"}), !dbg !15 + tail call void @llvm.dbg.value(metadata i32 %nbytes, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !16 %tmp = load i32* @length, !dbg !17 ; [#uses=3] %cmp = icmp eq i32 %tmp, -1, !dbg !17 ; [#uses=1] %cmp.not = xor i1 %cmp, true ; [#uses=1] %cmp3 = icmp ult i32 %tmp, %nbytes, !dbg !17 ; [#uses=1] %or.cond = and i1 %cmp.not, %cmp3 ; [#uses=1] - tail call void @llvm.dbg.value(metadata !{i32 %tmp}, i64 0, metadata !8, metadata !{metadata !"0x102"}), !dbg !17 + tail call void @llvm.dbg.value(metadata i32 %tmp, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !17 %nbytes.addr.0 = select i1 %or.cond, i32 %tmp, i32 %nbytes ; [#uses=1] - tail call void @llvm.dbg.value(metadata !18, i64 0, metadata !10, metadata !{metadata !"0x102"}), !dbg !19 + tail call void @llvm.dbg.value(metadata i32 0, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !19 br label %while.cond, !dbg !20 while.cond: ; preds = %while.body, %entry @@ -47,30 +47,30 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.lv.fn = !{!0, !8, !10, !12} !llvm.dbg.gv = !{!14} -!0 = metadata !{metadata !"0x101\00buf\004\000", metadata !1, metadata !2, metadata !6} ; [ DW_TAG_arg_variable ] -!1 = metadata !{metadata !"0x2e\00x0\00x0\00x0\005\000\001\000\006\000\000\000", metadata !26, null, metadata !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!2 = metadata !{metadata !"0x29", metadata !26} ; [ DW_TAG_file_type ] -!3 = metadata !{metadata !"0x11\0012\00clang 2.0\001\00\00\00\00", metadata !26, null, null, null, null, null} ; [ DW_TAG_compile_unit ] -!4 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !26, metadata !2, null, metadata !5, null} ; [ DW_TAG_subroutine_type ] -!5 = metadata !{null} -!6 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", metadata !26, metadata !2, metadata !7} ; [ DW_TAG_pointer_type ] -!7 = metadata !{metadata !"0x24\00unsigned char\000\008\008\000\000\008", metadata !26, metadata !2} ; [ DW_TAG_base_type ] -!8 = metadata !{metadata !"0x101\00nbytes\004\000", metadata !1, metadata !2, metadata !9} ; [ DW_TAG_arg_variable ] -!9 = metadata !{metadata !"0x24\00unsigned long\000\0032\0032\000\000\007", metadata !26, metadata !2} ; [ DW_TAG_base_type ] -!10 = metadata !{metadata !"0x100\00nread\006\000", metadata !11, metadata !2, metadata !9} ; [ DW_TAG_auto_variable ] -!11 = metadata !{metadata !"0xb\005\001\000", metadata !26, metadata !1} ; [ DW_TAG_lexical_block ] -!12 = metadata !{metadata !"0x100\00c\007\000", metadata !11, metadata !2, metadata !13} ; [ DW_TAG_auto_variable ] -!13 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", metadata !26, metadata !2} ; [ DW_TAG_base_type ] -!14 = metadata !{metadata !"0x34\00length\00length\00length\001\000\001", metadata !2, metadata !2, metadata !13, i32* @length} ; [ DW_TAG_variable ] -!15 = metadata !{i32 4, i32 24, metadata !1, null} -!16 = metadata !{i32 4, i32 43, metadata !1, null} -!17 = metadata !{i32 9, i32 2, metadata !11, null} -!18 = metadata !{i32 0} -!19 = metadata !{i32 10, i32 2, metadata !11, null} -!20 = metadata !{i32 11, i32 2, metadata !11, null} -!21 = metadata !{i32 12, i32 3, metadata !22, null} -!22 = metadata !{metadata !"0xb\0011\0045\000", metadata !26, metadata !11} ; [ DW_TAG_lexical_block ] -!23 = metadata !{i32 13, i32 3, metadata !22, null} -!24 = metadata !{i32 14, i32 2, metadata !22, null} -!25 = metadata !{i32 15, i32 1, metadata !11, null} -!26 = metadata !{metadata !"t.c", metadata !"/private/tmp"} +!0 = !{!"0x101\00buf\004\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] +!1 = !{!"0x2e\00x0\00x0\00x0\005\000\001\000\006\000\000\000", !26, null, !4, null, null, null, null, null} ; [ DW_TAG_subprogram ] +!2 = !{!"0x29", !26} ; [ DW_TAG_file_type ] +!3 = !{!"0x11\0012\00clang 2.0\001\00\00\00\00", !26, null, null, null, null, null} ; [ DW_TAG_compile_unit ] +!4 = !{!"0x15\00\000\000\000\000\000\000", !26, !2, null, !5, null} ; [ DW_TAG_subroutine_type ] +!5 = !{null} +!6 = !{!"0xf\00\000\0032\0032\000\000", !26, !2, !7} ; [ DW_TAG_pointer_type ] +!7 = !{!"0x24\00unsigned char\000\008\008\000\000\008", !26, !2} ; [ DW_TAG_base_type ] +!8 = !{!"0x101\00nbytes\004\000", !1, !2, !9} ; [ DW_TAG_arg_variable ] +!9 = !{!"0x24\00unsigned long\000\0032\0032\000\000\007", !26, !2} ; [ DW_TAG_base_type ] +!10 = !{!"0x100\00nread\006\000", !11, !2, !9} ; [ DW_TAG_auto_variable ] +!11 = !{!"0xb\005\001\000", !26, !1} ; [ DW_TAG_lexical_block ] +!12 = !{!"0x100\00c\007\000", !11, !2, !13} ; [ DW_TAG_auto_variable ] +!13 = !{!"0x24\00int\000\0032\0032\000\000\005", !26, !2} ; [ DW_TAG_base_type ] +!14 = !{!"0x34\00length\00length\00length\001\000\001", !2, !2, !13, i32* @length} ; [ DW_TAG_variable ] +!15 = !MDLocation(line: 4, column: 24, scope: !1) +!16 = !MDLocation(line: 4, column: 43, scope: !1) +!17 = !MDLocation(line: 9, column: 2, scope: !11) +!18 = !{i32 0} +!19 = !MDLocation(line: 10, column: 2, scope: !11) +!20 = !MDLocation(line: 11, column: 2, scope: !11) +!21 = !MDLocation(line: 12, column: 3, scope: !22) +!22 = !{!"0xb\0011\0045\000", !26, !11} ; [ DW_TAG_lexical_block ] +!23 = !MDLocation(line: 13, column: 3, scope: !22) +!24 = !MDLocation(line: 14, column: 2, scope: !22) +!25 = !MDLocation(line: 15, column: 1, scope: !11) +!26 = !{!"t.c", !"/private/tmp"} diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index f10408c..f71a6c9 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -6,8 +6,8 @@ define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp { entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.value(metadata !{i32 %i}, i64 0, metadata !23, metadata !{metadata !"0x102"}), !dbg !24 - call void @llvm.dbg.value(metadata !{%struct.SVal* %location}, i64 0, metadata !25, metadata !{metadata !"0x102"}), !dbg !24 + call void @llvm.dbg.value(metadata i32 %i, i64 0, metadata !23, metadata !{!"0x102"}), !dbg !24 + call void @llvm.dbg.value(metadata %struct.SVal* %location, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !24 %0 = icmp ne i32 %i, 0, !dbg !27 ; [#uses=1] br i1 %0, label %bb, label %bb1, !dbg !27 @@ -34,7 +34,7 @@ return: ; preds = %bb2 define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 { entry: %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.value(metadata !{%struct.SVal* %this}, i64 0, metadata !31, metadata !{metadata !"0x102"}), !dbg !34 + call void @llvm.dbg.value(metadata %struct.SVal* %this, i64 0, metadata !31, metadata !{!"0x102"}), !dbg !34 %0 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 0, !dbg !34 ; [#uses=1] store i8* null, i8** %0, align 8, !dbg !34 %1 = getelementptr inbounds %struct.SVal* %this, i32 0, i32 1, !dbg !34 ; [#uses=1] @@ -52,7 +52,7 @@ entry: %0 = alloca %struct.SVal ; <%struct.SVal*> [#uses=3] %v = alloca %struct.SVal ; <%struct.SVal*> [#uses=4] %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] - call void @llvm.dbg.declare(metadata !{%struct.SVal* %v}, metadata !38, metadata !{metadata !"0x102"}), !dbg !41 + call void @llvm.dbg.declare(metadata %struct.SVal* %v, metadata !38, metadata !{!"0x102"}), !dbg !41 call void @_ZN4SValC1Ev(%struct.SVal* %v) nounwind, !dbg !41 %1 = getelementptr inbounds %struct.SVal* %v, i32 0, i32 1, !dbg !42 ; [#uses=1] store i32 1, i32* %1, align 8, !dbg !42 @@ -65,7 +65,7 @@ entry: %7 = load i32* %6, align 8, !dbg !43 ; [#uses=1] store i32 %7, i32* %5, align 8, !dbg !43 %8 = call i32 @_Z3fooi4SVal(i32 2, %struct.SVal* noalias %0) nounwind, !dbg !43 ; [#uses=0] - call void @llvm.dbg.value(metadata !{i32 %8}, i64 0, metadata !44, metadata !{metadata !"0x102"}), !dbg !43 + call void @llvm.dbg.value(metadata i32 %8, i64 0, metadata !44, metadata !{!"0x102"}), !dbg !43 br label %return, !dbg !45 return: ; preds = %entry @@ -77,53 +77,53 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!49} -!0 = metadata !{metadata !"0x2e\00SVal\00SVal\00\0011\000\000\000\006\000\000\000", metadata !48, metadata !1, metadata !14, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!1 = metadata !{metadata !"0x13\00SVal\001\00128\0064\000\000\000", metadata !48, null, null, metadata !4, null, null, null} ; [ DW_TAG_structure_type ] [SVal] [line 1, size 128, align 64, offset 0] [def] [from ] -!2 = metadata !{metadata !"0x29", metadata !48} ; [ DW_TAG_file_type ] -!3 = metadata !{metadata !"0x11\004\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\001", metadata !48, metadata !47, metadata !47, metadata !46, metadata !47, metadata !47} ; [ DW_TAG_compile_unit ] -!4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} -!5 = metadata !{metadata !"0xd\00Data\007\0064\0064\000\000", metadata !48, metadata !1, metadata !6} ; [ DW_TAG_member ] -!6 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", metadata !48, null, null} ; [ DW_TAG_pointer_type ] -!7 = metadata !{metadata !"0xd\00Kind\008\0032\0032\0064\000", metadata !48, metadata !1, metadata !8} ; [ DW_TAG_member ] -!8 = metadata !{metadata !"0x24\00unsigned int\000\0032\0032\000\000\007", metadata !48, null} ; [ DW_TAG_base_type ] -!9 = metadata !{metadata !"0x2e\00~SVal\00~SVal\00\0012\000\000\000\006\000\000\000", metadata !48, metadata !1, metadata !10, null, null, null, null, null} ; [ DW_TAG_subprogram ] -!10 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !48, null, null, metadata !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!11 = metadata !{null, metadata !12, metadata !13} -!12 = metadata !{metadata !"0xf\00\000\0064\0064\000\0064", metadata !48, null, metadata !1} ; [ DW_TAG_pointer_type ] -!13 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", metadata !48, null} ; [ DW_TAG_base_type ] -!14 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !48, null, null, metadata !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!15 = metadata !{null, metadata !12} -!16 = metadata !{metadata !"0x2e\00SVal\00SVal\00_ZN4SValC1Ev\0011\000\001\000\006\000\000\000", metadata !48, metadata !1, metadata !14, null, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null} ; [ DW_TAG_subprogram ] -!17 = metadata !{metadata !"0x2e\00foo\00foo\00_Z3fooi4SVal\0016\000\001\000\006\000\000\000", metadata !48, metadata !2, metadata !18, null, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null} ; [ DW_TAG_subprogram ] -!18 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !48, null, null, metadata !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!19 = metadata !{metadata !13, metadata !13, metadata !1} -!20 = metadata !{metadata !"0x2e\00main\00main\00main\0023\000\001\000\006\000\000\000", metadata !48, metadata !2, metadata !21, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ] -!21 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !48, null, null, metadata !22, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!22 = metadata !{metadata !13} -!23 = metadata !{metadata !"0x101\00i\0016\000", metadata !17, metadata !2, metadata !13} ; [ DW_TAG_arg_variable ] -!24 = metadata !{i32 16, i32 0, metadata !17, null} -!25 = metadata !{metadata !"0x101\00location\0016\000", metadata !17, metadata !2, metadata !26} ; [ DW_TAG_arg_variable ] -!26 = metadata !{metadata !"0x10\00SVal\000\0064\0064\000\000", metadata !48, metadata !2, metadata !1} ; [ DW_TAG_reference_type ] -!27 = metadata !{i32 17, i32 0, metadata !28, null} -!28 = metadata !{metadata !"0xb\0016\000\002", metadata !2, metadata !17} ; [ DW_TAG_lexical_block ] -!29 = metadata !{i32 18, i32 0, metadata !28, null} -!30 = metadata !{i32 20, i32 0, metadata !28, null} -!31 = metadata !{metadata !"0x101\00this\0011\000", metadata !16, metadata !2, metadata !32} ; [ DW_TAG_arg_variable ] -!32 = metadata !{metadata !"0x26\00\000\0064\0064\000\0064", metadata !48, metadata !2, metadata !33} ; [ DW_TAG_const_type ] -!33 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", metadata !48, metadata !2, metadata !1} ; [ DW_TAG_pointer_type ] -!34 = metadata !{i32 11, i32 0, metadata !16, null} -!35 = metadata !{i32 11, i32 0, metadata !36, null} -!36 = metadata !{metadata !"0xb\0011\000\001", metadata !48, metadata !37} ; [ DW_TAG_lexical_block ] -!37 = metadata !{metadata !"0xb\0011\000\000", metadata !48, metadata !16} ; [ DW_TAG_lexical_block ] -!38 = metadata !{metadata !"0x100\00v\0024\000", metadata !39, metadata !2, metadata !1} ; [ DW_TAG_auto_variable ] -!39 = metadata !{metadata !"0xb\0023\000\004", metadata !48, metadata !40} ; [ DW_TAG_lexical_block ] -!40 = metadata !{metadata !"0xb\0023\000\003", metadata !48, metadata !20} ; [ DW_TAG_lexical_block ] -!41 = metadata !{i32 24, i32 0, metadata !39, null} -!42 = metadata !{i32 25, i32 0, metadata !39, null} -!43 = metadata !{i32 26, i32 0, metadata !39, null} -!44 = metadata !{metadata !"0x100\00k\0026\000", metadata !39, metadata !2, metadata !13} ; [ DW_TAG_auto_variable ] -!45 = metadata !{i32 27, i32 0, metadata !39, null} -!46 = metadata !{metadata !16, metadata !17, metadata !20} -!47 = metadata !{} -!48 = metadata !{metadata !"small.cc", metadata !"/Users/manav/R8248330"} -!49 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x2e\00SVal\00SVal\00\0011\000\000\000\006\000\000\000", !48, !1, !14, null, null, null, null, null} ; [ DW_TAG_subprogram ] +!1 = !{!"0x13\00SVal\001\00128\0064\000\000\000", !48, null, null, !4, null, null, null} ; [ DW_TAG_structure_type ] [SVal] [line 1, size 128, align 64, offset 0] [def] [from ] +!2 = !{!"0x29", !48} ; [ DW_TAG_file_type ] +!3 = !{!"0x11\004\004.2.1 (Based on Apple Inc. build 5658) (LLVM build)\000\00\000\00\001", !48, !47, !47, !46, !47, !47} ; [ DW_TAG_compile_unit ] +!4 = !{!5, !7, !0, !9} +!5 = !{!"0xd\00Data\007\0064\0064\000\000", !48, !1, !6} ; [ DW_TAG_member ] +!6 = !{!"0xf\00\000\0064\0064\000\000", !48, null, null} ; [ DW_TAG_pointer_type ] +!7 = !{!"0xd\00Kind\008\0032\0032\0064\000", !48, !1, !8} ; [ DW_TAG_member ] +!8 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", !48, null} ; [ DW_TAG_base_type ] +!9 = !{!"0x2e\00~SVal\00~SVal\00\0012\000\000\000\006\000\000\000", !48, !1, !10, null, null, null, null, null} ; [ DW_TAG_subprogram ] +!10 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !11, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!11 = !{null, !12, !13} +!12 = !{!"0xf\00\000\0064\0064\000\0064", !48, null, !1} ; [ DW_TAG_pointer_type ] +!13 = !{!"0x24\00int\000\0032\0032\000\000\005", !48, null} ; [ DW_TAG_base_type ] +!14 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !15, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!15 = !{null, !12} +!16 = !{!"0x2e\00SVal\00SVal\00_ZN4SValC1Ev\0011\000\001\000\006\000\000\000", !48, !1, !14, null, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null} ; [ DW_TAG_subprogram ] +!17 = !{!"0x2e\00foo\00foo\00_Z3fooi4SVal\0016\000\001\000\006\000\000\000", !48, !2, !18, null, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null} ; [ DW_TAG_subprogram ] +!18 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !19, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!19 = !{!13, !13, !1} +!20 = !{!"0x2e\00main\00main\00main\0023\000\001\000\006\000\000\000", !48, !2, !21, null, i32 ()* @main, null, null, null} ; [ DW_TAG_subprogram ] +!21 = !{!"0x15\00\000\000\000\000\000\000", !48, null, null, !22, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!22 = !{!13} +!23 = !{!"0x101\00i\0016\000", !17, !2, !13} ; [ DW_TAG_arg_variable ] +!24 = !MDLocation(line: 16, scope: !17) +!25 = !{!"0x101\00location\0016\000", !17, !2, !26} ; [ DW_TAG_arg_variable ] +!26 = !{!"0x10\00SVal\000\0064\0064\000\000", !48, !2, !1} ; [ DW_TAG_reference_type ] +!27 = !MDLocation(line: 17, scope: !28) +!28 = !{!"0xb\0016\000\002", !2, !17} ; [ DW_TAG_lexical_block ] +!29 = !MDLocation(line: 18, scope: !28) +!30 = !MDLocation(line: 20, scope: !28) +!31 = !{!"0x101\00this\0011\000", !16, !2, !32} ; [ DW_TAG_arg_variable ] +!32 = !{!"0x26\00\000\0064\0064\000\0064", !48, !2, !33} ; [ DW_TAG_const_type ] +!33 = !{!"0xf\00\000\0064\0064\000\000", !48, !2, !1} ; [ DW_TAG_pointer_type ] +!34 = !MDLocation(line: 11, scope: !16) +!35 = !MDLocation(line: 11, scope: !36) +!36 = !{!"0xb\0011\000\001", !48, !37} ; [ DW_TAG_lexical_block ] +!37 = !{!"0xb\0011\000\000", !48, !16} ; [ DW_TAG_lexical_block ] +!38 = !{!"0x100\00v\0024\000", !39, !2, !1} ; [ DW_TAG_auto_variable ] +!39 = !{!"0xb\0023\000\004", !48, !40} ; [ DW_TAG_lexical_block ] +!40 = !{!"0xb\0023\000\003", !48, !20} ; [ DW_TAG_lexical_block ] +!41 = !MDLocation(line: 24, scope: !39) +!42 = !MDLocation(line: 25, scope: !39) +!43 = !MDLocation(line: 26, scope: !39) +!44 = !{!"0x100\00k\0026\000", !39, !2, !13} ; [ DW_TAG_auto_variable ] +!45 = !MDLocation(line: 27, scope: !39) +!46 = !{!16, !17, !20} +!47 = !{} +!48 = !{!"small.cc", !"/Users/manav/R8248330"} +!49 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index 7fbd3ba..67dda67 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -30,9 +30,9 @@ target triple = "thumbv7-apple-darwin10" define zeroext i8 @get1(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !10, metadata !{metadata !"0x102"}), !dbg !30 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !30 %0 = load i8* @x1, align 4, !dbg !30 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !11, metadata !{metadata !"0x102"}), !dbg !30 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !30 store i8 %a, i8* @x1, align 4, !dbg !30 ret i8 %0, !dbg !31 } @@ -41,36 +41,36 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon define zeroext i8 @get2(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !18, metadata !{metadata !"0x102"}), !dbg !32 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !32 %0 = load i8* @x2, align 4, !dbg !32 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !19, metadata !{metadata !"0x102"}), !dbg !32 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !32 store i8 %a, i8* @x2, align 4, !dbg !32 ret i8 %0, !dbg !33 } define zeroext i8 @get3(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !21, metadata !{metadata !"0x102"}), !dbg !34 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !34 %0 = load i8* @x3, align 4, !dbg !34 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !22, metadata !{metadata !"0x102"}), !dbg !34 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !34 store i8 %a, i8* @x3, align 4, !dbg !34 ret i8 %0, !dbg !35 } define zeroext i8 @get4(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !24, metadata !{metadata !"0x102"}), !dbg !36 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !24, metadata !{!"0x102"}), !dbg !36 %0 = load i8* @x4, align 4, !dbg !36 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !25, metadata !{metadata !"0x102"}), !dbg !36 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !25, metadata !{!"0x102"}), !dbg !36 store i8 %a, i8* @x4, align 4, !dbg !36 ret i8 %0, !dbg !37 } define zeroext i8 @get5(i8 zeroext %a) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8 %a}, i64 0, metadata !27, metadata !{metadata !"0x102"}), !dbg !38 + tail call void @llvm.dbg.value(metadata i8 %a, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !38 %0 = load i8* @x5, align 4, !dbg !38 - tail call void @llvm.dbg.value(metadata !{i8 %0}, i64 0, metadata !28, metadata !{metadata !"0x102"}), !dbg !38 + tail call void @llvm.dbg.value(metadata i8 %0, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !38 store i8 %a, i8* @x5, align 4, !dbg !38 ret i8 %0, !dbg !39 } @@ -78,53 +78,53 @@ entry: !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!49} -!0 = metadata !{metadata !"0x2e\00get1\00get1\00get1\004\000\001\000\006\00256\001\004", metadata !47, metadata !1, metadata !3, null, i8 (i8)* @get1, null, null, metadata !42} ; [ DW_TAG_subprogram ] -!1 = metadata !{metadata !"0x29", metadata !47} ; [ DW_TAG_file_type ] -!2 = metadata !{metadata !"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)\001\00\000\00\000", metadata !47, metadata !48, metadata !48, metadata !40, metadata !41, metadata !48} ; [ DW_TAG_compile_unit ] -!3 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !47, metadata !1, null, metadata !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!4 = metadata !{metadata !5, metadata !5} -!5 = metadata !{metadata !"0x24\00_Bool\000\008\008\000\000\002", metadata !47, metadata !1} ; [ DW_TAG_base_type ] -!6 = metadata !{metadata !"0x2e\00get2\00get2\00get2\007\000\001\000\006\00256\001\007", metadata !47, metadata !1, metadata !3, null, i8 (i8)* @get2, null, null, metadata !43} ; [ DW_TAG_subprogram ] -!7 = metadata !{metadata !"0x2e\00get3\00get3\00get3\0010\000\001\000\006\00256\001\0010", metadata !47, metadata !1, metadata !3, null, i8 (i8)* @get3, null, null, metadata !44} ; [ DW_TAG_subprogram ] -!8 = metadata !{metadata !"0x2e\00get4\00get4\00get4\0013\000\001\000\006\00256\001\0013", metadata !47, metadata !1, metadata !3, null, i8 (i8)* @get4, null, null, metadata !45} ; [ DW_TAG_subprogram ] -!9 = metadata !{metadata !"0x2e\00get5\00get5\00get5\0016\000\001\000\006\00256\001\0016", metadata !47, metadata !1, metadata !3, null, i8 (i8)* @get5, null, null, metadata !46} ; [ DW_TAG_subprogram ] -!10 = metadata !{metadata !"0x101\00a\004\000", metadata !0, metadata !1, metadata !5} ; [ DW_TAG_arg_variable ] -!11 = metadata !{metadata !"0x100\00b\004\000", metadata !12, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!12 = metadata !{metadata !"0xb\004\000\000", metadata !47, metadata !0} ; [ DW_TAG_lexical_block ] -!13 = metadata !{metadata !"0x34\00x1\00x1\00\003\001\001", metadata !1, metadata !1, metadata !5, i8* @x1, null} ; [ DW_TAG_variable ] -!14 = metadata !{metadata !"0x34\00x2\00x2\00\006\001\001", metadata !1, metadata !1, metadata !5, i8* @x2, null} ; [ DW_TAG_variable ] -!15 = metadata !{metadata !"0x34\00x3\00x3\00\009\001\001", metadata !1, metadata !1, metadata !5, i8* @x3, null} ; [ DW_TAG_variable ] -!16 = metadata !{metadata !"0x34\00x4\00x4\00\0012\001\001", metadata !1, metadata !1, metadata !5, i8* @x4, null} ; [ DW_TAG_variable ] -!17 = metadata !{metadata !"0x34\00x5\00x5\00\0015\000\001", metadata !1, metadata !1, metadata !5, i8* @x5, null} ; [ DW_TAG_variable ] -!18 = metadata !{metadata !"0x101\00a\007\000", metadata !6, metadata !1, metadata !5} ; [ DW_TAG_arg_variable ] -!19 = metadata !{metadata !"0x100\00b\007\000", metadata !20, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!20 = metadata !{metadata !"0xb\007\000\001", metadata !47, metadata !6} ; [ DW_TAG_lexical_block ] -!21 = metadata !{metadata !"0x101\00a\0010\000", metadata !7, metadata !1, metadata !5} ; [ DW_TAG_arg_variable ] -!22 = metadata !{metadata !"0x100\00b\0010\000", metadata !23, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!23 = metadata !{metadata !"0xb\0010\000\002", metadata !47, metadata !7} ; [ DW_TAG_lexical_block ] -!24 = metadata !{metadata !"0x101\00a\0013\000", metadata !8, metadata !1, metadata !5} ; [ DW_TAG_arg_variable ] -!25 = metadata !{metadata !"0x100\00b\0013\000", metadata !26, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!26 = metadata !{metadata !"0xb\0013\000\003", metadata !47, metadata !8} ; [ DW_TAG_lexical_block ] -!27 = metadata !{metadata !"0x101\00a\0016\000", metadata !9, metadata !1, metadata !5} ; [ DW_TAG_arg_variable ] -!28 = metadata !{metadata !"0x100\00b\0016\000", metadata !29, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!29 = metadata !{metadata !"0xb\0016\000\004", metadata !47, metadata !9} ; [ DW_TAG_lexical_block ] -!30 = metadata !{i32 4, i32 0, metadata !0, null} -!31 = metadata !{i32 4, i32 0, metadata !12, null} -!32 = metadata !{i32 7, i32 0, metadata !6, null} -!33 = metadata !{i32 7, i32 0, metadata !20, null} -!34 = metadata !{i32 10, i32 0, metadata !7, null} -!35 = metadata !{i32 10, i32 0, metadata !23, null} -!36 = metadata !{i32 13, i32 0, metadata !8, null} -!37 = metadata !{i32 13, i32 0, metadata !26, null} -!38 = metadata !{i32 16, i32 0, metadata !9, null} -!39 = metadata !{i32 16, i32 0, metadata !29, null} -!40 = metadata !{metadata !0, metadata !6, metadata !7, metadata !8, metadata !9} -!41 = metadata !{metadata !13, metadata !14, metadata !15, metadata !16, metadata !17} -!42 = metadata !{metadata !10, metadata !11} -!43 = metadata !{metadata !18, metadata !19} -!44 = metadata !{metadata !21, metadata !22} -!45 = metadata !{metadata !24, metadata !25} -!46 = metadata !{metadata !27, metadata !28} -!47 = metadata !{metadata !"foo.c", metadata !"/tmp/"} -!48 = metadata !{} -!49 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x2e\00get1\00get1\00get1\004\000\001\000\006\00256\001\004", !47, !1, !3, null, i8 (i8)* @get1, null, null, !42} ; [ DW_TAG_subprogram ] +!1 = !{!"0x29", !47} ; [ DW_TAG_file_type ] +!2 = !{!"0x11\001\004.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)\001\00\000\00\000", !47, !48, !48, !40, !41, !48} ; [ DW_TAG_compile_unit ] +!3 = !{!"0x15\00\000\000\000\000\000\000", !47, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !{!5, !5} +!5 = !{!"0x24\00_Bool\000\008\008\000\000\002", !47, !1} ; [ DW_TAG_base_type ] +!6 = !{!"0x2e\00get2\00get2\00get2\007\000\001\000\006\00256\001\007", !47, !1, !3, null, i8 (i8)* @get2, null, null, !43} ; [ DW_TAG_subprogram ] +!7 = !{!"0x2e\00get3\00get3\00get3\0010\000\001\000\006\00256\001\0010", !47, !1, !3, null, i8 (i8)* @get3, null, null, !44} ; [ DW_TAG_subprogram ] +!8 = !{!"0x2e\00get4\00get4\00get4\0013\000\001\000\006\00256\001\0013", !47, !1, !3, null, i8 (i8)* @get4, null, null, !45} ; [ DW_TAG_subprogram ] +!9 = !{!"0x2e\00get5\00get5\00get5\0016\000\001\000\006\00256\001\0016", !47, !1, !3, null, i8 (i8)* @get5, null, null, !46} ; [ DW_TAG_subprogram ] +!10 = !{!"0x101\00a\004\000", !0, !1, !5} ; [ DW_TAG_arg_variable ] +!11 = !{!"0x100\00b\004\000", !12, !1, !5} ; [ DW_TAG_auto_variable ] +!12 = !{!"0xb\004\000\000", !47, !0} ; [ DW_TAG_lexical_block ] +!13 = !{!"0x34\00x1\00x1\00\003\001\001", !1, !1, !5, i8* @x1, null} ; [ DW_TAG_variable ] +!14 = !{!"0x34\00x2\00x2\00\006\001\001", !1, !1, !5, i8* @x2, null} ; [ DW_TAG_variable ] +!15 = !{!"0x34\00x3\00x3\00\009\001\001", !1, !1, !5, i8* @x3, null} ; [ DW_TAG_variable ] +!16 = !{!"0x34\00x4\00x4\00\0012\001\001", !1, !1, !5, i8* @x4, null} ; [ DW_TAG_variable ] +!17 = !{!"0x34\00x5\00x5\00\0015\000\001", !1, !1, !5, i8* @x5, null} ; [ DW_TAG_variable ] +!18 = !{!"0x101\00a\007\000", !6, !1, !5} ; [ DW_TAG_arg_variable ] +!19 = !{!"0x100\00b\007\000", !20, !1, !5} ; [ DW_TAG_auto_variable ] +!20 = !{!"0xb\007\000\001", !47, !6} ; [ DW_TAG_lexical_block ] +!21 = !{!"0x101\00a\0010\000", !7, !1, !5} ; [ DW_TAG_arg_variable ] +!22 = !{!"0x100\00b\0010\000", !23, !1, !5} ; [ DW_TAG_auto_variable ] +!23 = !{!"0xb\0010\000\002", !47, !7} ; [ DW_TAG_lexical_block ] +!24 = !{!"0x101\00a\0013\000", !8, !1, !5} ; [ DW_TAG_arg_variable ] +!25 = !{!"0x100\00b\0013\000", !26, !1, !5} ; [ DW_TAG_auto_variable ] +!26 = !{!"0xb\0013\000\003", !47, !8} ; [ DW_TAG_lexical_block ] +!27 = !{!"0x101\00a\0016\000", !9, !1, !5} ; [ DW_TAG_arg_variable ] +!28 = !{!"0x100\00b\0016\000", !29, !1, !5} ; [ DW_TAG_auto_variable ] +!29 = !{!"0xb\0016\000\004", !47, !9} ; [ DW_TAG_lexical_block ] +!30 = !MDLocation(line: 4, scope: !0) +!31 = !MDLocation(line: 4, scope: !12) +!32 = !MDLocation(line: 7, scope: !6) +!33 = !MDLocation(line: 7, scope: !20) +!34 = !MDLocation(line: 10, scope: !7) +!35 = !MDLocation(line: 10, scope: !23) +!36 = !MDLocation(line: 13, scope: !8) +!37 = !MDLocation(line: 13, scope: !26) +!38 = !MDLocation(line: 16, scope: !9) +!39 = !MDLocation(line: 16, scope: !29) +!40 = !{!0, !6, !7, !8, !9} +!41 = !{!13, !14, !15, !16, !17} +!42 = !{!10, !11} +!43 = !{!18, !19} +!44 = !{!21, !22} +!45 = !{!24, !25} +!46 = !{!27, !28} +!47 = !{!"foo.c", !"/tmp/"} +!48 = !{} +!49 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll index eb23de0..e9a6793 100644 --- a/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll +++ b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll @@ -12,4 +12,4 @@ entry: ret void } -!0 = metadata !{i32 109} +!0 = !{i32 109} diff --git a/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll b/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll index d3394b5..2af3e3e 100644 --- a/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll +++ b/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll @@ -81,8 +81,8 @@ declare void @_Unwind_SjLj_Resume_or_Rethrow(i8*) declare void @_ZSt9terminatev() -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} -!3 = metadata !{metadata !"bool", metadata !1} -!4 = metadata !{metadata !"int", metadata !1} +!0 = !{!"any pointer", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA", null} +!3 = !{!"bool", !1} +!4 = !{!"int", !1} diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index ede936c..3edc946 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -29,41 +29,41 @@ target triple = "thumbv7-apple-macosx10.7.0" @x5 = global i32 0, align 4 define i32 @get1(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !10, metadata !{metadata !"0x102"}), !dbg !30 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !30 %1 = load i32* @x1, align 4, !dbg !31 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !11, metadata !{metadata !"0x102"}), !dbg !31 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !31 store i32 %a, i32* @x1, align 4, !dbg !31 ret i32 %1, !dbg !31 } define i32 @get2(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !13, metadata !{metadata !"0x102"}), !dbg !32 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !32 %1 = load i32* @x2, align 4, !dbg !33 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !14, metadata !{metadata !"0x102"}), !dbg !33 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !33 store i32 %a, i32* @x2, align 4, !dbg !33 ret i32 %1, !dbg !33 } define i32 @get3(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !16, metadata !{metadata !"0x102"}), !dbg !34 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !34 %1 = load i32* @x3, align 4, !dbg !35 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !17, metadata !{metadata !"0x102"}), !dbg !35 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !35 store i32 %a, i32* @x3, align 4, !dbg !35 ret i32 %1, !dbg !35 } define i32 @get4(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !19, metadata !{metadata !"0x102"}), !dbg !36 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !36 %1 = load i32* @x4, align 4, !dbg !37 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !20, metadata !{metadata !"0x102"}), !dbg !37 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !20, metadata !{!"0x102"}), !dbg !37 store i32 %a, i32* @x4, align 4, !dbg !37 ret i32 %1, !dbg !37 } define i32 @get5(i32 %a) nounwind optsize ssp { - tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !27, metadata !{metadata !"0x102"}), !dbg !38 + tail call void @llvm.dbg.value(metadata i32 %a, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !38 %1 = load i32* @x5, align 4, !dbg !39 - tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !28, metadata !{metadata !"0x102"}), !dbg !39 + tail call void @llvm.dbg.value(metadata i32 %1, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !39 store i32 %a, i32* @x5, align 4, !dbg !39 ret i32 %1, !dbg !39 } @@ -73,50 +73,50 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!49} -!0 = metadata !{metadata !"0x11\0012\00clang\001\00\000\00\001", metadata !47, metadata !48, metadata !48, metadata !40, metadata !41, metadata !48} ; [ DW_TAG_compile_unit ] -!1 = metadata !{metadata !"0x2e\00get1\00get1\00\005\000\001\000\006\00256\001\005", metadata !47, metadata !2, metadata !3, null, i32 (i32)* @get1, null, null, metadata !42} ; [ DW_TAG_subprogram ] [line 5] [def] [get1] -!2 = metadata !{metadata !"0x29", metadata !47} ; [ DW_TAG_file_type ] -!3 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !47, metadata !2, null, metadata !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!4 = metadata !{metadata !5} -!5 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, metadata !0} ; [ DW_TAG_base_type ] -!6 = metadata !{metadata !"0x2e\00get2\00get2\00\008\000\001\000\006\00256\001\008", metadata !47, metadata !2, metadata !3, null, i32 (i32)* @get2, null, null, metadata !43} ; [ DW_TAG_subprogram ] [line 8] [def] [get2] -!7 = metadata !{metadata !"0x2e\00get3\00get3\00\0011\000\001\000\006\00256\001\0011", metadata !47, metadata !2, metadata !3, null, i32 (i32)* @get3, null, null, metadata !44} ; [ DW_TAG_subprogram ] [line 11] [def] [get3] -!8 = metadata !{metadata !"0x2e\00get4\00get4\00\0014\000\001\000\006\00256\001\0014", metadata !47, metadata !2, metadata !3, null, i32 (i32)* @get4, null, null, metadata !45} ; [ DW_TAG_subprogram ] [line 14] [def] [get4] -!9 = metadata !{metadata !"0x2e\00get5\00get5\00\0017\000\001\000\006\00256\001\0017", metadata !47, metadata !2, metadata !3, null, i32 (i32)* @get5, null, null, metadata !46} ; [ DW_TAG_subprogram ] [line 17] [def] [get5] -!10 = metadata !{metadata !"0x101\00a\0016777221\000", metadata !1, metadata !2, metadata !5} ; [ DW_TAG_arg_variable ] -!11 = metadata !{metadata !"0x100\00b\005\000", metadata !12, metadata !2, metadata !5} ; [ DW_TAG_auto_variable ] -!12 = metadata !{metadata !"0xb\005\0019\000", metadata !47, metadata !1} ; [ DW_TAG_lexical_block ] -!13 = metadata !{metadata !"0x101\00a\0016777224\000", metadata !6, metadata !2, metadata !5} ; [ DW_TAG_arg_variable ] -!14 = metadata !{metadata !"0x100\00b\008\000", metadata !15, metadata !2, metadata !5} ; [ DW_TAG_auto_variable ] -!15 = metadata !{metadata !"0xb\008\0017\001", metadata !47, metadata !6} ; [ DW_TAG_lexical_block ] -!16 = metadata !{metadata !"0x101\00a\0016777227\000", metadata !7, metadata !2, metadata !5} ; [ DW_TAG_arg_variable ] -!17 = metadata !{metadata !"0x100\00b\0011\000", metadata !18, metadata !2, metadata !5} ; [ DW_TAG_auto_variable ] -!18 = metadata !{metadata !"0xb\0011\0019\002", metadata !47, metadata !7} ; [ DW_TAG_lexical_block ] -!19 = metadata !{metadata !"0x101\00a\0016777230\000", metadata !8, metadata !2, metadata !5} ; [ DW_TAG_arg_variable ] -!20 = metadata !{metadata !"0x100\00b\0014\000", metadata !21, metadata !2, metadata !5} ; [ DW_TAG_auto_variable ] -!21 = metadata !{metadata !"0xb\0014\0019\003", metadata !47, metadata !8} ; [ DW_TAG_lexical_block ] -!25 = metadata !{metadata !"0x34\00x1\00x1\00\004\001\001", metadata !0, metadata !2, metadata !5, i32* @x1, null} ; [ DW_TAG_variable ] -!26 = metadata !{metadata !"0x34\00x2\00x2\00\007\001\001", metadata !0, metadata !2, metadata !5, i32* @x2, null} ; [ DW_TAG_variable ] -!27 = metadata !{metadata !"0x101\00a\0016777233\000", metadata !9, metadata !2, metadata !5} ; [ DW_TAG_arg_variable ] -!28 = metadata !{metadata !"0x100\00b\0017\000", metadata !29, metadata !2, metadata !5} ; [ DW_TAG_auto_variable ] -!29 = metadata !{metadata !"0xb\0017\0019\004", metadata !47, metadata !9} ; [ DW_TAG_lexical_block ] -!30 = metadata !{i32 5, i32 16, metadata !1, null} -!31 = metadata !{i32 5, i32 32, metadata !12, null} -!32 = metadata !{i32 8, i32 14, metadata !6, null} -!33 = metadata !{i32 8, i32 29, metadata !15, null} -!34 = metadata !{i32 11, i32 16, metadata !7, null} -!35 = metadata !{i32 11, i32 32, metadata !18, null} -!36 = metadata !{i32 14, i32 16, metadata !8, null} -!37 = metadata !{i32 14, i32 32, metadata !21, null} -!38 = metadata !{i32 17, i32 16, metadata !9, null} -!39 = metadata !{i32 17, i32 32, metadata !29, null} -!40 = metadata !{metadata !1, metadata !6, metadata !7, metadata !8, metadata !9} -!41 = metadata !{metadata !25, metadata !26} -!42 = metadata !{metadata !10, metadata !11} -!43 = metadata !{metadata !13, metadata !14} -!44 = metadata !{metadata !16, metadata !17} -!45 = metadata !{metadata !19, metadata !20} -!46 = metadata !{metadata !27, metadata !28} -!47 = metadata !{metadata !"ss3.c", metadata !"/private/tmp"} -!48 = metadata !{} -!49 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x11\0012\00clang\001\00\000\00\001", !47, !48, !48, !40, !41, !48} ; [ DW_TAG_compile_unit ] +!1 = !{!"0x2e\00get1\00get1\00\005\000\001\000\006\00256\001\005", !47, !2, !3, null, i32 (i32)* @get1, null, null, !42} ; [ DW_TAG_subprogram ] [line 5] [def] [get1] +!2 = !{!"0x29", !47} ; [ DW_TAG_file_type ] +!3 = !{!"0x15\00\000\000\000\000\000\000", !47, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !{!5} +!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ] +!6 = !{!"0x2e\00get2\00get2\00\008\000\001\000\006\00256\001\008", !47, !2, !3, null, i32 (i32)* @get2, null, null, !43} ; [ DW_TAG_subprogram ] [line 8] [def] [get2] +!7 = !{!"0x2e\00get3\00get3\00\0011\000\001\000\006\00256\001\0011", !47, !2, !3, null, i32 (i32)* @get3, null, null, !44} ; [ DW_TAG_subprogram ] [line 11] [def] [get3] +!8 = !{!"0x2e\00get4\00get4\00\0014\000\001\000\006\00256\001\0014", !47, !2, !3, null, i32 (i32)* @get4, null, null, !45} ; [ DW_TAG_subprogram ] [line 14] [def] [get4] +!9 = !{!"0x2e\00get5\00get5\00\0017\000\001\000\006\00256\001\0017", !47, !2, !3, null, i32 (i32)* @get5, null, null, !46} ; [ DW_TAG_subprogram ] [line 17] [def] [get5] +!10 = !{!"0x101\00a\0016777221\000", !1, !2, !5} ; [ DW_TAG_arg_variable ] +!11 = !{!"0x100\00b\005\000", !12, !2, !5} ; [ DW_TAG_auto_variable ] +!12 = !{!"0xb\005\0019\000", !47, !1} ; [ DW_TAG_lexical_block ] +!13 = !{!"0x101\00a\0016777224\000", !6, !2, !5} ; [ DW_TAG_arg_variable ] +!14 = !{!"0x100\00b\008\000", !15, !2, !5} ; [ DW_TAG_auto_variable ] +!15 = !{!"0xb\008\0017\001", !47, !6} ; [ DW_TAG_lexical_block ] +!16 = !{!"0x101\00a\0016777227\000", !7, !2, !5} ; [ DW_TAG_arg_variable ] +!17 = !{!"0x100\00b\0011\000", !18, !2, !5} ; [ DW_TAG_auto_variable ] +!18 = !{!"0xb\0011\0019\002", !47, !7} ; [ DW_TAG_lexical_block ] +!19 = !{!"0x101\00a\0016777230\000", !8, !2, !5} ; [ DW_TAG_arg_variable ] +!20 = !{!"0x100\00b\0014\000", !21, !2, !5} ; [ DW_TAG_auto_variable ] +!21 = !{!"0xb\0014\0019\003", !47, !8} ; [ DW_TAG_lexical_block ] +!25 = !{!"0x34\00x1\00x1\00\004\001\001", !0, !2, !5, i32* @x1, null} ; [ DW_TAG_variable ] +!26 = !{!"0x34\00x2\00x2\00\007\001\001", !0, !2, !5, i32* @x2, null} ; [ DW_TAG_variable ] +!27 = !{!"0x101\00a\0016777233\000", !9, !2, !5} ; [ DW_TAG_arg_variable ] +!28 = !{!"0x100\00b\0017\000", !29, !2, !5} ; [ DW_TAG_auto_variable ] +!29 = !{!"0xb\0017\0019\004", !47, !9} ; [ DW_TAG_lexical_block ] +!30 = !MDLocation(line: 5, column: 16, scope: !1) +!31 = !MDLocation(line: 5, column: 32, scope: !12) +!32 = !MDLocation(line: 8, column: 14, scope: !6) +!33 = !MDLocation(line: 8, column: 29, scope: !15) +!34 = !MDLocation(line: 11, column: 16, scope: !7) +!35 = !MDLocation(line: 11, column: 32, scope: !18) +!36 = !MDLocation(line: 14, column: 16, scope: !8) +!37 = !MDLocation(line: 14, column: 32, scope: !21) +!38 = !MDLocation(line: 17, column: 16, scope: !9) +!39 = !MDLocation(line: 17, column: 32, scope: !29) +!40 = !{!1, !6, !7, !8, !9} +!41 = !{!25, !26} +!42 = !{!10, !11} +!43 = !{!13, !14} +!44 = !{!16, !17} +!45 = !{!19, !20} +!46 = !{!27, !28} +!47 = !{!"ss3.c", !"/private/tmp"} +!48 = !{} +!49 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll b/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll index b3a7e34..69d72bd 100644 --- a/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll +++ b/test/CodeGen/ARM/2012-04-24-SplitEHCriticalEdge.ll @@ -65,7 +65,7 @@ declare i32 @__gxx_personality_sj0(...) !llvm.module.flags = !{!0, !1, !2, !3} -!0 = metadata !{i32 1, metadata !"Objective-C Version", i32 2} -!1 = metadata !{i32 1, metadata !"Objective-C Image Info Version", i32 0} -!2 = metadata !{i32 1, metadata !"Objective-C Image Info Section", metadata !"__DATA, __objc_imageinfo, regular, no_dead_strip"} -!3 = metadata !{i32 4, metadata !"Objective-C Garbage Collection", i32 0} +!0 = !{i32 1, !"Objective-C Version", i32 2} +!1 = !{i32 1, !"Objective-C Image Info Version", i32 0} +!2 = !{i32 1, !"Objective-C Image Info Section", !"__DATA, __objc_imageinfo, regular, no_dead_strip"} +!3 = !{i32 4, !"Objective-C Garbage Collection", i32 0} diff --git a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll index adb5c7e..70e3079 100644 --- a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll +++ b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll @@ -169,4 +169,4 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable declare arm_aapcs_vfpcc void @bar(%0*, float) -!0 = metadata !{metadata !"branch_weights", i32 64, i32 4} +!0 = !{!"branch_weights", i32 64, i32 4} diff --git a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll index 5235e9c..53860ea 100644 --- a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll +++ b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv.ll @@ -8,4 +8,4 @@ define void @f() nounwind ssp { ret void } -!0 = metadata !{i32 318437} +!0 = !{i32 318437} diff --git a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll index d389b5c..b47247c 100644 --- a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll +++ b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll @@ -8,4 +8,4 @@ define hidden void @f(i32* %corr, i32 %order) nounwind ssp { ret void } -!0 = metadata !{i32 257} +!0 = !{i32 257} diff --git a/test/CodeGen/ARM/2014-08-04-muls-it.ll b/test/CodeGen/ARM/2014-08-04-muls-it.ll index 4636bff..5ba1347 100644 --- a/test/CodeGen/ARM/2014-08-04-muls-it.ll +++ b/test/CodeGen/ARM/2014-08-04-muls-it.ll @@ -17,9 +17,7 @@ if.end: ; preds = %if.then, %entry ; CHECK-LABEL: function ; CHECK: cmp r0, r1 -; CHECK: bne [[LABEL:[.*]]] ; CHECK-NOT: mulseq r0, r0, r0 -; CHECK: [[LABEL]] -; CHECK: muls r0, r0, r0 +; CHECK: muleq r0, r0, r0 ; CHECK: bx lr diff --git a/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll b/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll new file mode 100644 index 0000000..de2dead --- /dev/null +++ b/test/CodeGen/ARM/2015-01-21-thumbv4t-ldstr-opt.ll @@ -0,0 +1,48 @@ +; RUN: llc -mtriple=thumbv4t-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V4T +; RUN: llc -mtriple=thumbv6m-none--eabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V6M + +; CHECK-LABEL: test1 +define i32 @test1(i32* %p) { + +; Offsets less than 8 can be generated in a single add +; CHECK: adds [[NEWBASE:r[0-9]]], r0, #4 + %1 = getelementptr inbounds i32* %p, i32 1 + %2 = getelementptr inbounds i32* %p, i32 2 + %3 = getelementptr inbounds i32* %p, i32 3 + %4 = getelementptr inbounds i32* %p, i32 4 + +; CHECK-NEXT: ldm [[NEWBASE]], + %5 = load i32* %1, align 4 + %6 = load i32* %2, align 4 + %7 = load i32* %3, align 4 + %8 = load i32* %4, align 4 + + %9 = add nsw i32 %5, %6 + %10 = add nsw i32 %9, %7 + %11 = add nsw i32 %10, %8 + ret i32 %11 +} + +; CHECK-LABEL: test2 +define i32 @test2(i32* %p) { + +; Offsets >=8 require a mov and an add +; CHECK-V4T: movs [[NEWBASE:r[0-9]]], r0 +; CHECK-V6M: mov [[NEWBASE:r[0-9]]], r0 +; CHECK-NEXT: adds [[NEWBASE]], #8 + %1 = getelementptr inbounds i32* %p, i32 2 + %2 = getelementptr inbounds i32* %p, i32 3 + %3 = getelementptr inbounds i32* %p, i32 4 + %4 = getelementptr inbounds i32* %p, i32 5 + +; CHECK-NEXT: ldm [[NEWBASE]], + %5 = load i32* %1, align 4 + %6 = load i32* %2, align 4 + %7 = load i32* %3, align 4 + %8 = load i32* %4, align 4 + + %9 = add nsw i32 %5, %6 + %10 = add nsw i32 %9, %7 + %11 = add nsw i32 %10, %8 + ret i32 %11 +} diff --git a/test/CodeGen/ARM/Windows/read-only-data.ll b/test/CodeGen/ARM/Windows/read-only-data.ll index 0ccb5ed..0438d68 100644 --- a/test/CodeGen/ARM/Windows/read-only-data.ll +++ b/test/CodeGen/ARM/Windows/read-only-data.ll @@ -10,6 +10,6 @@ entry: ret void } -; CHECK: .section .rdata,"rd" +; CHECK: .section .rdata,"dr" ; CHECK-NOT: .section ".rodata.str1.1" diff --git a/test/CodeGen/ARM/Windows/stack-probe-non-default.ll b/test/CodeGen/ARM/Windows/stack-probe-non-default.ll new file mode 100644 index 0000000..796bcdd --- /dev/null +++ b/test/CodeGen/ARM/Windows/stack-probe-non-default.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple thumbv7-windows -mcpu cortex-a9 -o - %s \ +; RUN: | FileCheck %s -check-prefix CHECK-DEFAULT-CODE-MODEL + +; RUN: llc -mtriple thumbv7-windows -mcpu cortex-a9 -code-model large -o - %s \ +; RUN: | FileCheck %s -check-prefix CHECK-LARGE-CODE-MODEL + +declare dllimport arm_aapcs_vfpcc void @initialise(i8*) + +define dllexport arm_aapcs_vfpcc signext i8 @function(i32 %offset) #0 { +entry: + %buffer = alloca [4096 x i8], align 1 + %0 = getelementptr inbounds [4096 x i8]* %buffer, i32 0, i32 0 + call arm_aapcs_vfpcc void @initialise(i8* %0) + %arrayidx = getelementptr inbounds [4096 x i8]* %buffer, i32 0, i32 %offset + %1 = load i8* %arrayidx, align 1 + ret i8 %1 +} + +attributes #0 = { "stack-probe-size"="8096" } + +; CHECK-DEFAULT-CODE-MODEL-NOT: __chkstk +; CHECK-DEFAULT-CODE-MODEL: sub.w sp, sp, #4096 + +; CHECK-LARGE-CODE-MODEL-NOT: movw r12, :lower16:__chkstk +; CHECK-LARGE-CODE-MODEL-NOT: movt r12, :upper16:__chkstk +; CHECK-LARGE-CODE-MODEL: sub.w sp, sp, #4096 + diff --git a/test/CodeGen/ARM/Windows/structors.ll b/test/CodeGen/ARM/Windows/structors.ll index a1a9026..874b5bf 100644 --- a/test/CodeGen/ARM/Windows/structors.ll +++ b/test/CodeGen/ARM/Windows/structors.ll @@ -7,6 +7,6 @@ entry: ret void } -; CHECK: .section .CRT$XCU,"rd" +; CHECK: .section .CRT$XCU,"dr" ; CHECK: .long function diff --git a/test/CodeGen/ARM/aggregate-padding.ll b/test/CodeGen/ARM/aggregate-padding.ll new file mode 100644 index 0000000..bc46a9c --- /dev/null +++ b/test/CodeGen/ARM/aggregate-padding.ll @@ -0,0 +1,101 @@ +; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s + +; [2 x i64] should be contiguous when split (e.g. we shouldn't try to align all +; i32 components to 64 bits). Also makes sure i64 based types are properly +; aligned on the stack. +define i64 @test_i64_contiguous_on_stack([8 x double], float, i32 %in, [2 x i64] %arg) nounwind { +; CHECK-LABEL: test_i64_contiguous_on_stack: +; CHECK-DAG: ldr [[LO0:r[0-9]+]], [sp, #8] +; CHECK-DAG: ldr [[HI0:r[0-9]+]], [sp, #12] +; CHECK-DAG: ldr [[LO1:r[0-9]+]], [sp, #16] +; CHECK-DAG: ldr [[HI1:r[0-9]+]], [sp, #20] +; CHECK: adds r0, [[LO0]], [[LO1]] +; CHECK: adc r1, [[HI0]], [[HI1]] + + %val1 = extractvalue [2 x i64] %arg, 0 + %val2 = extractvalue [2 x i64] %arg, 1 + %sum = add i64 %val1, %val2 + ret i64 %sum +} + +; [2 x i64] should try to use looks for 4 regs, not 8 (which might happen if the +; i64 -> i32, i32 split wasn't handled correctly). +define i64 @test_2xi64_uses_4_regs([8 x double], float, [2 x i64] %arg) nounwind { +; CHECK-LABEL: test_2xi64_uses_4_regs: +; CHECK-DAG: mov r0, r2 +; CHECK-DAG: mov r1, r3 + + %val = extractvalue [2 x i64] %arg, 1 + ret i64 %val +} + +; An aggregate should be able to split between registers and stack if there is +; nothing else on the stack. +define i32 @test_aggregates_split([8 x double], i32, [4 x i32] %arg) nounwind { +; CHECK-LABEL: test_aggregates_split: +; CHECK: ldr [[VAL3:r[0-9]+]], [sp] +; CHECK: add r0, r1, [[VAL3]] + + %val0 = extractvalue [4 x i32] %arg, 0 + %val3 = extractvalue [4 x i32] %arg, 3 + %sum = add i32 %val0, %val3 + ret i32 %sum +} + +; If an aggregate has to be moved entirely onto the stack, nothing should be +; able to use r0-r3 any more. Also checks that [2 x i64] properly aligned when +; it uses regs. +define i32 @test_no_int_backfilling([8 x double], float, i32, [2 x i64], i32 %arg) nounwind { +; CHECK-LABEL: test_no_int_backfilling: +; CHECK: ldr r0, [sp, #24] + ret i32 %arg +} + +; Even if the argument was successfully allocated as reg block, there should be +; no backfillig to r1. +define i32 @test_no_int_backfilling_regsonly(i32, [1 x i64], i32 %arg) { +; CHECK-LABEL: test_no_int_backfilling_regsonly: +; CHECK: ldr r0, [sp] + ret i32 %arg +} + +; If an aggregate has to be moved entirely onto the stack, nothing should be +; able to use r0-r3 any more. +define float @test_no_float_backfilling([7 x double], [4 x i32], i32, [4 x double], float %arg) nounwind { +; CHECK-LABEL: test_no_float_backfilling: +; CHECK: vldr s0, [sp, #40] + ret float %arg +} + +; They're a bit pointless, but types like [N x i8] should work as well. +define i8 @test_i8_in_regs(i32, [3 x i8] %arg) { +; CHECK-LABEL: test_i8_in_regs: +; CHECK: add r0, r1, r3 + %val0 = extractvalue [3 x i8] %arg, 0 + %val2 = extractvalue [3 x i8] %arg, 2 + %sum = add i8 %val0, %val2 + ret i8 %sum +} + +define i16 @test_i16_split(i32, i32, [3 x i16] %arg) { +; CHECK-LABEL: test_i16_split: +; CHECK: ldrh [[VAL2:r[0-9]+]], [sp] +; CHECK: add r0, r2, [[VAL2]] + %val0 = extractvalue [3 x i16] %arg, 0 + %val2 = extractvalue [3 x i16] %arg, 2 + %sum = add i16 %val0, %val2 + ret i16 %sum +} + +; Beware: on the stack each i16 still gets a 32-bit slot, the array is not +; packed. +define i16 @test_i16_forced_stack([8 x double], double, i32, i32, [3 x i16] %arg) { +; CHECK-LABEL: test_i16_forced_stack: +; CHECK-DAG: ldrh [[VAL0:r[0-9]+]], [sp, #8] +; CHECK-DAG: ldrh [[VAL2:r[0-9]+]], [sp, #16] +; CHECK: add r0, [[VAL0]], [[VAL2]] + %val0 = extractvalue [3 x i16] %arg, 0 + %val2 = extractvalue [3 x i16] %arg, 2 + %sum = add i16 %val0, %val2 + ret i16 %sum +} diff --git a/test/CodeGen/ARM/alloc-no-stack-realign.ll b/test/CodeGen/ARM/alloc-no-stack-realign.ll index 6e6311d..5ad8719 100644 --- a/test/CodeGen/ARM/alloc-no-stack-realign.ll +++ b/test/CodeGen/ARM/alloc-no-stack-realign.ll @@ -8,21 +8,28 @@ define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" { entry: -; NO-REALIGN: test1 -; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 -; NO-REALIGN: vst1.64 -; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 -; NO-REALIGN: vst1.64 -; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 -; NO-REALIGN: vst1.64 -; NO-REALIGN: vst1.64 -; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 -; NO-REALIGN: vst1.64 -; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 -; NO-REALIGN: vst1.64 -; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 -; NO-REALIGN: vst1.64 -; NO-REALIGN: vst1.64 +; NO-REALIGN-LABEL: test1 +; NO-REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]] +; NO-REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]! +; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32 +; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48 +; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] + +; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48 +; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32 +; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]! +; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128] + +; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48 +; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32 +; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; NO-REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]! +; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128] %retval = alloca <16 x float>, align 16 %0 = load <16 x float>* @T3_retval, align 16 store <16 x float> %0, <16 x float>* %retval @@ -33,22 +40,31 @@ entry: define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp { entry: -; REALIGN: test2 -; REALIGN: bic sp, sp, #63 -; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 -; REALIGN: vst1.64 -; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 -; REALIGN: vst1.64 -; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 -; REALIGN: vst1.64 -; REALIGN: vst1.64 -; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 -; REALIGN: vst1.64 -; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 -; REALIGN: vst1.64 -; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 -; REALIGN: vst1.64 -; REALIGN: vst1.64 +; REALIGN-LABEL: test2 +; REALIGN: bfc sp, #0, #6 +; REALIGN: mov r[[R2:[0-9]+]], r[[R1:[0-9]+]] +; REALIGN: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]! +; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32 +; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48 +; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] + + +; REALIGN: orr r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48 +; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #32 +; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #16 +; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128] +; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128] + +; REALIGN: add r[[R1:[0-9]+]], r[[R0:0]], #48 +; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128] +; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32 +; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128] +; REALIGN: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]! +; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128] %retval = alloca <16 x float>, align 16 %0 = load <16 x float>* @T3_retval, align 16 store <16 x float> %0, <16 x float>* %retval diff --git a/test/CodeGen/ARM/arm-abi-attr.ll b/test/CodeGen/ARM/arm-abi-attr.ll index f3923ae..61cb6ce 100644 --- a/test/CodeGen/ARM/arm-abi-attr.ll +++ b/test/CodeGen/ARM/arm-abi-attr.ll @@ -1,13 +1,13 @@ -; RUN: llc -mtriple=arm-linux < %s | FileCheck %s --check-prefix=APCS -; RUN: llc -mtriple=arm-linux -mattr=apcs < %s | \ +; RUN: llc -mtriple=arm-linux-gnu < %s | FileCheck %s --check-prefix=APCS +; RUN: llc -mtriple=arm-linux-gnu -target-abi=apcs < %s | \ ; RUN: FileCheck %s --check-prefix=APCS -; RUN: llc -mtriple=arm-linux-gnueabi -mattr=apcs < %s | \ +; RUN: llc -mtriple=arm-linux-gnueabi -target-abi=apcs < %s | \ ; RUN: FileCheck %s --check-prefix=APCS ; RUN: llc -mtriple=arm-linux-gnueabi < %s | FileCheck %s --check-prefix=AAPCS -; RUN: llc -mtriple=arm-linux-gnueabi -mattr=aapcs < %s | \ +; RUN: llc -mtriple=arm-linux-gnueabi -target-abi=aapcs < %s | \ ; RUN: FileCheck %s --check-prefix=AAPCS -; RUN: llc -mtriple=arm-linux-gnu -mattr=aapcs < %s | \ +; RUN: llc -mtriple=arm-linux-gnu -target-abi=aapcs < %s | \ ; RUN: FileCheck %s --check-prefix=AAPCS ; The stack is 8 byte aligned on AAPCS and 4 on APCS, so we should get a BIC diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index 462c185..0c0769f 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE ; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-LE -; RUN: llc < %s -mtriple=armebv7 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE +; RUN: llc < %s -mtriple=armebv7 -target-abi apcs | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE ; RUN: llc < %s -mtriple=thumbebv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-BE define i64 @test1(i64* %ptr, i64 %val) { diff --git a/test/CodeGen/ARM/atomic-ops-v8.ll b/test/CodeGen/ARM/atomic-ops-v8.ll index 7072aaa..6ba1352 100644 --- a/test/CodeGen/ARM/atomic-ops-v8.ll +++ b/test/CodeGen/ARM/atomic-ops-v8.ll @@ -1296,7 +1296,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) %addr = inttoptr i64 %addr_int to i8* store atomic i8 %val, i8* %addr monotonic, align 1 -; CHECK-LE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp] +; CHECK-LE: ldr{{b?(\.w)?}} [[VAL:r[0-9]+]], [sp] ; CHECK-LE: strb [[VAL]], [r0, r2] ; CHECK-BE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp, #3] ; CHECK-BE: strb [[VAL]], [r1, r3] diff --git a/test/CodeGen/ARM/big-endian-neon-extend.ll b/test/CodeGen/ARM/big-endian-neon-extend.ll index 931c6c3..1498356 100644 --- a/test/CodeGen/ARM/big-endian-neon-extend.ll +++ b/test/CodeGen/ARM/big-endian-neon-extend.ll @@ -2,10 +2,18 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i8_to_2i64: -; CHECK: vld1.16 {[[REG:d[0-9]+]] -; CHECK: vmov.i64 {{q[0-9]+}}, #0xff -; CHECK: vrev16.8 [[REG]], [[REG]] -; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] +; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16] +; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xff +; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]] +; CHECK-NEXT: vrev16.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] +; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]] +; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] +; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]] +; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] +; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] +; CHECK-NEXT: bx lr %1 = load <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i64> store <2 x i64> %2, <2 x i64>* %storeaddr @@ -14,10 +22,17 @@ define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i16_to_2i64: -; CHECK: vld1.32 {[[REG:d[0-9]+]] -; CHECK: vmov.i64 {{q[0-9]+}}, #0xffff -; CHECK: vrev32.16 [[REG]], [[REG]] -; CHECK: vmovl.u16 {{q[0-9]+}}, [[REG]] +; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32] +; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xffff +; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]] +; CHECK-NEXT: vrev32.16 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]] +; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] +; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]] +; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] +; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] +; CHECK-NEXT: bx lr %1 = load <2 x i16>* %loadaddr %2 = zext <2 x i16> %1 to <2 x i64> store <2 x i64> %2, <2 x i64>* %storeaddr @@ -27,8 +42,13 @@ define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeadd define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i8_to_2i32: -; CHECK: vld1.16 {[[REG:d[0-9]+]] -; CHECK: vrev16.8 [[REG]], [[REG]] +; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16] +; CHECK-NEXT: vrev16.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] +; CHECK-NEXT: vrev64.32 [[REG]], [[REG]] +; CHECK-NEXT: vstr [[REG]], [r1] +; CHECK-NEXT: bx lr %1 = load <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i32> store <2 x i32> %2, <2 x i32>* %storeaddr @@ -37,9 +57,12 @@ define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i16_to_2i32: -; CHECK: vld1.32 {[[REG:d[0-9]+]] -; CHECK: vrev32.16 [[REG]], [[REG]] -; CHECK: vmovl.u16 {{q[0-9]+}}, [[REG]] +; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32] +; CHECK-NEXT: vrev32.16 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vrev64.32 [[REG]], [[REG]] +; CHECK-NEXT: vstr [[REG]], [r1] +; CHECK-NEXT: bx lr %1 = load <2 x i16>* %loadaddr %2 = zext <2 x i16> %1 to <2 x i32> store <2 x i32> %2, <2 x i32>* %storeaddr @@ -48,9 +71,15 @@ define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeadd define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) { ; CHECK-LABEL: vector_ext_2i8_to_2i16: -; CHECK: vld1.16 {[[REG:d[0-9]+]] -; CHECK: vrev16.8 [[REG]], [[REG]] -; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] +; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16] +; CHECK-NEXT: vrev16.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] +; CHECK-NEXT: vrev32.16 [[REG]], [[REG]] +; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}} +; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}} +; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32] +; CHECK-NEXT: bx lr %1 = load <2 x i8>* %loadaddr %2 = zext <2 x i8> %1 to <2 x i16> store <2 x i16> %2, <2 x i16>* %storeaddr @@ -59,9 +88,13 @@ define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ) { ; CHECK-LABEL: vector_ext_4i8_to_4i32: -; CHECK: vld1.32 {[[REG:d[0-9]+]] -; CHECK: vrev32.8 [[REG]], [[REG]] -; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] +; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32] +; CHECK-NEXT: vrev32.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]] +; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]] +; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1] +; CHECK-NEXT: bx lr %1 = load <4 x i8>* %loadaddr %2 = zext <4 x i8> %1 to <4 x i32> store <4 x i32> %2, <4 x i32>* %storeaddr @@ -70,12 +103,14 @@ define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ) { ; CHECK-LABEL: vector_ext_4i8_to_4i16: -; CHECK: vld1.32 {[[REG:d[0-9]+]] -; CHECK: vrev32.8 [[REG]], [[REG]] -; CHECK: vmovl.u8 {{q[0-9]+}}, [[REG]] +; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32] +; CHECK-NEXT: vrev32.8 [[REG]], [[REG]] +; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]] +; CHECK-NEXT: vrev64.16 [[REG]], [[REG]] +; CHECK-NEXT: vstr [[REG]], [r1] +; CHECK-NEXT: bx lr %1 = load <4 x i8>* %loadaddr %2 = zext <4 x i8> %1 to <4 x i16> store <4 x i16> %2, <4 x i16>* %storeaddr ret void } - diff --git a/test/CodeGen/ARM/build-attributes-encoding.s b/test/CodeGen/ARM/build-attributes-encoding.s index 34a1ad3..29f13f0 100644 --- a/test/CodeGen/ARM/build-attributes-encoding.s +++ b/test/CodeGen/ARM/build-attributes-encoding.s @@ -78,7 +78,7 @@ // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: SectionData ( // CHECK-NEXT: 0000: 41460000 00616561 62690001 3C000000 -// CHECK-NEXT: 0010: 05434F52 5445582D 41380006 0A074108 +// CHECK-NEXT: 0010: 05636F72 7465782D 61380006 0A074108 // CHECK-NEXT: 0020: 0109020A 030C0214 01150117 01180119 // CHECK-NEXT: 0030: 011B001C 0124012A 012C0244 036EA001 // CHECK-NEXT: 0040: 81013100 FA0101 diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll index 99c2445..37c6a447 100644 --- a/test/CodeGen/ARM/build-attributes.ll +++ b/test/CodeGen/ARM/build-attributes.ll @@ -3,39 +3,106 @@ ; RUN: llc < %s -mtriple=thumbv5-linux-gnueabi -mcpu=xscale | FileCheck %s --check-prefix=XSCALE ; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s --check-prefix=V6 +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6-FAST +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi | FileCheck %s --check-prefix=V6M +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST +; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi | FileCheck %s --check-prefix=V6M +; RUN: llc < %s -mtriple=thumbv6sm-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s | FileCheck %s --check-prefix=ARM1156T2F-S +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=ARM1156T2F-S-FAST +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefix=V7M +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7M-FAST +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7 +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V8-FAST +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8 +; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-neon,-crypto | FileCheck %s --check-prefix=V8-FPARMv8 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,-crypto | FileCheck %s --check-prefix=V8-NEON ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT-FAST +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-neon,+d16 | FileCheck %s --check-prefix=CORTEX-A5-NONEON ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A5-NOFPU +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-NOFPU-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A9-SOFT-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A9-HARD +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A9-HARD-FAST +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 | FileCheck %s --check-prefix=CORTEX-A12-DEFAULT +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A12-DEFAULT-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A12-NOFPU +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A12-NOFPU-FAST +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15 +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A15-FAST +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 | FileCheck %s --check-prefix=CORTEX-A17-DEFAULT +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A17-NOFPU +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-NOFPU-FAST +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus | FileCheck %s --check-prefix=CORTEX-M0PLUS +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0PLUS-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0plus -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 | FileCheck %s --check-prefix=CORTEX-M1 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M1-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m1 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 | FileCheck %s --check-prefix=SC000 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC000-FAST +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=sc000 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3 +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M3-FAST +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 | FileCheck %s --check-prefix=SC300 +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=SC300-FAST +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=sc300 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-SOFT-FAST ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-HARD-FAST +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SOFT +; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-NOFPU-FAST ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SINGLE -; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-DOUBLE +; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-FAST +; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7-DOUBLE +; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5 +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R5-FAST +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 | FileCheck %s --check-prefix=CORTEX-R7 +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R7-FAST +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A53-FAST +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=CORTEX-A72 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A72-FAST +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=CORTEX-A7-CHECK +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-CHECK-FAST ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-NOFPU +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-NOFPU-FAST ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4 +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-FPUV4-FAST ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,,+d16,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=pic | FileCheck %s --check-prefix=RELOC-PIC ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=static | FileCheck %s --check-prefix=RELOC-OTHER @@ -49,6 +116,9 @@ ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; ARMv7a ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN @@ -82,75 +152,185 @@ ; XSCALE: .eabi_attribute 8, 1 ; XSCALE: .eabi_attribute 9, 1 +; DYN-ROUNDING: .eabi_attribute 19, 1 + ; V6: .eabi_attribute 6, 6 ; V6: .eabi_attribute 8, 1 +;; We assume round-to-nearest by default (matches GCC) +; V6-NOT: .eabi_attribute 19 +;; The default choice made by llc is for a V6 CPU without an FPU. +;; This is not an interesting detail, but for such CPUs, the default intention is to use +;; software floating-point support. The choice is not important for targets without +;; FPU support! +; V6: .eabi_attribute 20, 1 +; V6: .eabi_attribute 21, 1 +; V6-NOT: .eabi_attribute 22 +; V6: .eabi_attribute 23, 3 ; V6: .eabi_attribute 24, 1 ; V6: .eabi_attribute 25, 1 ; V6-NOT: .eabi_attribute 27 ; V6-NOT: .eabi_attribute 28 ; V6-NOT: .eabi_attribute 36 +; V6: .eabi_attribute 38, 1 ; V6-NOT: .eabi_attribute 42 +; V6-NOT: .eabi_attribute 44 ; V6-NOT: .eabi_attribute 68 +; V6-FAST-NOT: .eabi_attribute 19 +;; Despite the V6 CPU having no FPU by default, we chose to flush to +;; positive zero here. There's no hardware support doing this, but the +;; fast maths software library might. +; V6-FAST-NOT: .eabi_attribute 20 +; V6-FAST-NOT: .eabi_attribute 21 +; V6-FAST-NOT: .eabi_attribute 22 +; V6-FAST: .eabi_attribute 23, 1 + +;; We emit 6, 12 for both v6-M and v6S-M, technically this is incorrect for +;; V6-M, however we don't model the OS extension so this is fine. ; V6M: .eabi_attribute 6, 12 ; V6M-NOT: .eabi_attribute 7 ; V6M: .eabi_attribute 8, 0 ; V6M: .eabi_attribute 9, 1 +; V6M-NOT: .eabi_attribute 19 +;; The default choice made by llc is for a V6M CPU without an FPU. +;; This is not an interesting detail, but for such CPUs, the default intention is to use +;; software floating-point support. The choice is not important for targets without +;; FPU support! +; V6M: .eabi_attribute 20, 1 +; V6M: .eabi_attribute 21, 1 +; V6M-NOT: .eabi_attribute 22 +; V6M: .eabi_attribute 23, 3 ; V6M: .eabi_attribute 24, 1 ; V6M: .eabi_attribute 25, 1 ; V6M-NOT: .eabi_attribute 27 ; V6M-NOT: .eabi_attribute 28 ; V6M-NOT: .eabi_attribute 36 +; V6M: .eabi_attribute 38, 1 ; V6M-NOT: .eabi_attribute 42 +; V6M-NOT: .eabi_attribute 44 ; V6M-NOT: .eabi_attribute 68 +; V6M-FAST-NOT: .eabi_attribute 19 +;; Despite the V6M CPU having no FPU by default, we chose to flush to +;; positive zero here. There's no hardware support doing this, but the +;; fast maths software library might. +; V6M-FAST-NOT: .eabi_attribute 20 +; V6M-FAST-NOT: .eabi_attribute 21 +; V6M-FAST-NOT: .eabi_attribute 22 +; V6M-FAST: .eabi_attribute 23, 1 + ; ARM1156T2F-S: .cpu arm1156t2f-s ; ARM1156T2F-S: .eabi_attribute 6, 8 ; ARM1156T2F-S: .eabi_attribute 8, 1 ; ARM1156T2F-S: .eabi_attribute 9, 2 ; ARM1156T2F-S: .fpu vfpv2 +; ARM1156T2F-S-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; ARM1156T2F-S: .eabi_attribute 20, 1 ; ARM1156T2F-S: .eabi_attribute 21, 1 +; ARM1156T2F-S-NOT: .eabi_attribute 22 ; ARM1156T2F-S: .eabi_attribute 23, 3 ; ARM1156T2F-S: .eabi_attribute 24, 1 ; ARM1156T2F-S: .eabi_attribute 25, 1 ; ARM1156T2F-S-NOT: .eabi_attribute 27 ; ARM1156T2F-S-NOT: .eabi_attribute 28 ; ARM1156T2F-S-NOT: .eabi_attribute 36 +; ARM1156T2F-S: .eabi_attribute 38, 1 ; ARM1156T2F-S-NOT: .eabi_attribute 42 +; ARM1156T2F-S-NOT: .eabi_attribute 44 ; ARM1156T2F-S-NOT: .eabi_attribute 68 +; ARM1156T2F-S-FAST-NOT: .eabi_attribute 19 +;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally +;; valid for this core, it's an implementation defined question as to which of 0 and 2 you +;; select. LLVM historically picks 0. +; ARM1156T2F-S-FAST-NOT: .eabi_attribute 20 +; ARM1156T2F-S-FAST-NOT: .eabi_attribute 21 +; ARM1156T2F-S-FAST-NOT: .eabi_attribute 22 +; ARM1156T2F-S-FAST: .eabi_attribute 23, 1 + ; V7M: .eabi_attribute 6, 10 ; V7M: .eabi_attribute 7, 77 ; V7M: .eabi_attribute 8, 0 ; V7M: .eabi_attribute 9, 2 +; V7M-NOT: .eabi_attribute 19 +;; The default choice made by llc is for a V7M CPU without an FPU. +;; This is not an interesting detail, but for such CPUs, the default intention is to use +;; software floating-point support. The choice is not important for targets without +;; FPU support! +; V7M: .eabi_attribute 20, 1 +; V7M: .eabi_attribute 21, 1 +; V7M-NOT: .eabi_attribute 22 +; V7M: .eabi_attribute 23, 3 ; V7M: .eabi_attribute 24, 1 ; V7M: .eabi_attribute 25, 1 ; V7M-NOT: .eabi_attribute 27 ; V7M-NOT: .eabi_attribute 28 ; V7M-NOT: .eabi_attribute 36 +; V7M: .eabi_attribute 38, 1 ; V7M-NOT: .eabi_attribute 42 ; V7M-NOT: .eabi_attribute 44 ; V7M-NOT: .eabi_attribute 68 +; V7M-FAST-NOT: .eabi_attribute 19 +;; Despite the V7M CPU having no FPU by default, we chose to flush +;; preserving sign. This matches what the hardware would do in the +;; architecture revision were to exist on the current target. +; V7M-FAST: .eabi_attribute 20, 2 +; V7M-FAST-NOT: .eabi_attribute 21 +; V7M-FAST-NOT: .eabi_attribute 22 +; V7M-FAST: .eabi_attribute 23, 1 + ; V7: .syntax unified ; V7: .eabi_attribute 6, 10 +; V7-NOT: .eabi_attribute 19 +;; In safe-maths mode we default to an IEEE 754 compliant choice. ; V7: .eabi_attribute 20, 1 ; V7: .eabi_attribute 21, 1 +; V7-NOT: .eabi_attribute 22 ; V7: .eabi_attribute 23, 3 ; V7: .eabi_attribute 24, 1 ; V7: .eabi_attribute 25, 1 ; V7-NOT: .eabi_attribute 27 ; V7-NOT: .eabi_attribute 28 ; V7-NOT: .eabi_attribute 36 +; V7: .eabi_attribute 38, 1 ; V7-NOT: .eabi_attribute 42 +; V7-NOT: .eabi_attribute 44 ; V7-NOT: .eabi_attribute 68 +; V7-FAST-NOT: .eabi_attribute 19 +;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes +;; denormals to zero preserving the sign. +; V7-FAST: .eabi_attribute 20, 2 +; V7-FAST-NOT: .eabi_attribute 21 +; V7-FAST-NOT: .eabi_attribute 22 +; V7-FAST: .eabi_attribute 23, 1 + ; V8: .syntax unified +; V8: .eabi_attribute 67, "2.09" ; V8: .eabi_attribute 6, 14 +; V8-NOT: .eabi_attribute 19 +; V8: .eabi_attribute 20, 1 +; V8: .eabi_attribute 21, 1 +; V8-NOT: .eabi_attribute 22 +; V8: .eabi_attribute 23, 3 +; V8-NOT: .eabi_attribute 44 + +; V8-FAST-NOT: .eabi_attribute 19 +;; The default does have an FPU, and for V8-A, it flushes preserving sign. +; V8-FAST: .eabi_attribute 20, 2 +; V8-FAST-NOT: .eabi_attribute 21 +; V8-FAST-NOT: .eabi_attribute 22 +; V8-FAST: .eabi_attribute 23, 1 ; Vt8: .syntax unified ; Vt8: .eabi_attribute 6, 14 +; Vt8-NOT: .eabi_attribute 19 +; Vt8: .eabi_attribute 20, 1 +; Vt8: .eabi_attribute 21, 1 +; Vt8-NOT: .eabi_attribute 22 +; Vt8: .eabi_attribute 23, 3 ; V8-FPARMv8: .syntax unified ; V8-FPARMv8: .eabi_attribute 6, 14 @@ -175,74 +355,95 @@ ; NO-STRICT-ALIGN: .eabi_attribute 34, 1 ; STRICT-ALIGN: .eabi_attribute 34, 0 -; Tag_CPU_arch 'ARMv7' -; CORTEX-A7-CHECK: .eabi_attribute 6, 10 -; CORTEX-A7-NOFPU: .eabi_attribute 6, 10 -; CORTEX-A7-FPUV4: .eabi_attribute 6, 10 +; Tag_CPU_arch 'ARMv7' +; CORTEX-A7-CHECK: .eabi_attribute 6, 10 +; CORTEX-A7-NOFPU: .eabi_attribute 6, 10 + +; CORTEX-A7-FPUV4: .eabi_attribute 6, 10 ; Tag_CPU_arch_profile 'A' -; CORTEX-A7-CHECK: .eabi_attribute 7, 65 -; CORTEX-A7-NOFPU: .eabi_attribute 7, 65 -; CORTEX-A7-FPUV4: .eabi_attribute 7, 65 +; CORTEX-A7-CHECK: .eabi_attribute 7, 65 +; CORTEX-A7-NOFPU: .eabi_attribute 7, 65 +; CORTEX-A7-FPUV4: .eabi_attribute 7, 65 ; Tag_ARM_ISA_use -; CORTEX-A7-CHECK: .eabi_attribute 8, 1 -; CORTEX-A7-NOFPU: .eabi_attribute 8, 1 -; CORTEX-A7-FPUV4: .eabi_attribute 8, 1 +; CORTEX-A7-CHECK: .eabi_attribute 8, 1 +; CORTEX-A7-NOFPU: .eabi_attribute 8, 1 +; CORTEX-A7-FPUV4: .eabi_attribute 8, 1 ; Tag_THUMB_ISA_use -; CORTEX-A7-CHECK: .eabi_attribute 9, 2 -; CORTEX-A7-NOFPU: .eabi_attribute 9, 2 -; CORTEX-A7-FPUV4: .eabi_attribute 9, 2 +; CORTEX-A7-CHECK: .eabi_attribute 9, 2 +; CORTEX-A7-NOFPU: .eabi_attribute 9, 2 +; CORTEX-A7-FPUV4: .eabi_attribute 9, 2 -; CORTEX-A7-CHECK: .fpu neon-vfpv4 +; CORTEX-A7-CHECK: .fpu neon-vfpv4 ; CORTEX-A7-NOFPU-NOT: .fpu -; CORTEX-A7-FPUV4: .fpu vfpv4 +; CORTEX-A7-FPUV4: .fpu vfpv4 +; CORTEX-A7-CHECK-NOT: .eabi_attribute 19 ; Tag_ABI_FP_denormal -; CORTEX-A7-CHECK: .eabi_attribute 20, 1 -; CORTEX-A7-NOFPU: .eabi_attribute 20, 1 -; CORTEX-A7-FPUV4: .eabi_attribute 20, 1 +;; We default to IEEE 754 compliance +; CORTEX-A7-CHECK: .eabi_attribute 20, 1 +;; The A7 has VFPv3 support by default, so flush preserving sign. +; CORTEX-A7-CHECK-FAST: .eabi_attribute 20, 2 +; CORTEX-A7-NOFPU: .eabi_attribute 20, 1 +;; Despite there being no FPU, we chose to flush to zero preserving +;; sign. This matches what the hardware would do for this architecture +;; revision. +; CORTEX-A7-NOFPU-FAST: .eabi_attribute 20, 2 +; CORTEX-A7-FPUV4: .eabi_attribute 20, 1 +;; The VFPv4 FPU flushes preserving sign. +; CORTEX-A7-FPUV4-FAST: .eabi_attribute 20, 2 ; Tag_ABI_FP_exceptions -; CORTEX-A7-CHECK: .eabi_attribute 21, 1 -; CORTEX-A7-NOFPU: .eabi_attribute 21, 1 -; CORTEX-A7-FPUV4: .eabi_attribute 21, 1 +; CORTEX-A7-CHECK: .eabi_attribute 21, 1 +; CORTEX-A7-NOFPU: .eabi_attribute 21, 1 +; CORTEX-A7-FPUV4: .eabi_attribute 21, 1 + +; Tag_ABI_FP_user_exceptions +; CORTEX-A7-CHECK-NOT: .eabi_attribute 22 +; CORTEX-A7-NOFPU-NOT: .eabi_attribute 22 +; CORTEX-A7-FPUV4-NOT: .eabi_attribute 22 ; Tag_ABI_FP_number_model -; CORTEX-A7-CHECK: .eabi_attribute 23, 3 -; CORTEX-A7-NOFPU: .eabi_attribute 23, 3 -; CORTEX-A7-FPUV4: .eabi_attribute 23, 3 +; CORTEX-A7-CHECK: .eabi_attribute 23, 3 +; CORTEX-A7-NOFPU: .eabi_attribute 23, 3 +; CORTEX-A7-FPUV4: .eabi_attribute 23, 3 ; Tag_ABI_align_needed -; CORTEX-A7-CHECK: .eabi_attribute 24, 1 -; CORTEX-A7-NOFPU: .eabi_attribute 24, 1 -; CORTEX-A7-FPUV4: .eabi_attribute 24, 1 +; CORTEX-A7-CHECK: .eabi_attribute 24, 1 +; CORTEX-A7-NOFPU: .eabi_attribute 24, 1 +; CORTEX-A7-FPUV4: .eabi_attribute 24, 1 ; Tag_ABI_align_preserved -; CORTEX-A7-CHECK: .eabi_attribute 25, 1 -; CORTEX-A7-NOFPU: .eabi_attribute 25, 1 -; CORTEX-A7-FPUV4: .eabi_attribute 25, 1 +; CORTEX-A7-CHECK: .eabi_attribute 25, 1 +; CORTEX-A7-NOFPU: .eabi_attribute 25, 1 +; CORTEX-A7-FPUV4: .eabi_attribute 25, 1 ; Tag_FP_HP_extension -; CORTEX-A7-CHECK: .eabi_attribute 36, 1 -; CORTEX-A7-NOFPU: .eabi_attribute 36, 1 -; CORTEX-A7-FPUV4: .eabi_attribute 36, 1 +; CORTEX-A7-CHECK: .eabi_attribute 36, 1 +; CORTEX-A7-NOFPU: .eabi_attribute 36, 1 +; CORTEX-A7-FPUV4: .eabi_attribute 36, 1 + +; Tag_FP_16bit_format +; CORTEX-A7-CHECK: .eabi_attribute 38, 1 +; CORTEX-A7-NOFPU: .eabi_attribute 38, 1 +; CORTEX-A7-FPUV4: .eabi_attribute 38, 1 ; Tag_MPextension_use -; CORTEX-A7-CHECK: .eabi_attribute 42, 1 -; CORTEX-A7-NOFPU: .eabi_attribute 42, 1 -; CORTEX-A7-FPUV4: .eabi_attribute 42, 1 +; CORTEX-A7-CHECK: .eabi_attribute 42, 1 +; CORTEX-A7-NOFPU: .eabi_attribute 42, 1 +; CORTEX-A7-FPUV4: .eabi_attribute 42, 1 ; Tag_DIV_use -; CORTEX-A7-CHECK: .eabi_attribute 44, 2 -; CORTEX-A7-NOFPU: .eabi_attribute 44, 2 -; CORTEX-A7-FPUV4: .eabi_attribute 44, 2 +; CORTEX-A7-CHECK: .eabi_attribute 44, 2 +; CORTEX-A7-NOFPU: .eabi_attribute 44, 2 +; CORTEX-A7-FPUV4: .eabi_attribute 44, 2 ; Tag_Virtualization_use -; CORTEX-A7-CHECK: .eabi_attribute 68, 3 -; CORTEX-A7-NOFPU: .eabi_attribute 68, 3 -; CORTEX-A7-FPUV4: .eabi_attribute 68, 3 +; CORTEX-A7-CHECK: .eabi_attribute 68, 3 +; CORTEX-A7-NOFPU: .eabi_attribute 68, 3 +; CORTEX-A7-FPUV4: .eabi_attribute 68, 3 ; CORTEX-A5-DEFAULT: .cpu cortex-a5 ; CORTEX-A5-DEFAULT: .eabi_attribute 6, 10 @@ -250,84 +451,146 @@ ; CORTEX-A5-DEFAULT: .eabi_attribute 8, 1 ; CORTEX-A5-DEFAULT: .eabi_attribute 9, 2 ; CORTEX-A5-DEFAULT: .fpu neon-vfpv4 +; CORTEX-A5-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-A5-DEFAULT: .eabi_attribute 20, 1 ; CORTEX-A5-DEFAULT: .eabi_attribute 21, 1 +; CORTEX-A5-DEFAULT-NOT: .eabi_attribute 22 ; CORTEX-A5-DEFAULT: .eabi_attribute 23, 3 ; CORTEX-A5-DEFAULT: .eabi_attribute 24, 1 ; CORTEX-A5-DEFAULT: .eabi_attribute 25, 1 ; CORTEX-A5-DEFAULT: .eabi_attribute 42, 1 +; CORTEX-A5-DEFAULT-NOT: .eabi_attribute 44 ; CORTEX-A5-DEFAULT: .eabi_attribute 68, 1 +; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 19 +;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math +;; is given. +; CORTEX-A5-DEFAULT-FAST: .eabi_attribute 20, 2 +; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 21 +; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 22 +; CORTEX-A5-DEFAULT-FAST: .eabi_attribute 23, 1 + ; CORTEX-A5-NONEON: .cpu cortex-a5 ; CORTEX-A5-NONEON: .eabi_attribute 6, 10 ; CORTEX-A5-NONEON: .eabi_attribute 7, 65 ; CORTEX-A5-NONEON: .eabi_attribute 8, 1 ; CORTEX-A5-NONEON: .eabi_attribute 9, 2 ; CORTEX-A5-NONEON: .fpu vfpv4-d16 +;; We default to IEEE 754 compliance ; CORTEX-A5-NONEON: .eabi_attribute 20, 1 ; CORTEX-A5-NONEON: .eabi_attribute 21, 1 +; CORTEX-A5-NONEON-NOT: .eabi_attribute 22 ; CORTEX-A5-NONEON: .eabi_attribute 23, 3 ; CORTEX-A5-NONEON: .eabi_attribute 24, 1 ; CORTEX-A5-NONEON: .eabi_attribute 25, 1 ; CORTEX-A5-NONEON: .eabi_attribute 42, 1 ; CORTEX-A5-NONEON: .eabi_attribute 68, 1 +; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 19 +;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math +;; is given. +; CORTEX-A5-NONEON-FAST: .eabi_attribute 20, 2 +; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 21 +; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 22 +; CORTEX-A5-NONEON-FAST: .eabi_attribute 23, 1 + ; CORTEX-A5-NOFPU: .cpu cortex-a5 ; CORTEX-A5-NOFPU: .eabi_attribute 6, 10 ; CORTEX-A5-NOFPU: .eabi_attribute 7, 65 ; CORTEX-A5-NOFPU: .eabi_attribute 8, 1 ; CORTEX-A5-NOFPU: .eabi_attribute 9, 2 ; CORTEX-A5-NOFPU-NOT: .fpu +; CORTEX-A5-NOFPU-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-A5-NOFPU: .eabi_attribute 20, 1 ; CORTEX-A5-NOFPU: .eabi_attribute 21, 1 +; CORTEX-A5-NOFPU-NOT: .eabi_attribute 22 ; CORTEX-A5-NOFPU: .eabi_attribute 23, 3 ; CORTEX-A5-NOFPU: .eabi_attribute 24, 1 ; CORTEX-A5-NOFPU: .eabi_attribute 25, 1 ; CORTEX-A5-NOFPU: .eabi_attribute 42, 1 ; CORTEX-A5-NOFPU: .eabi_attribute 68, 1 +; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 19 +;; Despite there being no FPU, we chose to flush to zero preserving +;; sign. This matches what the hardware would do for this architecture +;; revision. +; CORTEX-A5-NOFPU-FAST: .eabi_attribute 20, 2 +; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 21 +; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 22 +; CORTEX-A5-NOFPU-FAST: .eabi_attribute 23, 1 + ; CORTEX-A9-SOFT: .cpu cortex-a9 ; CORTEX-A9-SOFT: .eabi_attribute 6, 10 ; CORTEX-A9-SOFT: .eabi_attribute 7, 65 ; CORTEX-A9-SOFT: .eabi_attribute 8, 1 ; CORTEX-A9-SOFT: .eabi_attribute 9, 2 ; CORTEX-A9-SOFT: .fpu neon +; CORTEX-A9-SOFT-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-A9-SOFT: .eabi_attribute 20, 1 ; CORTEX-A9-SOFT: .eabi_attribute 21, 1 +; CORTEX-A9-SOFT-NOT: .eabi_attribute 22 ; CORTEX-A9-SOFT: .eabi_attribute 23, 3 ; CORTEX-A9-SOFT: .eabi_attribute 24, 1 ; CORTEX-A9-SOFT: .eabi_attribute 25, 1 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 27 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 28 ; CORTEX-A9-SOFT: .eabi_attribute 36, 1 +; CORTEX-A9-SOFT: .eabi_attribute 38, 1 ; CORTEX-A9-SOFT: .eabi_attribute 42, 1 +; CORTEX-A9-SOFT-NOT: .eabi_attribute 44 ; CORTEX-A9-SOFT: .eabi_attribute 68, 1 +; CORTEX-A9-SOFT-FAST-NOT: .eabi_attribute 19 +;; The A9 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; -ffast-math is specified. +; CORTEX-A9-SOFT-FAST: .eabi_attribute 20, 2 +; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 21 +; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 22 +; CORTEX-A5-SOFT-FAST: .eabi_attribute 23, 1 + ; CORTEX-A9-HARD: .cpu cortex-a9 ; CORTEX-A9-HARD: .eabi_attribute 6, 10 ; CORTEX-A9-HARD: .eabi_attribute 7, 65 ; CORTEX-A9-HARD: .eabi_attribute 8, 1 ; CORTEX-A9-HARD: .eabi_attribute 9, 2 ; CORTEX-A9-HARD: .fpu neon +; CORTEX-A9-HARD-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-A9-HARD: .eabi_attribute 20, 1 ; CORTEX-A9-HARD: .eabi_attribute 21, 1 +; CORTEX-A9-HARD-NOT: .eabi_attribute 22 ; CORTEX-A9-HARD: .eabi_attribute 23, 3 ; CORTEX-A9-HARD: .eabi_attribute 24, 1 ; CORTEX-A9-HARD: .eabi_attribute 25, 1 ; CORTEX-A9-HARD-NOT: .eabi_attribute 27 ; CORTEX-A9-HARD: .eabi_attribute 28, 1 ; CORTEX-A9-HARD: .eabi_attribute 36, 1 +; CORTEX-A9-HARD: .eabi_attribute 38, 1 ; CORTEX-A9-HARD: .eabi_attribute 42, 1 ; CORTEX-A9-HARD: .eabi_attribute 68, 1 +; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 19 +;; The A9 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; -ffast-math is specified. +; CORTEX-A9-HARD-FAST: .eabi_attribute 20, 2 +; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 21 +; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 22 +; CORTEX-A9-HARD-FAST: .eabi_attribute 23, 1 + ; CORTEX-A12-DEFAULT: .cpu cortex-a12 ; CORTEX-A12-DEFAULT: .eabi_attribute 6, 10 ; CORTEX-A12-DEFAULT: .eabi_attribute 7, 65 ; CORTEX-A12-DEFAULT: .eabi_attribute 8, 1 ; CORTEX-A12-DEFAULT: .eabi_attribute 9, 2 ; CORTEX-A12-DEFAULT: .fpu neon-vfpv4 +; CORTEX-A12-DEFAULT-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-A12-DEFAULT: .eabi_attribute 20, 1 ; CORTEX-A12-DEFAULT: .eabi_attribute 21, 1 +; CORTEX-A12-DEFAULT-NOT: .eabi_attribute 22 ; CORTEX-A12-DEFAULT: .eabi_attribute 23, 3 ; CORTEX-A12-DEFAULT: .eabi_attribute 24, 1 ; CORTEX-A12-DEFAULT: .eabi_attribute 25, 1 @@ -335,14 +598,25 @@ ; CORTEX-A12-DEFAULT: .eabi_attribute 44, 2 ; CORTEX-A12-DEFAULT: .eabi_attribute 68, 3 +; CORTEX-A12-DEFAULT-FAST-NOT: .eabi_attribute 19 +;; The A12 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; -ffast-math is specified. +; CORTEX-A12-DEFAULT-FAST: .eabi_attribute 20, 2 +; CORTEX-A12-HARD-FAST-NOT: .eabi_attribute 21 +; CORTEX-A12-HARD-FAST-NOT: .eabi_attribute 22 +; CORTEX-A12-HARD-FAST: .eabi_attribute 23, 1 + ; CORTEX-A12-NOFPU: .cpu cortex-a12 ; CORTEX-A12-NOFPU: .eabi_attribute 6, 10 ; CORTEX-A12-NOFPU: .eabi_attribute 7, 65 ; CORTEX-A12-NOFPU: .eabi_attribute 8, 1 ; CORTEX-A12-NOFPU: .eabi_attribute 9, 2 ; CORTEX-A12-NOFPU-NOT: .fpu +; CORTEX-A12-NOFPU-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-A12-NOFPU: .eabi_attribute 20, 1 ; CORTEX-A12-NOFPU: .eabi_attribute 21, 1 +; CORTEX-A12-NOFPU-NOT: .eabi_attribute 22 ; CORTEX-A12-NOFPU: .eabi_attribute 23, 3 ; CORTEX-A12-NOFPU: .eabi_attribute 24, 1 ; CORTEX-A12-NOFPU: .eabi_attribute 25, 1 @@ -350,32 +624,56 @@ ; CORTEX-A12-NOFPU: .eabi_attribute 44, 2 ; CORTEX-A12-NOFPU: .eabi_attribute 68, 3 +; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 19 +;; Despite there being no FPU, we chose to flush to zero preserving +;; sign. This matches what the hardware would do for this architecture +;; revision. +; CORTEX-A12-NOFPU-FAST: .eabi_attribute 20, 2 +; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 21 +; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 22 +; CORTEX-A12-NOFPU-FAST: .eabi_attribute 23, 1 + ; CORTEX-A15: .cpu cortex-a15 ; CORTEX-A15: .eabi_attribute 6, 10 ; CORTEX-A15: .eabi_attribute 7, 65 ; CORTEX-A15: .eabi_attribute 8, 1 ; CORTEX-A15: .eabi_attribute 9, 2 ; CORTEX-A15: .fpu neon-vfpv4 +; CORTEX-A15-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-A15: .eabi_attribute 20, 1 ; CORTEX-A15: .eabi_attribute 21, 1 +; CORTEX-A15-NOT: .eabi_attribute 22 ; CORTEX-A15: .eabi_attribute 23, 3 ; CORTEX-A15: .eabi_attribute 24, 1 ; CORTEX-A15: .eabi_attribute 25, 1 ; CORTEX-A15-NOT: .eabi_attribute 27 ; CORTEX-A15-NOT: .eabi_attribute 28 ; CORTEX-A15: .eabi_attribute 36, 1 +; CORTEX-A15: .eabi_attribute 38, 1 ; CORTEX-A15: .eabi_attribute 42, 1 ; CORTEX-A15: .eabi_attribute 44, 2 ; CORTEX-A15: .eabi_attribute 68, 3 +; CORTEX-A15-FAST-NOT: .eabi_attribute 19 +;; The A15 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; -ffast-math is specified. +; CORTEX-A15-FAST: .eabi_attribute 20, 2 +; CORTEX-A15-FAST-NOT: .eabi_attribute 21 +; CORTEX-A15-FAST-NOT: .eabi_attribute 22 +; CORTEX-A15-FAST: .eabi_attribute 23, 1 + ; CORTEX-A17-DEFAULT: .cpu cortex-a17 ; CORTEX-A17-DEFAULT: .eabi_attribute 6, 10 ; CORTEX-A17-DEFAULT: .eabi_attribute 7, 65 ; CORTEX-A17-DEFAULT: .eabi_attribute 8, 1 ; CORTEX-A17-DEFAULT: .eabi_attribute 9, 2 ; CORTEX-A17-DEFAULT: .fpu neon-vfpv4 +; CORTEX-A17-DEFAULT-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-A17-DEFAULT: .eabi_attribute 20, 1 ; CORTEX-A17-DEFAULT: .eabi_attribute 21, 1 +; CORTEX-A17-DEFAULT-NOT: .eabi_attribute 22 ; CORTEX-A17-DEFAULT: .eabi_attribute 23, 3 ; CORTEX-A17-DEFAULT: .eabi_attribute 24, 1 ; CORTEX-A17-DEFAULT: .eabi_attribute 25, 1 @@ -383,14 +681,25 @@ ; CORTEX-A17-DEFAULT: .eabi_attribute 44, 2 ; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3 +; CORTEX-A17-FAST-NOT: .eabi_attribute 19 +;; The A17 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; -ffast-math is specified. +; CORTEX-A17-FAST: .eabi_attribute 20, 2 +; CORTEX-A17-FAST-NOT: .eabi_attribute 21 +; CORTEX-A17-FAST-NOT: .eabi_attribute 22 +; CORTEX-A17-FAST: .eabi_attribute 23, 1 + ; CORTEX-A17-NOFPU: .cpu cortex-a17 ; CORTEX-A17-NOFPU: .eabi_attribute 6, 10 ; CORTEX-A17-NOFPU: .eabi_attribute 7, 65 ; CORTEX-A17-NOFPU: .eabi_attribute 8, 1 ; CORTEX-A17-NOFPU: .eabi_attribute 9, 2 ; CORTEX-A17-NOFPU-NOT: .fpu +; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-A17-NOFPU: .eabi_attribute 20, 1 ; CORTEX-A17-NOFPU: .eabi_attribute 21, 1 +; CORTEX-A17-NOFPU-NOT: .eabi_attribute 22 ; CORTEX-A17-NOFPU: .eabi_attribute 23, 3 ; CORTEX-A17-NOFPU: .eabi_attribute 24, 1 ; CORTEX-A17-NOFPU: .eabi_attribute 25, 1 @@ -398,72 +707,263 @@ ; CORTEX-A17-NOFPU: .eabi_attribute 44, 2 ; CORTEX-A17-NOFPU: .eabi_attribute 68, 3 +; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19 +;; Despite there being no FPU, we chose to flush to zero preserving +;; sign. This matches what the hardware would do for this architecture +;; revision. +; CORTEX-A17-NOFPU-FAST: .eabi_attribute 20, 2 +; CORTEX-A17-NOFPU-FAST-NOT: .eabi_attribute 21 +; CORTEX-A17-NOFPU-FAST-NOT: .eabi_attribute 22 +; CORTEX-A17-NOFPU-FAST: .eabi_attribute 23, 1 + ; CORTEX-M0: .cpu cortex-m0 ; CORTEX-M0: .eabi_attribute 6, 12 ; CORTEX-M0-NOT: .eabi_attribute 7 ; CORTEX-M0: .eabi_attribute 8, 0 ; CORTEX-M0: .eabi_attribute 9, 1 +; CORTEX-M0-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-M0: .eabi_attribute 20, 1 +; CORTEX-M0: .eabi_attribute 21, 1 +; CORTEX-M0-NOT: .eabi_attribute 22 +; CORTEX-M0: .eabi_attribute 23, 3 ; CORTEX-M0: .eabi_attribute 24, 1 ; CORTEX-M0: .eabi_attribute 25, 1 ; CORTEX-M0-NOT: .eabi_attribute 27 ; CORTEX-M0-NOT: .eabi_attribute 28 ; CORTEX-M0-NOT: .eabi_attribute 36 +; CORTEX-M0: .eabi_attribute 38, 1 ; CORTEX-M0-NOT: .eabi_attribute 42 +; CORTEX-M0-NOT: .eabi_attribute 44 ; CORTEX-M0-NOT: .eabi_attribute 68 +; CORTEX-M0-FAST-NOT: .eabi_attribute 19 +;; Despite the M0 CPU having no FPU in this scenario, we chose to +;; flush to positive zero here. There's no hardware support doing +;; this, but the fast maths software library might and such behaviour +;; would match hardware support on this architecture revision if it +;; existed. +; CORTEX-M0-FAST-NOT: .eabi_attribute 20 +; CORTEX-M0-FAST-NOT: .eabi_attribute 21 +; CORTEX-M0-FAST-NOT: .eabi_attribute 22 +; CORTEX-M0-FAST: .eabi_attribute 23, 1 + +; CORTEX-M0PLUS: .cpu cortex-m0plus +; CORTEX-M0PLUS: .eabi_attribute 6, 12 +; CORTEX-M0PLUS-NOT: .eabi_attribute 7 +; CORTEX-M0PLUS: .eabi_attribute 8, 0 +; CORTEX-M0PLUS: .eabi_attribute 9, 1 +; CORTEX-M0PLUS-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-M0PLUS: .eabi_attribute 20, 1 +; CORTEX-M0PLUS: .eabi_attribute 21, 1 +; CORTEX-M0PLUS-NOT: .eabi_attribute 22 +; CORTEX-M0PLUS: .eabi_attribute 23, 3 +; CORTEX-M0PLUS: .eabi_attribute 24, 1 +; CORTEX-M0PLUS: .eabi_attribute 25, 1 +; CORTEX-M0PLUS-NOT: .eabi_attribute 27 +; CORTEX-M0PLUS-NOT: .eabi_attribute 28 +; CORTEX-M0PLUS-NOT: .eabi_attribute 36 +; CORTEX-M0PLUS: .eabi_attribute 38, 1 +; CORTEX-M0PLUS-NOT: .eabi_attribute 42 +; CORTEX-M0PLUS-NOT: .eabi_attribute 44 +; CORTEX-M0PLUS-NOT: .eabi_attribute 68 + +; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 19 +;; Despite the M0+ CPU having no FPU in this scenario, we chose to +;; flush to positive zero here. There's no hardware support doing +;; this, but the fast maths software library might and such behaviour +;; would match hardware support on this architecture revision if it +;; existed. +; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 20 +; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 21 +; CORTEX-M0PLUS-FAST-NOT: .eabi_attribute 22 +; CORTEX-M0PLUS-FAST: .eabi_attribute 23, 1 + +; CORTEX-M1: .cpu cortex-m1 +; CORTEX-M1: .eabi_attribute 6, 12 +; CORTEX-M1-NOT: .eabi_attribute 7 +; CORTEX-M1: .eabi_attribute 8, 0 +; CORTEX-M1: .eabi_attribute 9, 1 +; CORTEX-M1-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-M1: .eabi_attribute 20, 1 +; CORTEX-M1: .eabi_attribute 21, 1 +; CORTEX-M1-NOT: .eabi_attribute 22 +; CORTEX-M1: .eabi_attribute 23, 3 +; CORTEX-M1: .eabi_attribute 24, 1 +; CORTEX-M1: .eabi_attribute 25, 1 +; CORTEX-M1-NOT: .eabi_attribute 27 +; CORTEX-M1-NOT: .eabi_attribute 28 +; CORTEX-M1-NOT: .eabi_attribute 36 +; CORTEX-M1: .eabi_attribute 38, 1 +; CORTEX-M1-NOT: .eabi_attribute 42 +; CORTEX-M1-NOT: .eabi_attribute 44 +; CORTEX-M1-NOT: .eabi_attribute 68 + +; CORTEX-M1-FAST-NOT: .eabi_attribute 19 +;; Despite the M1 CPU having no FPU in this scenario, we chose to +;; flush to positive zero here. There's no hardware support doing +;; this, but the fast maths software library might and such behaviour +;; would match hardware support on this architecture revision if it +;; existed. +; CORTEX-M1-FAST-NOT: .eabi_attribute 20 +; CORTEX-M1-FAST-NOT: .eabi_attribute 21 +; CORTEX-M1-FAST-NOT: .eabi_attribute 22 +; CORTEX-M1-FAST: .eabi_attribute 23, 1 + +; SC000: .cpu sc000 +; SC000: .eabi_attribute 6, 12 +; SC000-NOT: .eabi_attribute 7 +; SC000: .eabi_attribute 8, 0 +; SC000: .eabi_attribute 9, 1 +; SC000-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; SC000: .eabi_attribute 20, 1 +; SC000: .eabi_attribute 21, 1 +; SC000-NOT: .eabi_attribute 22 +; SC000: .eabi_attribute 23, 3 +; SC000: .eabi_attribute 24, 1 +; SC000: .eabi_attribute 25, 1 +; SC000-NOT: .eabi_attribute 27 +; SC000-NOT: .eabi_attribute 28 +; SC000-NOT: .eabi_attribute 36 +; SC000: .eabi_attribute 38, 1 +; SC000-NOT: .eabi_attribute 42 +; SC000-NOT: .eabi_attribute 44 +; SC000-NOT: .eabi_attribute 68 + +; SC000-FAST-NOT: .eabi_attribute 19 +;; Despite the SC000 CPU having no FPU in this scenario, we chose to +;; flush to positive zero here. There's no hardware support doing +;; this, but the fast maths software library might and such behaviour +;; would match hardware support on this architecture revision if it +;; existed. +; SC000-FAST-NOT: .eabi_attribute 20 +; SC000-FAST-NOT: .eabi_attribute 21 +; SC000-FAST-NOT: .eabi_attribute 22 +; SC000-FAST: .eabi_attribute 23, 1 + ; CORTEX-M3: .cpu cortex-m3 ; CORTEX-M3: .eabi_attribute 6, 10 ; CORTEX-M3: .eabi_attribute 7, 77 ; CORTEX-M3: .eabi_attribute 8, 0 ; CORTEX-M3: .eabi_attribute 9, 2 +; CORTEX-M3-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-M3: .eabi_attribute 20, 1 ; CORTEX-M3: .eabi_attribute 21, 1 +; CORTEX-M3-NOT: .eabi_attribute 22 ; CORTEX-M3: .eabi_attribute 23, 3 ; CORTEX-M3: .eabi_attribute 24, 1 ; CORTEX-M3: .eabi_attribute 25, 1 ; CORTEX-M3-NOT: .eabi_attribute 27 ; CORTEX-M3-NOT: .eabi_attribute 28 ; CORTEX-M3-NOT: .eabi_attribute 36 +; CORTEX-M3: .eabi_attribute 38, 1 ; CORTEX-M3-NOT: .eabi_attribute 42 ; CORTEX-M3-NOT: .eabi_attribute 44 ; CORTEX-M3-NOT: .eabi_attribute 68 +; CORTEX-M3-FAST-NOT: .eabi_attribute 19 +;; Despite there being no FPU, we chose to flush to zero preserving +;; sign. This matches what the hardware would do for this architecture +;; revision. +; CORTEX-M3-FAST: .eabi_attribute 20, 2 +; CORTEX-M3-FAST-NOT: .eabi_attribute 21 +; CORTEX-M3-FAST-NOT: .eabi_attribute 22 +; CORTEX-M3-FAST: .eabi_attribute 23, 1 + +; SC300: .cpu sc300 +; SC300: .eabi_attribute 6, 10 +; SC300: .eabi_attribute 7, 77 +; SC300: .eabi_attribute 8, 0 +; SC300: .eabi_attribute 9, 2 +; SC300-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; SC300: .eabi_attribute 20, 1 +; SC300: .eabi_attribute 21, 1 +; SC300-NOT: .eabi_attribute 22 +; SC300: .eabi_attribute 23, 3 +; SC300: .eabi_attribute 24, 1 +; SC300: .eabi_attribute 25, 1 +; SC300-NOT: .eabi_attribute 27 +; SC300-NOT: .eabi_attribute 28 +; SC300-NOT: .eabi_attribute 36 +; SC300: .eabi_attribute 38, 1 +; SC300-NOT: .eabi_attribute 42 +; SC300-NOT: .eabi_attribute 44 +; SC300-NOT: .eabi_attribute 68 + +; SC300-FAST-NOT: .eabi_attribute 19 +;; Despite there being no FPU, we chose to flush to zero preserving +;; sign. This matches what the hardware would do for this architecture +;; revision. +; SC300-FAST: .eabi_attribute 20, 2 +; SC300-FAST-NOT: .eabi_attribute 21 +; SC300-FAST-NOT: .eabi_attribute 22 +; SC300-FAST: .eabi_attribute 23, 1 + ; CORTEX-M4-SOFT: .cpu cortex-m4 ; CORTEX-M4-SOFT: .eabi_attribute 6, 13 ; CORTEX-M4-SOFT: .eabi_attribute 7, 77 ; CORTEX-M4-SOFT: .eabi_attribute 8, 0 ; CORTEX-M4-SOFT: .eabi_attribute 9, 2 ; CORTEX-M4-SOFT: .fpu vfpv4-d16 +; CORTEX-M4-SOFT-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-M4-SOFT: .eabi_attribute 20, 1 ; CORTEX-M4-SOFT: .eabi_attribute 21, 1 +; CORTEX-M4-SOFT-NOT: .eabi_attribute 22 ; CORTEX-M4-SOFT: .eabi_attribute 23, 3 ; CORTEX-M4-SOFT: .eabi_attribute 24, 1 ; CORTEX-M4-SOFT: .eabi_attribute 25, 1 ; CORTEX-M4-SOFT: .eabi_attribute 27, 1 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 28 ; CORTEX-M4-SOFT: .eabi_attribute 36, 1 +; CORTEX-M4-SOFT: .eabi_attribute 38, 1 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 42 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 44 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 68 +; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 19 +;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when +;; -ffast-math is specified. +; CORTEX-M4-SOFT-FAST: .eabi_attribute 20, 2 +; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 21 +; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 22 +; CORTEX-M4-SOFT-FAST: .eabi_attribute 23, 1 + ; CORTEX-M4-HARD: .cpu cortex-m4 ; CORTEX-M4-HARD: .eabi_attribute 6, 13 ; CORTEX-M4-HARD: .eabi_attribute 7, 77 ; CORTEX-M4-HARD: .eabi_attribute 8, 0 ; CORTEX-M4-HARD: .eabi_attribute 9, 2 ; CORTEX-M4-HARD: .fpu vfpv4-d16 +; CORTEX-M4-HARD-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-M4-HARD: .eabi_attribute 20, 1 ; CORTEX-M4-HARD: .eabi_attribute 21, 1 +; CORTEX-M4-HARD-NOT: .eabi_attribute 22 ; CORTEX-M4-HARD: .eabi_attribute 23, 3 ; CORTEX-M4-HARD: .eabi_attribute 24, 1 ; CORTEX-M4-HARD: .eabi_attribute 25, 1 ; CORTEX-M4-HARD: .eabi_attribute 27, 1 ; CORTEX-M4-HARD: .eabi_attribute 28, 1 ; CORTEX-M4-HARD: .eabi_attribute 36, 1 +; CORTEX-M4-HARD: .eabi_attribute 38, 1 ; CORTEX-M4-HARD-NOT: .eabi_attribute 42 ; CORTEX-M4-HARD-NOT: .eabi_attribute 44 ; CORTEX-M4-HARD-NOT: .eabi_attribute 68 +; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 19 +;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when +;; -ffast-math is specified. +; CORTEX-M4-HARD-FAST: .eabi_attribute 20, 2 +; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 21 +; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 22 +; CORTEX-M4-HARD-FAST: .eabi_attribute 23, 1 + ; CORTEX-M7: .cpu cortex-m7 ; CORTEX-M7: .eabi_attribute 6, 13 ; CORTEX-M7: .eabi_attribute 7, 77 @@ -473,8 +973,11 @@ ; CORTEX-M7-SINGLE: .fpu fpv5-d16 ; CORTEX-M7-DOUBLE: .fpu fpv5-d16 ; CORTEX-M7: .eabi_attribute 17, 1 +; CORTEX-M7-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-M7: .eabi_attribute 20, 1 ; CORTEX-M7: .eabi_attribute 21, 1 +; CORTEX-M7-NOT: .eabi_attribute 22 ; CORTEX-M7: .eabi_attribute 23, 3 ; CORTEX-M7: .eabi_attribute 24, 1 ; CORTEX-M7: .eabi_attribute 25, 1 @@ -482,26 +985,79 @@ ; CORTEX-M7-SINGLE: .eabi_attribute 27, 1 ; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27 ; CORTEX-M7: .eabi_attribute 36, 1 +; CORTEX-M7: .eabi_attribute 38, 1 +; CORTEX-M7-NOT: .eabi_attribute 44 ; CORTEX-M7: .eabi_attribute 14, 0 +; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 19 +;; The M7 has the ARMv8 FP unit, which always flushes preserving sign. +; CORTEX-M7-FAST: .eabi_attribute 20, 2 +;; Despite there being no FPU, we chose to flush to zero preserving +;; sign. This matches what the hardware would do for this architecture +;; revision. +; CORTEX-M7-NOFPU-FAST: .eabi_attribute 20, 2 +; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 21 +; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 22 +; CORTEX-M7-NOFPU-FAST: .eabi_attribute 23, 1 + ; CORTEX-R5: .cpu cortex-r5 ; CORTEX-R5: .eabi_attribute 6, 10 ; CORTEX-R5: .eabi_attribute 7, 82 ; CORTEX-R5: .eabi_attribute 8, 1 ; CORTEX-R5: .eabi_attribute 9, 2 ; CORTEX-R5: .fpu vfpv3-d16 +; CORTEX-R5-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance ; CORTEX-R5: .eabi_attribute 20, 1 ; CORTEX-R5: .eabi_attribute 21, 1 +; CORTEX-R5-NOT: .eabi_attribute 22 ; CORTEX-R5: .eabi_attribute 23, 3 ; CORTEX-R5: .eabi_attribute 24, 1 ; CORTEX-R5: .eabi_attribute 25, 1 ; CORTEX-R5: .eabi_attribute 27, 1 ; CORTEX-R5-NOT: .eabi_attribute 28 ; CORTEX-R5-NOT: .eabi_attribute 36 +; CORTEX-R5: .eabi_attribute 38, 1 ; CORTEX-R5-NOT: .eabi_attribute 42 ; CORTEX-R5: .eabi_attribute 44, 2 ; CORTEX-R5-NOT: .eabi_attribute 68 +; CORTEX-R5-FAST-NOT: .eabi_attribute 19 +;; The R5 has the VFPv3 FP unit, which always flushes preserving sign. +; CORTEX-R5-FAST: .eabi_attribute 20, 2 +; CORTEX-R5-FAST-NOT: .eabi_attribute 21 +; CORTEX-R5-FAST-NOT: .eabi_attribute 22 +; CORTEX-R5-FAST: .eabi_attribute 23, 1 + +; CORTEX-R7: .cpu cortex-r7 +; CORTEX-R7: .eabi_attribute 6, 10 +; CORTEX-R7: .eabi_attribute 7, 82 +; CORTEX-R7: .eabi_attribute 8, 1 +; CORTEX-R7: .eabi_attribute 9, 2 +; CORTEX-R7: .fpu vfpv3-d16 +; CORTEX-R7-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-R7: .eabi_attribute 20, 1 +; CORTEX-R7: .eabi_attribute 21, 1 +; CORTEX-R7-NOT: .eabi_attribute 22 +; CORTEX-R7: .eabi_attribute 23, 3 +; CORTEX-R7: .eabi_attribute 24, 1 +; CORTEX-R7: .eabi_attribute 25, 1 +; CORTEX-R7: .eabi_attribute 27, 1 +; CORTEX-R7-NOT: .eabi_attribute 28 +; CORTEX-R7-NOT: .eabi_attribute 36 +; CORTEX-R7: .eabi_attribute 38, 1 +; CORTEX-R7: .eabi_attribute 42, 1 +; CORTEX-R7: .eabi_attribute 44, 2 +; CORTEX-R7-NOT: .eabi_attribute 68 + +; CORTEX-R7-FAST-NOT: .eabi_attribute 19 +;; The R7 has the VFPv3 FP unit, which always flushes preserving sign. +; CORTEX-R7-FAST: .eabi_attribute 20, 2 +; CORTEX-R7-FAST-NOT: .eabi_attribute 21 +; CORTEX-R7-FAST-NOT: .eabi_attribute 22 +; CORTEX-R7-FAST: .eabi_attribute 23, 1 + ; CORTEX-A53: .cpu cortex-a53 ; CORTEX-A53: .eabi_attribute 6, 14 ; CORTEX-A53: .eabi_attribute 7, 65 @@ -509,15 +1065,29 @@ ; CORTEX-A53: .eabi_attribute 9, 2 ; CORTEX-A53: .fpu crypto-neon-fp-armv8 ; CORTEX-A53: .eabi_attribute 12, 3 +; CORTEX-A53-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-A53: .eabi_attribute 20, 1 +; CORTEX-A53: .eabi_attribute 21, 1 +; CORTEX-A53-NOT: .eabi_attribute 22 +; CORTEX-A53: .eabi_attribute 23, 3 ; CORTEX-A53: .eabi_attribute 24, 1 ; CORTEX-A53: .eabi_attribute 25, 1 ; CORTEX-A53-NOT: .eabi_attribute 27 ; CORTEX-A53-NOT: .eabi_attribute 28 ; CORTEX-A53: .eabi_attribute 36, 1 +; CORTEX-A53: .eabi_attribute 38, 1 ; CORTEX-A53: .eabi_attribute 42, 1 ; CORTEX-A53-NOT: .eabi_attribute 44 ; CORTEX-A53: .eabi_attribute 68, 3 +; CORTEX-A53-FAST-NOT: .eabi_attribute 19 +;; The A53 has the ARMv8 FP unit, which always flushes preserving sign. +; CORTEX-A53-FAST: .eabi_attribute 20, 2 +; CORTEX-A53-FAST-NOT: .eabi_attribute 21 +; CORTEX-A53-FAST-NOT: .eabi_attribute 22 +; CORTEX-A53-FAST: .eabi_attribute 23, 1 + ; CORTEX-A57: .cpu cortex-a57 ; CORTEX-A57: .eabi_attribute 6, 14 ; CORTEX-A57: .eabi_attribute 7, 65 @@ -525,15 +1095,59 @@ ; CORTEX-A57: .eabi_attribute 9, 2 ; CORTEX-A57: .fpu crypto-neon-fp-armv8 ; CORTEX-A57: .eabi_attribute 12, 3 +; CORTEX-A57-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-A57: .eabi_attribute 20, 1 +; CORTEX-A57: .eabi_attribute 21, 1 +; CORTEX-A57-NOT: .eabi_attribute 22 +; CORTEX-A57: .eabi_attribute 23, 3 ; CORTEX-A57: .eabi_attribute 24, 1 ; CORTEX-A57: .eabi_attribute 25, 1 ; CORTEX-A57-NOT: .eabi_attribute 27 ; CORTEX-A57-NOT: .eabi_attribute 28 ; CORTEX-A57: .eabi_attribute 36, 1 +; CORTEX-A57: .eabi_attribute 38, 1 ; CORTEX-A57: .eabi_attribute 42, 1 ; CORTEX-A57-NOT: .eabi_attribute 44 ; CORTEX-A57: .eabi_attribute 68, 3 +; CORTEX-A57-FAST-NOT: .eabi_attribute 19 +;; The A57 has the ARMv8 FP unit, which always flushes preserving sign. +; CORTEX-A57-FAST: .eabi_attribute 20, 2 +; CORTEX-A57-FAST-NOT: .eabi_attribute 21 +; CORTEX-A57-FAST-NOT: .eabi_attribute 22 +; CORTEX-A57-FAST: .eabi_attribute 23, 1 + +; CORTEX-A72: .cpu cortex-a72 +; CORTEX-A72: .eabi_attribute 6, 14 +; CORTEX-A72: .eabi_attribute 7, 65 +; CORTEX-A72: .eabi_attribute 8, 1 +; CORTEX-A72: .eabi_attribute 9, 2 +; CORTEX-A72: .fpu crypto-neon-fp-armv8 +; CORTEX-A72: .eabi_attribute 12, 3 +; CORTEX-A72-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-A72: .eabi_attribute 20, 1 +; CORTEX-A72: .eabi_attribute 21, 1 +; CORTEX-A72-NOT: .eabi_attribute 22 +; CORTEX-A72: .eabi_attribute 23, 3 +; CORTEX-A72: .eabi_attribute 24, 1 +; CORTEX-A72: .eabi_attribute 25, 1 +; CORTEX-A72-NOT: .eabi_attribute 27 +; CORTEX-A72-NOT: .eabi_attribute 28 +; CORTEX-A72: .eabi_attribute 36, 1 +; CORTEX-A72: .eabi_attribute 38, 1 +; CORTEX-A72: .eabi_attribute 42, 1 +; CORTEX-A72-NOT: .eabi_attribute 44 +; CORTEX-A72: .eabi_attribute 68, 3 + +; CORTEX-A72-FAST-NOT: .eabi_attribute 19 +;; The A72 has the ARMv8 FP unit, which always flushes preserving sign. +; CORTEX-A72-FAST: .eabi_attribute 20, 2 +; CORTEX-A72-FAST-NOT: .eabi_attribute 21 +; CORTEX-A72-FAST-NOT: .eabi_attribute 22 +; CORTEX-A72-FAST: .eabi_attribute 23, 1 + ; RELOC-PIC: .eabi_attribute 15, 1 ; RELOC-PIC: .eabi_attribute 16, 1 ; RELOC-PIC: .eabi_attribute 17, 2 @@ -543,5 +1157,5 @@ ; PCS-R9-RESERVE: .eabi_attribute 14, 3 define i32 @f(i64 %z) { - ret i32 0 + ret i32 0 } diff --git a/test/CodeGen/ARM/coalesce-dbgvalue.ll b/test/CodeGen/ARM/coalesce-dbgvalue.ll index 47d81a6..4e5fb5e 100644 --- a/test/CodeGen/ARM/coalesce-dbgvalue.ll +++ b/test/CodeGen/ARM/coalesce-dbgvalue.ll @@ -27,11 +27,11 @@ for.cond1: ; preds = %for.end9, %for.cond for.body2: ; preds = %for.cond1 store i32 %storemerge11, i32* @b, align 4, !dbg !26 - tail call void @llvm.dbg.value(metadata !27, i64 0, metadata !11, metadata !{metadata !"0x102"}), !dbg !28 + tail call void @llvm.dbg.value(metadata i32* null, i64 0, metadata !11, metadata !{!"0x102"}), !dbg !28 %0 = load i64* @a, align 8, !dbg !29 %xor = xor i64 %0, %e.1.ph, !dbg !29 %conv3 = trunc i64 %xor to i32, !dbg !29 - tail call void @llvm.dbg.value(metadata !{i32 %conv3}, i64 0, metadata !10, metadata !{metadata !"0x102"}), !dbg !29 + tail call void @llvm.dbg.value(metadata i32 %conv3, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !29 %tobool4 = icmp eq i32 %conv3, 0, !dbg !29 br i1 %tobool4, label %land.end, label %land.rhs, !dbg !29 @@ -79,33 +79,33 @@ attributes #3 = { nounwind } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} -!0 = metadata !{metadata !"0x11\0012\00clang version 3.4 (trunk 182024) (llvm/trunk 182023)\001\00\000\00\000", metadata !1, metadata !2, metadata !2, metadata !3, metadata !15, metadata !2} ; [ DW_TAG_compile_unit ] [/d/b/pr16110.c] [DW_LANG_C99] -!1 = metadata !{metadata !"pr16110.c", metadata !"/d/b"} -!2 = metadata !{} -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !"0x2e\00pr16110\00pr16110\00\007\000\001\000\006\000\001\007", metadata !1, metadata !5, metadata !6, null, i32 ()* @pr16110, null, null, metadata !9} ; [ DW_TAG_subprogram ] [line 7] [def] [pr16110] -!5 = metadata !{metadata !"0x29", metadata !1} ; [ DW_TAG_file_type ] [/d/b/pr16110.c] -!6 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!7 = metadata !{metadata !8} -!8 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] -!9 = metadata !{metadata !10, metadata !11} -!10 = metadata !{metadata !"0x100\00e\008\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [e] [line 8] -!11 = metadata !{metadata !"0x100\00f\0013\000", metadata !12, metadata !5, metadata !14} ; [ DW_TAG_auto_variable ] [f] [line 13] -!12 = metadata !{metadata !"0xb\0012\000\002", metadata !1, metadata !13} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] -!13 = metadata !{metadata !"0xb\0012\000\001", metadata !1, metadata !4} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] -!14 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, null, metadata !8} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from int] -!15 = metadata !{metadata !16, metadata !18, metadata !19, metadata !20} -!16 = metadata !{metadata !"0x34\00a\00a\00\001\000\001", null, metadata !5, metadata !17, i64* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def] -!17 = metadata !{metadata !"0x24\00long long int\000\0064\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [long long int] [line 0, size 64, align 32, offset 0, enc DW_ATE_signed] -!18 = metadata !{metadata !"0x34\00b\00b\00\002\000\001", null, metadata !5, metadata !8, i32* @b, null} ; [ DW_TAG_variable ] [b] [line 2] [def] -!19 = metadata !{metadata !"0x34\00c\00c\00\003\000\001", null, metadata !5, metadata !8, i32* @c, null} ; [ DW_TAG_variable ] [c] [line 3] [def] -!20 = metadata !{metadata !"0x34\00d\00d\00\004\000\001", null, metadata !5, metadata !8, i32* @d, null} ; [ DW_TAG_variable ] [d] [line 4] [def] -!21 = metadata !{i32 10, i32 0, metadata !22, null} -!22 = metadata !{metadata !"0xb\0010\000\000", metadata !1, metadata !4} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] -!26 = metadata !{i32 12, i32 0, metadata !13, null} -!27 = metadata !{i32* null} -!28 = metadata !{i32 13, i32 0, metadata !12, null} -!29 = metadata !{i32 14, i32 0, metadata !12, null} -!31 = metadata !{i32 16, i32 0, metadata !4, null} -!32 = metadata !{i32 18, i32 0, metadata !4, null} -!33 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x11\0012\00clang version 3.4 (trunk 182024) (llvm/trunk 182023)\001\00\000\00\000", !1, !2, !2, !3, !15, !2} ; [ DW_TAG_compile_unit ] [/d/b/pr16110.c] [DW_LANG_C99] +!1 = !{!"pr16110.c", !"/d/b"} +!2 = !{} +!3 = !{!4} +!4 = !{!"0x2e\00pr16110\00pr16110\00\007\000\001\000\006\000\001\007", !1, !5, !6, null, i32 ()* @pr16110, null, null, !9} ; [ DW_TAG_subprogram ] [line 7] [def] [pr16110] +!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/d/b/pr16110.c] +!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = !{!8} +!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = !{!10, !11} +!10 = !{!"0x100\00e\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [e] [line 8] +!11 = !{!"0x100\00f\0013\000", !12, !5, !14} ; [ DW_TAG_auto_variable ] [f] [line 13] +!12 = !{!"0xb\0012\000\002", !1, !13} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] +!13 = !{!"0xb\0012\000\001", !1, !4} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] +!14 = !{!"0xf\00\000\0032\0032\000\000", null, null, !8} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from int] +!15 = !{!16, !18, !19, !20} +!16 = !{!"0x34\00a\00a\00\001\000\001", null, !5, !17, i64* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def] +!17 = !{!"0x24\00long long int\000\0064\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [long long int] [line 0, size 64, align 32, offset 0, enc DW_ATE_signed] +!18 = !{!"0x34\00b\00b\00\002\000\001", null, !5, !8, i32* @b, null} ; [ DW_TAG_variable ] [b] [line 2] [def] +!19 = !{!"0x34\00c\00c\00\003\000\001", null, !5, !8, i32* @c, null} ; [ DW_TAG_variable ] [c] [line 3] [def] +!20 = !{!"0x34\00d\00d\00\004\000\001", null, !5, !8, i32* @d, null} ; [ DW_TAG_variable ] [d] [line 4] [def] +!21 = !MDLocation(line: 10, scope: !22) +!22 = !{!"0xb\0010\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] +!26 = !MDLocation(line: 12, scope: !13) +!27 = !{i32* null} +!28 = !MDLocation(line: 13, scope: !12) +!29 = !MDLocation(line: 14, scope: !12) +!31 = !MDLocation(line: 16, scope: !4) +!32 = !MDLocation(line: 18, scope: !4) +!33 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/coalesce-subregs.ll b/test/CodeGen/ARM/coalesce-subregs.ll index e7bd5f4..e4e3315 100644 --- a/test/CodeGen/ARM/coalesce-subregs.ll +++ b/test/CodeGen/ARM/coalesce-subregs.ll @@ -293,7 +293,6 @@ bb: ; CHECK: adjustCopiesBackFrom ; The shuffle in if.else3 must be preserved even though adjustCopiesBackFrom ; is tempted to remove it. -; CHECK: %if.else3 ; CHECK: vorr d define internal void @adjustCopiesBackFrom(<2 x i64>* noalias nocapture sret %agg.result, <2 x i64> %in) { entry: diff --git a/test/CodeGen/ARM/crc32.ll b/test/CodeGen/ARM/crc32.ll new file mode 100644 index 0000000..cc94330 --- /dev/null +++ b/test/CodeGen/ARM/crc32.ll @@ -0,0 +1,58 @@ +; RUN: llc -mtriple=thumbv8 -o - %s | FileCheck %s + +define i32 @test_crc32b(i32 %cur, i8 %next) { +; CHECK-LABEL: test_crc32b: +; CHECK: crc32b r0, r0, r1 + %bits = zext i8 %next to i32 + %val = call i32 @llvm.arm.crc32b(i32 %cur, i32 %bits) + ret i32 %val +} + +define i32 @test_crc32h(i32 %cur, i16 %next) { +; CHECK-LABEL: test_crc32h: +; CHECK: crc32h r0, r0, r1 + %bits = zext i16 %next to i32 + %val = call i32 @llvm.arm.crc32h(i32 %cur, i32 %bits) + ret i32 %val +} + +define i32 @test_crc32w(i32 %cur, i32 %next) { +; CHECK-LABEL: test_crc32w: +; CHECK: crc32w r0, r0, r1 + %val = call i32 @llvm.arm.crc32w(i32 %cur, i32 %next) + ret i32 %val +} + +define i32 @test_crc32cb(i32 %cur, i8 %next) { +; CHECK-LABEL: test_crc32cb: +; CHECK: crc32cb r0, r0, r1 + %bits = zext i8 %next to i32 + %val = call i32 @llvm.arm.crc32cb(i32 %cur, i32 %bits) + ret i32 %val +} + +define i32 @test_crc32ch(i32 %cur, i16 %next) { +; CHECK-LABEL: test_crc32ch: +; CHECK: crc32ch r0, r0, r1 + %bits = zext i16 %next to i32 + %val = call i32 @llvm.arm.crc32ch(i32 %cur, i32 %bits) + ret i32 %val +} + +define i32 @test_crc32cw(i32 %cur, i32 %next) { +; CHECK-LABEL: test_crc32cw: +; CHECK: crc32cw r0, r0, r1 + %val = call i32 @llvm.arm.crc32cw(i32 %cur, i32 %next) + ret i32 %val +} + + +declare i32 @llvm.arm.crc32b(i32, i32) +declare i32 @llvm.arm.crc32h(i32, i32) +declare i32 @llvm.arm.crc32w(i32, i32) +declare i32 @llvm.arm.crc32x(i32, i64) + +declare i32 @llvm.arm.crc32cb(i32, i32) +declare i32 @llvm.arm.crc32ch(i32, i32) +declare i32 @llvm.arm.crc32cw(i32, i32) +declare i32 @llvm.arm.crc32cx(i32, i64) diff --git a/test/CodeGen/ARM/cse-ldrlit.ll b/test/CodeGen/ARM/cse-ldrlit.ll index ea8c0ca..3f5d4c2 100644 --- a/test/CodeGen/ARM/cse-ldrlit.ll +++ b/test/CodeGen/ARM/cse-ldrlit.ll @@ -33,8 +33,8 @@ false: ; CHECK-ARM-PIC-LABEL: foo: ; CHECK-ARM-PIC: ldr [[VAR_OFFSET:r[0-9]+]], LCPI0_0 ; CHECK-ARM-PIC: LPC0_0: -; CHECK-ARM-PIC-NEXT: ldr r0, [pc, [[VAR_OFFSET]]] -; CHECK-ARM-PIC: ldr {{r[1-9][0-9]?}}, [r0, #4] +; CHECK-ARM-PIC-NEXT: add r0, pc, [[VAR_OFFSET]] +; CHECK-ARM-PIC: ldr {{r[0-9]+}}, [r0, #4] ; CHECK-ARM-PIC: LCPI0_0: ; CHECK-ARM-PIC-NEXT: .long _var-(LPC0_0+8) diff --git a/test/CodeGen/ARM/cse-libcalls.ll b/test/CodeGen/ARM/cse-libcalls.ll index 62b9e43..4f5b759 100644 --- a/test/CodeGen/ARM/cse-libcalls.ll +++ b/test/CodeGen/ARM/cse-libcalls.ll @@ -1,9 +1,13 @@ -; RUN: llc < %s -march=arm | grep "bl.*__ltdf" | count 1 +; RUN: llc < %s -march=arm | FileCheck %s + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" ; Without CSE of libcalls, there are two calls in the output instead of one. +; CHECK: bl ___ltdf +; CHECK-NOT: bl ___ltdf + define double @u_f_nonbon(double %lambda) nounwind { entry: %tmp19.i.i = load double* null, align 4 ; [#uses=2] diff --git a/test/CodeGen/ARM/dagcombine-concatvector.ll b/test/CodeGen/ARM/dagcombine-concatvector.ll index 62ed87f..80ef2ab 100644 --- a/test/CodeGen/ARM/dagcombine-concatvector.ll +++ b/test/CodeGen/ARM/dagcombine-concatvector.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 -mcpu=generic | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE -; RUN: llc < %s -mtriple=thumbeb -mattr=v7,neon | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE +; RUN: llc < %s -mtriple=thumbeb -target-abi apcs -mattr=v7,neon | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE ; PR15525 ; CHECK-LABEL: test1: diff --git a/test/CodeGen/ARM/debug-frame-vararg.ll b/test/CodeGen/ARM/debug-frame-vararg.ll index ffc1a6a..65be2db 100644 --- a/test/CodeGen/ARM/debug-frame-vararg.ll +++ b/test/CodeGen/ARM/debug-frame-vararg.ll @@ -25,40 +25,40 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} -!0 = metadata !{metadata !"0x11\0012\00clang version 3.5 \000\00\000\00\000", metadata !1, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2} ; [ DW_TAG_compile_unit ] [/tmp/var.c] [DW_LANG_C99] -!1 = metadata !{metadata !"var.c", metadata !"/tmp"} -!2 = metadata !{} -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !"0x2e\00sum\00sum\00\005\000\001\000\006\00256\000\005", metadata !1, metadata !5, metadata !6, null, i32 (i32, ...)* @sum, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 5] [def] [sum] -!5 = metadata !{metadata !"0x29", metadata !1} ; [ DW_TAG_file_type ] [/tmp/var.c] -!6 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!7 = metadata !{metadata !8, metadata !8} -!8 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] -!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} -!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} -!11 = metadata !{metadata !"clang version 3.5 "} -!12 = metadata !{metadata !"0x101\00count\0016777221\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [count] [line 5] -!13 = metadata !{i32 5, i32 0, metadata !4, null} -!14 = metadata !{metadata !"0x100\00vl\006\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [vl] [line 6] -!15 = metadata !{metadata !"0x16\00va_list\0030\000\000\000\000", metadata !16, null, metadata !17} ; [ DW_TAG_typedef ] [va_list] [line 30, size 0, align 0, offset 0] [from __builtin_va_list] -!16 = metadata !{metadata !"/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", metadata !"/tmp"} -!17 = metadata !{metadata !"0x16\00__builtin_va_list\006\000\000\000\000", metadata !1, null, metadata !18} ; [ DW_TAG_typedef ] [__builtin_va_list] [line 6, size 0, align 0, offset 0] [from __va_list] -!18 = metadata !{metadata !"0x13\00__va_list\006\0032\0032\000\000\000", metadata !1, null, null, metadata !19, null, null, null} ; [ DW_TAG_structure_type ] [__va_list] [line 6, size 32, align 32, offset 0] [def] [from ] -!19 = metadata !{metadata !20} -!20 = metadata !{metadata !"0xd\00__ap\006\0032\0032\000\000", metadata !1, metadata !18, metadata !21} ; [ DW_TAG_member ] [__ap] [line 6, size 32, align 32, offset 0] [from ] -!21 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from ] -!22 = metadata !{i32 6, i32 0, metadata !4, null} -!23 = metadata !{i32 7, i32 0, metadata !4, null} -!24 = metadata !{metadata !"0x100\00sum\008\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [sum] [line 8] -!25 = metadata !{i32 8, i32 0, metadata !4, null} -!26 = metadata !{metadata !"0x100\00i\009\000", metadata !27, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 9] -!27 = metadata !{metadata !"0xb\009\000\000", metadata !1, metadata !4} ; [ DW_TAG_lexical_block ] [/tmp/var.c] -!28 = metadata !{i32 9, i32 0, metadata !27, null} -!29 = metadata !{i32 10, i32 0, metadata !30, null} -!30 = metadata !{metadata !"0xb\009\000\001", metadata !1, metadata !27} ; [ DW_TAG_lexical_block ] [/tmp/var.c] -!31 = metadata !{i32 11, i32 0, metadata !30, null} -!32 = metadata !{i32 12, i32 0, metadata !4, null} -!33 = metadata !{i32 13, i32 0, metadata !4, null} +!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/var.c] [DW_LANG_C99] +!1 = !{!"var.c", !"/tmp"} +!2 = !{} +!3 = !{!4} +!4 = !{!"0x2e\00sum\00sum\00\005\000\001\000\006\00256\000\005", !1, !5, !6, null, i32 (i32, ...)* @sum, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [sum] +!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/tmp/var.c] +!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = !{!8, !8} +!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = !{i32 2, !"Dwarf Version", i32 4} +!10 = !{i32 1, !"Debug Info Version", i32 2} +!11 = !{!"clang version 3.5 "} +!12 = !{!"0x101\00count\0016777221\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [count] [line 5] +!13 = !MDLocation(line: 5, scope: !4) +!14 = !{!"0x100\00vl\006\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [vl] [line 6] +!15 = !{!"0x16\00va_list\0030\000\000\000\000", !16, null, !17} ; [ DW_TAG_typedef ] [va_list] [line 30, size 0, align 0, offset 0] [from __builtin_va_list] +!16 = !{!"/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", !"/tmp"} +!17 = !{!"0x16\00__builtin_va_list\006\000\000\000\000", !1, null, !18} ; [ DW_TAG_typedef ] [__builtin_va_list] [line 6, size 0, align 0, offset 0] [from __va_list] +!18 = !{!"0x13\00__va_list\006\0032\0032\000\000\000", !1, null, null, !19, null, null, null} ; [ DW_TAG_structure_type ] [__va_list] [line 6, size 32, align 32, offset 0] [def] [from ] +!19 = !{!20} +!20 = !{!"0xd\00__ap\006\0032\0032\000\000", !1, !18, !21} ; [ DW_TAG_member ] [__ap] [line 6, size 32, align 32, offset 0] [from ] +!21 = !{!"0xf\00\000\0032\0032\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from ] +!22 = !MDLocation(line: 6, scope: !4) +!23 = !MDLocation(line: 7, scope: !4) +!24 = !{!"0x100\00sum\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [sum] [line 8] +!25 = !MDLocation(line: 8, scope: !4) +!26 = !{!"0x100\00i\009\000", !27, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 9] +!27 = !{!"0xb\009\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/var.c] +!28 = !MDLocation(line: 9, scope: !27) +!29 = !MDLocation(line: 10, scope: !30) +!30 = !{!"0xb\009\000\001", !1, !27} ; [ DW_TAG_lexical_block ] [/tmp/var.c] +!31 = !MDLocation(line: 11, scope: !30) +!32 = !MDLocation(line: 12, scope: !4) +!33 = !MDLocation(line: 13, scope: !4) ; CHECK-FP-LABEL: sum ; CHECK-FP: .cfi_startproc @@ -88,24 +88,22 @@ ; CHECK-THUMB-FP: .cfi_startproc ; CHECK-THUMB-FP: sub sp, #16 ; CHECK-THUMB-FP: .cfi_def_cfa_offset 16 -; CHECK-THUMB-FP: push {r4, r5, r7, lr} -; CHECK-THUMB-FP: .cfi_def_cfa_offset 32 +; CHECK-THUMB-FP: push {r4, lr} +; CHECK-THUMB-FP: .cfi_def_cfa_offset 24 ; CHECK-THUMB-FP: .cfi_offset lr, -20 -; CHECK-THUMB-FP: .cfi_offset r7, -24 -; CHECK-THUMB-FP: .cfi_offset r5, -28 -; CHECK-THUMB-FP: .cfi_offset r4, -32 +; CHECK-THUMB-FP: .cfi_offset r4, -24 ; CHECK-THUMB-FP: sub sp, #8 -; CHECK-THUMB-FP: .cfi_def_cfa_offset 40 +; CHECK-THUMB-FP: .cfi_def_cfa_offset 32 ; CHECK-THUMB-FP-ELIM-LABEL: sum ; CHECK-THUMB-FP-ELIM: .cfi_startproc ; CHECK-THUMB-FP-ELIM: sub sp, #16 ; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 16 -; CHECK-THUMB-FP-ELIM: push {r4, r5, r7, lr} +; CHECK-THUMB-FP-ELIM: push {r4, r6, r7, lr} ; CHECK-THUMB-FP-ELIM: .cfi_def_cfa_offset 32 ; CHECK-THUMB-FP-ELIM: .cfi_offset lr, -20 ; CHECK-THUMB-FP-ELIM: .cfi_offset r7, -24 -; CHECK-THUMB-FP-ELIM: .cfi_offset r5, -28 +; CHECK-THUMB-FP-ELIM: .cfi_offset r6, -28 ; CHECK-THUMB-FP-ELIM: .cfi_offset r4, -32 ; CHECK-THUMB-FP-ELIM: add r7, sp, #8 ; CHECK-THUMB-FP-ELIM: .cfi_def_cfa r7, 24 diff --git a/test/CodeGen/ARM/debug-frame.ll b/test/CodeGen/ARM/debug-frame.ll index c6243ec..16e2c4c 100644 --- a/test/CodeGen/ARM/debug-frame.ll +++ b/test/CodeGen/ARM/debug-frame.ll @@ -128,41 +128,41 @@ declare void @_ZSt9terminatev() !llvm.module.flags = !{!10, !11} !llvm.ident = !{!12} -!0 = metadata !{metadata !"0x11\004\00clang version 3.5 \000\00\000\00\000", metadata !1, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2} ; [ DW_TAG_compile_unit ] [/tmp/exp.cpp] [DW_LANG_C_plus_plus] -!1 = metadata !{metadata !"exp.cpp", metadata !"/tmp"} -!2 = metadata !{} -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !"0x2e\00test\00test\00_Z4testiiiiiddddd\004\000\001\000\006\00256\000\005", metadata !1, metadata !5, metadata !6, null, void (i32, i32, i32, i32, i32, double, double, double, double, double)* @_Z4testiiiiiddddd, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 4] [def] [scope 5] [test] -!5 = metadata !{metadata !"0x29", metadata !1} ; [ DW_TAG_file_type ] [/tmp/exp.cpp] -!6 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!7 = metadata !{null, metadata !8, metadata !8, metadata !8, metadata !8, metadata !8, metadata !9, metadata !9, metadata !9, metadata !9, metadata !9} -!8 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] -!9 = metadata !{metadata !"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float] -!10 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} -!11 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} -!12 = metadata !{metadata !"clang version 3.5 "} -!13 = metadata !{metadata !"0x101\00a\0016777220\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [a] [line 4] -!14 = metadata !{i32 4, i32 0, metadata !4, null} -!15 = metadata !{metadata !"0x101\00b\0033554436\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [b] [line 4] -!16 = metadata !{metadata !"0x101\00c\0050331652\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [c] [line 4] -!17 = metadata !{metadata !"0x101\00d\0067108868\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [d] [line 4] -!18 = metadata !{metadata !"0x101\00e\0083886084\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [e] [line 4] -!19 = metadata !{metadata !"0x101\00m\00100663301\000", metadata !4, metadata !5, metadata !9} ; [ DW_TAG_arg_variable ] [m] [line 5] -!20 = metadata !{i32 5, i32 0, metadata !4, null} -!21 = metadata !{metadata !"0x101\00n\00117440517\000", metadata !4, metadata !5, metadata !9} ; [ DW_TAG_arg_variable ] [n] [line 5] -!22 = metadata !{metadata !"0x101\00p\00134217733\000", metadata !4, metadata !5, metadata !9} ; [ DW_TAG_arg_variable ] [p] [line 5] -!23 = metadata !{metadata !"0x101\00q\00150994949\000", metadata !4, metadata !5, metadata !9} ; [ DW_TAG_arg_variable ] [q] [line 5] -!24 = metadata !{metadata !"0x101\00r\00167772165\000", metadata !4, metadata !5, metadata !9} ; [ DW_TAG_arg_variable ] [r] [line 5] -!25 = metadata !{i32 7, i32 0, metadata !26, null} -!26 = metadata !{metadata !"0xb\006\000\000", metadata !1, metadata !4} ; [ DW_TAG_lexical_block ] [/tmp/exp.cpp] -!27 = metadata !{i32 8, i32 0, metadata !26, null} -!28 = metadata !{i32 11, i32 0, metadata !26, null} -!29 = metadata !{i32 9, i32 0, metadata !30, null} -!30 = metadata !{metadata !"0xb\008\000\001", metadata !1, metadata !4} ; [ DW_TAG_lexical_block ] [/tmp/exp.cpp] -!31 = metadata !{i32 10, i32 0, metadata !30, null} -!32 = metadata !{i32 10, i32 0, metadata !4, null} -!33 = metadata !{i32 11, i32 0, metadata !4, null} -!34 = metadata !{i32 11, i32 0, metadata !30, null} +!0 = !{!"0x11\004\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/exp.cpp] [DW_LANG_C_plus_plus] +!1 = !{!"exp.cpp", !"/tmp"} +!2 = !{} +!3 = !{!4} +!4 = !{!"0x2e\00test\00test\00_Z4testiiiiiddddd\004\000\001\000\006\00256\000\005", !1, !5, !6, null, void (i32, i32, i32, i32, i32, double, double, double, double, double)* @_Z4testiiiiiddddd, null, null, !2} ; [ DW_TAG_subprogram ] [line 4] [def] [scope 5] [test] +!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/tmp/exp.cpp] +!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = !{null, !8, !8, !8, !8, !8, !9, !9, !9, !9, !9} +!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = !{!"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float] +!10 = !{i32 2, !"Dwarf Version", i32 4} +!11 = !{i32 1, !"Debug Info Version", i32 2} +!12 = !{!"clang version 3.5 "} +!13 = !{!"0x101\00a\0016777220\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [a] [line 4] +!14 = !MDLocation(line: 4, scope: !4) +!15 = !{!"0x101\00b\0033554436\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [b] [line 4] +!16 = !{!"0x101\00c\0050331652\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [c] [line 4] +!17 = !{!"0x101\00d\0067108868\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [d] [line 4] +!18 = !{!"0x101\00e\0083886084\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [e] [line 4] +!19 = !{!"0x101\00m\00100663301\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [m] [line 5] +!20 = !MDLocation(line: 5, scope: !4) +!21 = !{!"0x101\00n\00117440517\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [n] [line 5] +!22 = !{!"0x101\00p\00134217733\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [p] [line 5] +!23 = !{!"0x101\00q\00150994949\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [q] [line 5] +!24 = !{!"0x101\00r\00167772165\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [r] [line 5] +!25 = !MDLocation(line: 7, scope: !26) +!26 = !{!"0xb\006\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/exp.cpp] +!27 = !MDLocation(line: 8, scope: !26) +!28 = !MDLocation(line: 11, scope: !26) +!29 = !MDLocation(line: 9, scope: !30) +!30 = !{!"0xb\008\000\001", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/exp.cpp] +!31 = !MDLocation(line: 10, scope: !30) +!32 = !MDLocation(line: 10, scope: !4) +!33 = !MDLocation(line: 11, scope: !4) +!34 = !MDLocation(line: 11, scope: !30) ; CHECK-FP-LABEL: _Z4testiiiiiddddd: ; CHECK-FP: .cfi_startproc diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll index 34e9938..8679589 100644 --- a/test/CodeGen/ARM/debug-info-arg.ll +++ b/test/CodeGen/ARM/debug-info-arg.ll @@ -7,13 +7,13 @@ target triple = "thumbv7-apple-ios" %struct.tag_s = type { i32, i32, i32 } define void @foo(%struct.tag_s* nocapture %this, %struct.tag_s* %c, i64 %x, i64 %y, %struct.tag_s* nocapture %ptr1, %struct.tag_s* nocapture %ptr2) nounwind ssp { - tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %this}, i64 0, metadata !5, metadata !{metadata !"0x102"}), !dbg !20 - tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %c}, i64 0, metadata !13, metadata !{metadata !"0x102"}), !dbg !21 - tail call void @llvm.dbg.value(metadata !{i64 %x}, i64 0, metadata !14, metadata !{metadata !"0x102"}), !dbg !22 - tail call void @llvm.dbg.value(metadata !{i64 %y}, i64 0, metadata !17, metadata !{metadata !"0x102"}), !dbg !23 + tail call void @llvm.dbg.value(metadata %struct.tag_s* %this, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !20 + tail call void @llvm.dbg.value(metadata %struct.tag_s* %c, i64 0, metadata !13, metadata !{!"0x102"}), !dbg !21 + tail call void @llvm.dbg.value(metadata i64 %x, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !22 + tail call void @llvm.dbg.value(metadata i64 %y, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !23 ;CHECK: @DEBUG_VALUE: foo:y <- [R7+8] - tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr1}, i64 0, metadata !18, metadata !{metadata !"0x102"}), !dbg !24 - tail call void @llvm.dbg.value(metadata !{%struct.tag_s* %ptr2}, i64 0, metadata !19, metadata !{metadata !"0x102"}), !dbg !25 + tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr1, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !24 + tail call void @llvm.dbg.value(metadata %struct.tag_s* %ptr2, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !25 %1 = icmp eq %struct.tag_s* %c, null, !dbg !26 br i1 %1, label %3, label %2, !dbg !26 @@ -32,37 +32,37 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} -!0 = metadata !{metadata !"0x11\0012\00Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)\001\00\000\00\001", metadata !32, metadata !4, metadata !4, metadata !30, null, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{metadata !"0x2e\00foo\00foo\00\0011\000\001\000\006\00256\001\0011", metadata !2, metadata !2, metadata !3, null, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, metadata !31} ; [ DW_TAG_subprogram ] [line 11] [def] [foo] -!2 = metadata !{metadata !"0x29", metadata !32} ; [ DW_TAG_file_type ] -!3 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !32, metadata !2, null, metadata !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!4 = metadata !{null} -!5 = metadata !{metadata !"0x101\00this\0016777227\000", metadata !1, metadata !2, metadata !6} ; [ DW_TAG_arg_variable ] -!6 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !0, metadata !7} ; [ DW_TAG_pointer_type ] -!7 = metadata !{metadata !"0x13\00tag_s\005\0096\0032\000\000\000", metadata !32, metadata !0, null, metadata !8, null, null, null} ; [ DW_TAG_structure_type ] [tag_s] [line 5, size 96, align 32, offset 0] [def] [from ] -!8 = metadata !{metadata !9, metadata !11, metadata !12} -!9 = metadata !{metadata !"0xd\00x\006\0032\0032\000\000", metadata !32, metadata !7, metadata !10} ; [ DW_TAG_member ] -!10 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, metadata !0} ; [ DW_TAG_base_type ] -!11 = metadata !{metadata !"0xd\00y\007\0032\0032\0032\000", metadata !32, metadata !7, metadata !10} ; [ DW_TAG_member ] -!12 = metadata !{metadata !"0xd\00z\008\0032\0032\0064\000", metadata !32, metadata !7, metadata !10} ; [ DW_TAG_member ] -!13 = metadata !{metadata !"0x101\00c\0033554443\000", metadata !1, metadata !2, metadata !6} ; [ DW_TAG_arg_variable ] -!14 = metadata !{metadata !"0x101\00x\0050331659\000", metadata !1, metadata !2, metadata !15} ; [ DW_TAG_arg_variable ] -!15 = metadata !{metadata !"0x16\00UInt64\001\000\000\000\000", metadata !32, metadata !0, metadata !16} ; [ DW_TAG_typedef ] -!16 = metadata !{metadata !"0x24\00long long unsigned int\000\0064\0032\000\000\007", null, metadata !0} ; [ DW_TAG_base_type ] -!17 = metadata !{metadata !"0x101\00y\0067108875\000", metadata !1, metadata !2, metadata !15} ; [ DW_TAG_arg_variable ] -!18 = metadata !{metadata !"0x101\00ptr1\0083886091\000", metadata !1, metadata !2, metadata !6} ; [ DW_TAG_arg_variable ] -!19 = metadata !{metadata !"0x101\00ptr2\00100663307\000", metadata !1, metadata !2, metadata !6} ; [ DW_TAG_arg_variable ] -!20 = metadata !{i32 11, i32 24, metadata !1, null} -!21 = metadata !{i32 11, i32 44, metadata !1, null} -!22 = metadata !{i32 11, i32 54, metadata !1, null} -!23 = metadata !{i32 11, i32 64, metadata !1, null} -!24 = metadata !{i32 11, i32 81, metadata !1, null} -!25 = metadata !{i32 11, i32 101, metadata !1, null} -!26 = metadata !{i32 12, i32 3, metadata !27, null} -!27 = metadata !{metadata !"0xb\0011\00107\000", metadata !2, metadata !1} ; [ DW_TAG_lexical_block ] -!28 = metadata !{i32 13, i32 5, metadata !27, null} -!29 = metadata !{i32 14, i32 1, metadata !27, null} -!30 = metadata !{metadata !1} -!31 = metadata !{metadata !5, metadata !13, metadata !14, metadata !17, metadata !18, metadata!19} -!32 = metadata !{metadata !"one.c", metadata !"/Volumes/Athwagate/R10048772"} -!33 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x11\0012\00Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)\001\00\000\00\001", !32, !4, !4, !30, null, null} ; [ DW_TAG_compile_unit ] +!1 = !{!"0x2e\00foo\00foo\00\0011\000\001\000\006\00256\001\0011", !2, !2, !3, null, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, !31} ; [ DW_TAG_subprogram ] [line 11] [def] [foo] +!2 = !{!"0x29", !32} ; [ DW_TAG_file_type ] +!3 = !{!"0x15\00\000\000\000\000\000\000", !32, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !{null} +!5 = !{!"0x101\00this\0016777227\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] +!6 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !7} ; [ DW_TAG_pointer_type ] +!7 = !{!"0x13\00tag_s\005\0096\0032\000\000\000", !32, !0, null, !8, null, null, null} ; [ DW_TAG_structure_type ] [tag_s] [line 5, size 96, align 32, offset 0] [def] [from ] +!8 = !{!9, !11, !12} +!9 = !{!"0xd\00x\006\0032\0032\000\000", !32, !7, !10} ; [ DW_TAG_member ] +!10 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !0} ; [ DW_TAG_base_type ] +!11 = !{!"0xd\00y\007\0032\0032\0032\000", !32, !7, !10} ; [ DW_TAG_member ] +!12 = !{!"0xd\00z\008\0032\0032\0064\000", !32, !7, !10} ; [ DW_TAG_member ] +!13 = !{!"0x101\00c\0033554443\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] +!14 = !{!"0x101\00x\0050331659\000", !1, !2, !15} ; [ DW_TAG_arg_variable ] +!15 = !{!"0x16\00UInt64\001\000\000\000\000", !32, !0, !16} ; [ DW_TAG_typedef ] +!16 = !{!"0x24\00long long unsigned int\000\0064\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ] +!17 = !{!"0x101\00y\0067108875\000", !1, !2, !15} ; [ DW_TAG_arg_variable ] +!18 = !{!"0x101\00ptr1\0083886091\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] +!19 = !{!"0x101\00ptr2\00100663307\000", !1, !2, !6} ; [ DW_TAG_arg_variable ] +!20 = !MDLocation(line: 11, column: 24, scope: !1) +!21 = !MDLocation(line: 11, column: 44, scope: !1) +!22 = !MDLocation(line: 11, column: 54, scope: !1) +!23 = !MDLocation(line: 11, column: 64, scope: !1) +!24 = !MDLocation(line: 11, column: 81, scope: !1) +!25 = !MDLocation(line: 11, column: 101, scope: !1) +!26 = !MDLocation(line: 12, column: 3, scope: !27) +!27 = !{!"0xb\0011\00107\000", !2, !1} ; [ DW_TAG_lexical_block ] +!28 = !MDLocation(line: 13, column: 5, scope: !27) +!29 = !MDLocation(line: 14, column: 1, scope: !27) +!30 = !{!1} +!31 = !{!5, !13, !14, !17, !18, !19} +!32 = !{!"one.c", !"/Volumes/Athwagate/R10048772"} +!33 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll index 3623927..3bf6ad9 100644 --- a/test/CodeGen/ARM/debug-info-blocks.ll +++ b/test/CodeGen/ARM/debug-info-blocks.ll @@ -31,22 +31,22 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load %1 = alloca %0*, align 4 %bounds = alloca %struct.CR, align 4 %data = alloca %struct.CR, align 4 - call void @llvm.dbg.value(metadata !{i8* %.block_descriptor}, i64 0, metadata !27, metadata !{metadata !"0x102"}), !dbg !129 + call void @llvm.dbg.value(metadata i8* %.block_descriptor, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !129 store %0* %loadedMydata, %0** %1, align 4 - call void @llvm.dbg.declare(metadata !{%0** %1}, metadata !130, metadata !{metadata !"0x102"}), !dbg !131 + call void @llvm.dbg.declare(metadata %0** %1, metadata !130, metadata !{!"0x102"}), !dbg !131 %2 = bitcast %struct.CR* %bounds to %1* %3 = getelementptr %1* %2, i32 0, i32 0 store [4 x i32] %bounds.coerce0, [4 x i32]* %3 - call void @llvm.dbg.declare(metadata !{%struct.CR* %bounds}, metadata !132, metadata !{metadata !"0x102"}), !dbg !133 + call void @llvm.dbg.declare(metadata %struct.CR* %bounds, metadata !132, metadata !{!"0x102"}), !dbg !133 %4 = bitcast %struct.CR* %data to %1* %5 = getelementptr %1* %4, i32 0, i32 0 store [4 x i32] %data.coerce0, [4 x i32]* %5 - call void @llvm.dbg.declare(metadata !{%struct.CR* %data}, metadata !134, metadata !{metadata !"0x102"}), !dbg !135 + call void @llvm.dbg.declare(metadata %struct.CR* %data, metadata !134, metadata !{!"0x102"}), !dbg !135 %6 = bitcast i8* %.block_descriptor to %2* %7 = getelementptr inbounds %2* %6, i32 0, i32 6 - call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !136, metadata !163), !dbg !137 - call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !138, metadata !164), !dbg !137 - call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !139, metadata !165), !dbg !140 + call void @llvm.dbg.declare(metadata %2* %6, metadata !136, metadata !163), !dbg !137 + call void @llvm.dbg.declare(metadata %2* %6, metadata !138, metadata !164), !dbg !137 + call void @llvm.dbg.declare(metadata %2* %6, metadata !139, metadata !165), !dbg !140 %8 = load %0** %1, align 4, !dbg !141 %9 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_13", !dbg !141 %10 = bitcast %0* %8 to i8*, !dbg !141 @@ -95,169 +95,169 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!162} -!0 = metadata !{metadata !"0x11\0016\00Apple clang version 2.1\000\00\002\00\001", metadata !153, metadata !147, metadata !26, metadata !148, null, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{metadata !"0x4\00\00248\0032\0032\000\000\000", metadata !160, metadata !0, null, metadata !3, null, null, null} ; [ DW_TAG_enumeration_type ] [line 248, size 32, align 32, offset 0] [def] [from ] -!2 = metadata !{metadata !"0x29", metadata !160} ; [ DW_TAG_file_type ] -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !"0x28\00Ver1\000"} ; [ DW_TAG_enumerator ] -!5 = metadata !{metadata !"0x4\00Mode\0079\0032\0032\000\000\000", metadata !160, metadata !0, null, metadata !7, null, null, null} ; [ DW_TAG_enumeration_type ] [Mode] [line 79, size 32, align 32, offset 0] [def] [from ] -!6 = metadata !{metadata !"0x29", metadata !161} ; [ DW_TAG_file_type ] -!7 = metadata !{metadata !8} -!8 = metadata !{metadata !"0x28\00One\000"} ; [ DW_TAG_enumerator ] -!9 = metadata !{metadata !"0x4\00\0015\0032\0032\000\000\000", metadata !149, metadata !0, null, metadata !11, null, null, null} ; [ DW_TAG_enumeration_type ] [line 15, size 32, align 32, offset 0] [def] [from ] -!10 = metadata !{metadata !"0x29", metadata !149} ; [ DW_TAG_file_type ] -!11 = metadata !{metadata !12, metadata !13} -!12 = metadata !{metadata !"0x28\00Unknown\000"} ; [ DW_TAG_enumerator ] -!13 = metadata !{metadata !"0x28\00Known\001"} ; [ DW_TAG_enumerator ] -!14 = metadata !{metadata !"0x4\00\0020\0032\0032\000\000\000", metadata !150, metadata !0, null, metadata !16, null, null, null} ; [ DW_TAG_enumeration_type ] [line 20, size 32, align 32, offset 0] [def] [from ] -!15 = metadata !{metadata !"0x29", metadata !150} ; [ DW_TAG_file_type ] -!16 = metadata !{metadata !17, metadata !18} -!17 = metadata !{metadata !"0x28\00Single\000"} ; [ DW_TAG_enumerator ] -!18 = metadata !{metadata !"0x28\00Double\001"} ; [ DW_TAG_enumerator ] -!19 = metadata !{metadata !"0x4\00\0014\0032\0032\000\000\000", metadata !151, metadata !0, null, metadata !21, null, null, null} ; [ DW_TAG_enumeration_type ] [line 14, size 32, align 32, offset 0] [def] [from ] -!20 = metadata !{metadata !"0x29", metadata !151} ; [ DW_TAG_file_type ] -!21 = metadata !{metadata !22} -!22 = metadata !{metadata !"0x28\00Eleven\000"} ; [ DW_TAG_enumerator ] -!23 = metadata !{metadata !"0x2e\00foobar_func_block_invoke_0\00foobar_func_block_invoke_0\00\00609\001\001\000\006\00256\000\00609", metadata !152, metadata !24, metadata !25, null, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null, null} ; [ DW_TAG_subprogram ] [line 609] [local] [def] [foobar_func_block_invoke_0] -!24 = metadata !{metadata !"0x29", metadata !152} ; [ DW_TAG_file_type ] -!25 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !152, metadata !24, null, metadata !26, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!26 = metadata !{null} -!27 = metadata !{metadata !"0x101\00.block_descriptor\0016777825\0064", metadata !23, metadata !24, metadata !28} ; [ DW_TAG_arg_variable ] -!28 = metadata !{metadata !"0xf\00\000\0032\000\000\000", null, metadata !0, metadata !29} ; [ DW_TAG_pointer_type ] -!29 = metadata !{metadata !"0x13\00__block_literal_14\00609\00256\0032\000\000\000", metadata !152, metadata !24, null, metadata !30, null, null, null} ; [ DW_TAG_structure_type ] [__block_literal_14] [line 609, size 256, align 32, offset 0] [def] [from ] -!30 = metadata !{metadata !31, metadata !33, metadata !35, metadata !36, metadata !37, metadata !48, metadata !89, metadata !124} -!31 = metadata !{metadata !"0xd\00__isa\00609\0032\0032\000\000", metadata !152, metadata !24, metadata !32} ; [ DW_TAG_member ] -!32 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !0, null} ; [ DW_TAG_pointer_type ] -!33 = metadata !{metadata !"0xd\00__flags\00609\0032\0032\0032\000", metadata !152, metadata !24, metadata !34} ; [ DW_TAG_member ] -!34 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, metadata !0} ; [ DW_TAG_base_type ] -!35 = metadata !{metadata !"0xd\00__reserved\00609\0032\0032\0064\000", metadata !152, metadata !24, metadata !34} ; [ DW_TAG_member ] -!36 = metadata !{metadata !"0xd\00__FuncPtr\00609\0032\0032\0096\000", metadata !152, metadata !24, metadata !32} ; [ DW_TAG_member ] -!37 = metadata !{metadata !"0xd\00__descriptor\00609\0032\0032\00128\000", metadata !152, metadata !24, metadata !38} ; [ DW_TAG_member ] -!38 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !0, metadata !39} ; [ DW_TAG_pointer_type ] -!39 = metadata !{metadata !"0x13\00__block_descriptor_withcopydispose\00307\00128\0032\000\000\000", metadata !153, metadata !0, null, metadata !41, null, null, null} ; [ DW_TAG_structure_type ] [__block_descriptor_withcopydispose] [line 307, size 128, align 32, offset 0] [def] [from ] -!40 = metadata !{metadata !"0x29", metadata !153} ; [ DW_TAG_file_type ] -!41 = metadata !{metadata !42, metadata !44, metadata !45, metadata !47} -!42 = metadata !{metadata !"0xd\00reserved\00307\0032\0032\000\000", metadata !153, metadata !40, metadata !43} ; [ DW_TAG_member ] -!43 = metadata !{metadata !"0x24\00long unsigned int\000\0032\0032\000\000\007", null, metadata !0} ; [ DW_TAG_base_type ] -!44 = metadata !{metadata !"0xd\00Size\00307\0032\0032\0032\000", metadata !153, metadata !40, metadata !43} ; [ DW_TAG_member ] -!45 = metadata !{metadata !"0xd\00CopyFuncPtr\00307\0032\0032\0064\000", metadata !153, metadata !40, metadata !46} ; [ DW_TAG_member ] -!46 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !0, metadata !32} ; [ DW_TAG_pointer_type ] -!47 = metadata !{metadata !"0xd\00DestroyFuncPtr\00307\0032\0032\0096\000", metadata !153, metadata !40, metadata !46} ; [ DW_TAG_member ] -!48 = metadata !{metadata !"0xd\00mydata\00609\0032\0032\00160\000", metadata !152, metadata !24, metadata !49} ; [ DW_TAG_member ] -!49 = metadata !{metadata !"0xf\00\000\0032\000\000\000", null, metadata !0, metadata !50} ; [ DW_TAG_pointer_type ] -!50 = metadata !{metadata !"0x13\00\000\00224\000\000\0016\000", metadata !152, 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!{!"0xd\00__FuncPtr\00609\0032\0032\0096\000", !152, !24, !32} ; [ DW_TAG_member ] +!37 = !{!"0xd\00__descriptor\00609\0032\0032\00128\000", !152, !24, !38} ; [ DW_TAG_member ] +!38 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !39} ; [ DW_TAG_pointer_type ] +!39 = !{!"0x13\00__block_descriptor_withcopydispose\00307\00128\0032\000\000\000", !153, !0, null, !41, null, null, null} ; [ DW_TAG_structure_type ] [__block_descriptor_withcopydispose] [line 307, size 128, align 32, offset 0] [def] [from ] +!40 = !{!"0x29", !153} ; [ DW_TAG_file_type ] +!41 = !{!42, !44, !45, !47} +!42 = !{!"0xd\00reserved\00307\0032\0032\000\000", !153, !40, !43} ; [ DW_TAG_member ] +!43 = !{!"0x24\00long unsigned int\000\0032\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ] +!44 = !{!"0xd\00Size\00307\0032\0032\0032\000", !153, !40, !43} ; [ DW_TAG_member ] +!45 = !{!"0xd\00CopyFuncPtr\00307\0032\0032\0064\000", !153, !40, !46} ; [ DW_TAG_member ] +!46 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !32} ; [ DW_TAG_pointer_type ] +!47 = !{!"0xd\00DestroyFuncPtr\00307\0032\0032\0096\000", !153, !40, !46} ; [ DW_TAG_member ] +!48 = !{!"0xd\00mydata\00609\0032\0032\00160\000", !152, !24, !49} ; [ DW_TAG_member ] +!49 = !{!"0xf\00\000\0032\000\000\000", null, !0, !50} ; [ DW_TAG_pointer_type ] +!50 = !{!"0x13\00\000\00224\000\000\0016\000", !152, !24, null, !51, null, null, null} ; [ DW_TAG_structure_type ] [line 0, size 224, align 0, offset 0] [def] [from ] +!51 = !{!52, !53, !54, !55, !56, !57, !58} +!52 = !{!"0xd\00__isa\000\0032\0032\000\000", !152, !24, !32} ; [ DW_TAG_member ] +!53 = !{!"0xd\00__forwarding\000\0032\0032\0032\000", !152, !24, !32} ; [ DW_TAG_member ] +!54 = !{!"0xd\00__flags\000\0032\0032\0064\000", !152, !24, !34} ; [ DW_TAG_member ] +!55 = !{!"0xd\00__size\000\0032\0032\0096\000", !152, !24, !34} ; [ DW_TAG_member ] +!56 = !{!"0xd\00__copy_helper\000\0032\0032\00128\000", !152, !24, !32} ; [ DW_TAG_member ] +!57 = !{!"0xd\00__destroy_helper\000\0032\0032\00160\000", !152, !24, !32} ; [ DW_TAG_member ] +!58 = !{!"0xd\00mydata\000\0032\0032\00192\000", !152, !24, !59} ; [ DW_TAG_member ] +!59 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !60} ; [ DW_TAG_pointer_type ] +!60 = !{!"0x13\00UIMydata\0026\00128\0032\000\000\0016", !154, !24, null, !62, null, null, null} ; [ DW_TAG_structure_type ] [UIMydata] [line 26, size 128, align 32, offset 0] [def] [from ] +!61 = !{!"0x29", !154} ; [ DW_TAG_file_type ] +!62 = !{!63, !71, !75, !79} +!63 = !{!"0x1c\00\000\000\000\000\000", !60, null, !64} ; [ DW_TAG_inheritance ] +!64 = !{!"0x13\00NSO\0066\0032\0032\000\000\0016", !155, !40, null, !66, null, null, null} ; [ DW_TAG_structure_type ] [NSO] [line 66, size 32, align 32, offset 0] [def] [from ] +!65 = !{!"0x29", !155} ; [ DW_TAG_file_type ] +!66 = !{!67} +!67 = !{!"0xd\00isa\0067\0032\0032\000\002", !155, !65, !68, !"", !"", !"", i32 0} ; [ DW_TAG_member ] +!68 = !{!"0x16\00Class\00197\000\000\000\000", !153, !0, !69} ; [ DW_TAG_typedef ] +!69 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !70} ; [ DW_TAG_pointer_type ] +!70 = !{!"0x13\00objc_class\000\000\000\000\004\000", !153, !0, null, null, null, null, null} ; [ DW_TAG_structure_type ] [objc_class] [line 0, size 0, align 0, offset 0] [decl] [from ] +!71 = !{!"0xd\00_mydataRef\0028\0032\0032\0032\000", !154, !61, !72, !"", !"", !"", i32 0} ; [ DW_TAG_member ] +!72 = !{!"0x16\00CFTypeRef\00313\000\000\000\000", !152, !0, !73} ; [ DW_TAG_typedef ] +!73 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !74} ; [ DW_TAG_pointer_type ] +!74 = !{!"0x26\00\000\000\000\000\000", null, !0, null} ; [ DW_TAG_const_type ] +!75 = !{!"0xd\00_scale\0029\0032\0032\0064\000", !154, !61, !76, !"", !"", !"", i32 0} ; [ DW_TAG_member ] +!76 = !{!"0x16\00Float\0089\000\000\000\000", !156, !0, !78} ; [ DW_TAG_typedef ] +!77 = !{!"0x29", !156} ; [ DW_TAG_file_type ] +!78 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !0} ; [ DW_TAG_base_type ] +!79 = !{!"0xd\00_mydataFlags\0037\008\008\0096\000", !154, !61, !80, !"", !"", !"", i32 0} ; [ DW_TAG_member ] +!80 = !{!"0x13\00\0030\008\008\000\000\000", !154, !0, null, !81, null, null, null} ; [ DW_TAG_structure_type ] [line 30, size 8, align 8, offset 0] [def] [from ] +!81 = !{!82, !84, !85, !86, !87, !88} +!82 = !{!"0xd\00named\0031\001\0032\000\000", !154, !61, !83} ; [ DW_TAG_member ] +!83 = !{!"0x24\00unsigned int\000\0032\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ] +!84 = !{!"0xd\00mydataO\0032\003\0032\001\000", !154, !61, !83} ; [ DW_TAG_member ] +!85 = !{!"0xd\00cached\0033\001\0032\004\000", !154, !61, !83} ; [ DW_TAG_member ] +!86 = !{!"0xd\00hasBeenCached\0034\001\0032\005\000", !154, !61, !83} ; [ DW_TAG_member ] +!87 = !{!"0xd\00hasPattern\0035\001\0032\006\000", !154, !61, !83} ; [ DW_TAG_member ] +!88 = !{!"0xd\00isCIMydata\0036\001\0032\007\000", !154, !61, !83} ; [ DW_TAG_member ] +!89 = !{!"0xd\00self\00609\0032\0032\00192\000", !152, !24, !90} ; [ DW_TAG_member ] +!90 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !91} ; [ DW_TAG_pointer_type ] +!91 = !{!"0x13\00MyWork\0036\00384\0032\000\000\0016", !152, !40, null, !92, null, null, null} ; [ DW_TAG_structure_type ] [MyWork] [line 36, size 384, align 32, offset 0] [def] [from ] +!92 = !{!93, !98, !101, !107, !123} +!93 = !{!"0x1c\00\000\000\000\000\000", !152, !91, !94} ; [ DW_TAG_inheritance ] +!94 = !{!"0x13\00twork\0043\0032\0032\000\000\0016", !157, !40, null, !96, null, null, null} ; [ DW_TAG_structure_type ] [twork] [line 43, size 32, align 32, offset 0] [def] [from ] +!95 = !{!"0x29", !157} ; [ DW_TAG_file_type ] +!96 = !{!97} +!97 = !{!"0x1c\00\000\000\000\000\000", !94, null, !64} ; [ DW_TAG_inheritance ] +!98 = !{!"0xd\00_itemID\0038\0064\0032\0032\001", !152, !24, !99, !"", !"", !"", i32 0} ; [ DW_TAG_member ] +!99 = !{!"0x16\00uint64_t\0055\000\000\000\000", !153, !0, !100} ; [ DW_TAG_typedef ] +!100 = !{!"0x24\00long long unsigned int\000\0064\0032\000\000\007", null, !0} ; [ DW_TAG_base_type ] +!101 = !{!"0xd\00_library\0039\0032\0032\0096\001", !152, !24, !102, !"", !"", !"", i32 0} ; [ DW_TAG_member ] +!102 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !103} ; [ DW_TAG_pointer_type ] +!103 = !{!"0x13\00MyLibrary2\0022\0032\0032\000\000\0016", !158, !40, null, !105, null, null, null} ; [ DW_TAG_structure_type ] [MyLibrary2] [line 22, size 32, align 32, offset 0] [def] [from ] +!104 = !{!"0x29", !158} ; [ DW_TAG_file_type ] +!105 = !{!106} +!106 = !{!"0x1c\00\000\000\000\000\000", !103, null, !64} ; [ DW_TAG_inheritance ] +!107 = !{!"0xd\00_bounds\0040\00128\0032\00128\001", !152, !24, !108, !"", !"", !"", i32 0} ; [ DW_TAG_member ] +!108 = !{!"0x16\00CR\0033\000\000\000\000", !153, !0, !109} ; [ DW_TAG_typedef ] +!109 = !{!"0x13\00CR\0029\00128\0032\000\000\000", !156, !0, null, !110, null, null, null} ; [ DW_TAG_structure_type ] [CR] [line 29, size 128, align 32, offset 0] [def] [from ] +!110 = !{!111, !117} +!111 = !{!"0xd\00origin\0030\0064\0032\000\000", !156, !77, !112} ; [ DW_TAG_member ] +!112 = !{!"0x16\00CP\0017\000\000\000\000", !156, !0, !113} ; [ DW_TAG_typedef ] +!113 = !{!"0x13\00CP\0013\0064\0032\000\000\000", !156, !0, null, !114, null, null, null} ; [ DW_TAG_structure_type ] [CP] [line 13, size 64, align 32, offset 0] [def] [from ] +!114 = !{!115, !116} +!115 = !{!"0xd\00x\0014\0032\0032\000\000", !156, !77, !76} ; [ DW_TAG_member ] +!116 = !{!"0xd\00y\0015\0032\0032\0032\000", !156, !77, !76} ; [ DW_TAG_member ] +!117 = !{!"0xd\00size\0031\0064\0032\0064\000", !156, !77, !118} ; [ DW_TAG_member ] +!118 = !{!"0x16\00Size\0025\000\000\000\000", !156, !0, !119} ; [ DW_TAG_typedef ] +!119 = !{!"0x13\00Size\0021\0064\0032\000\000\000", !156, !0, null, !120, null, null, null} ; [ DW_TAG_structure_type ] [Size] [line 21, size 64, align 32, offset 0] [def] [from ] +!120 = !{!121, !122} +!121 = !{!"0xd\00width\0022\0032\0032\000\000", !156, !77, !76} ; [ DW_TAG_member ] +!122 = !{!"0xd\00height\0023\0032\0032\0032\000", !156, !77, !76} ; [ DW_TAG_member ] +!123 = !{!"0xd\00_data\0040\00128\0032\00256\001", !152, !24, !108, !"", !"", !"", i32 0} ; [ DW_TAG_member ] +!124 = !{!"0xd\00semi\00609\0032\0032\00224\000", !152, !24, !125} ; [ DW_TAG_member ] +!125 = !{!"0x16\00d_t\0035\000\000\000\000", !152, !0, !126} ; [ DW_TAG_typedef ] +!126 = !{!"0xf\00\000\0032\0032\000\000", null, !0, !127} ; [ DW_TAG_pointer_type ] +!127 = !{!"0x13\00my_struct\0049\000\000\000\004\000", !159, !0, null, null, null, null, null} ; [ DW_TAG_structure_type ] [my_struct] [line 49, size 0, align 0, offset 0] [decl] [from ] +!128 = !{!"0x29", !159} ; [ DW_TAG_file_type ] +!129 = !MDLocation(line: 609, column: 144, scope: !23) +!130 = !{!"0x101\00loadedMydata\0033555041\000", !23, !24, !59} ; [ DW_TAG_arg_variable ] +!131 = !MDLocation(line: 609, column: 155, scope: !23) +!132 = !{!"0x101\00bounds\0050332257\000", !23, !24, !108} ; [ DW_TAG_arg_variable ] +!133 = !MDLocation(line: 609, column: 175, scope: !23) +!134 = !{!"0x101\00data\0067109473\000", !23, !24, !108} ; [ DW_TAG_arg_variable ] +!135 = !MDLocation(line: 609, column: 190, scope: !23) +!136 = !{!"0x100\00mydata\00604\000", !23, !24, !50} ; [ DW_TAG_auto_variable ] +!137 = !MDLocation(line: 604, column: 49, scope: !23) +!138 = !{!"0x100\00self\00604\000", !23, !40, !90} ; [ DW_TAG_auto_variable ] +!139 = !{!"0x100\00semi\00607\000", !23, !24, !125} ; [ DW_TAG_auto_variable ] +!140 = !MDLocation(line: 607, column: 30, scope: !23) +!141 = !MDLocation(line: 610, column: 17, scope: !142) +!142 = !{!"0xb\00609\00200\0094", !152, !23} ; [ DW_TAG_lexical_block ] +!143 = !MDLocation(line: 611, column: 17, scope: !142) +!144 = !MDLocation(line: 612, column: 17, scope: !142) +!145 = !MDLocation(line: 613, column: 17, scope: !142) +!146 = !MDLocation(line: 615, column: 13, scope: !142) +!147 = !{!1, !1, !5, !5, !9, !14, !19, !19, !14, !14, !14, !19, !19, !19} +!148 = !{!23} +!149 = !{!"header3.h", !"/Volumes/Sandbox/llvm"} +!150 = !{!"Private.h", !"/Volumes/Sandbox/llvm"} +!151 = !{!"header4.h", !"/Volumes/Sandbox/llvm"} +!152 = !{!"MyLibrary.m", !"/Volumes/Sandbox/llvm"} +!153 = !{!"MyLibrary.i", !"/Volumes/Sandbox/llvm"} +!154 = !{!"header11.h", !"/Volumes/Sandbox/llvm"} +!155 = !{!"NSO.h", !"/Volumes/Sandbox/llvm"} +!156 = !{!"header12.h", !"/Volumes/Sandbox/llvm"} +!157 = !{!"header13.h", !"/Volumes/Sandbox/llvm"} +!158 = !{!"header14.h", !"/Volumes/Sandbox/llvm"} +!159 = !{!"header15.h", !"/Volumes/Sandbox/llvm"} +!160 = !{!"header.h", !"/Volumes/Sandbox/llvm"} +!161 = !{!"header2.h", !"/Volumes/Sandbox/llvm"} +!162 = !{i32 1, !"Debug Info Version", i32 2} +!163 = !{!"0x102\0034\0020\006\0034\004\006\0034\0024"} ; [ DW_TAG_expression ] [DW_OP_plus 20 DW_OP_deref DW_OP_plus 4 DW_OP_deref DW_OP_plus 24] +!164 = !{!"0x102\0034\0024"} ; [ DW_TAG_expression ] [DW_OP_plus 24] +!165 = !{!"0x102\0034\0028"} ; [ DW_TAG_expression ] [DW_OP_plus 28] diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll index db96b49..9475695 100644 --- a/test/CodeGen/ARM/debug-info-branch-folding.ll +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -20,9 +20,9 @@ entry: for.body9: ; preds = %for.body9, %entry %add19 = fadd <4 x float> undef, , !dbg !39 - tail call void @llvm.dbg.value(metadata !{<4 x float> %add19}, i64 0, metadata !27, metadata !{metadata !"0x102"}), !dbg !39 + tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !39 %add20 = fadd <4 x float> undef, , !dbg !39 - tail call void @llvm.dbg.value(metadata !{<4 x float> %add20}, i64 0, metadata !28, metadata !{metadata !"0x102"}), !dbg !39 + tail call void @llvm.dbg.value(metadata <4 x float> %add20, i64 0, metadata !28, metadata !{!"0x102"}), !dbg !39 br i1 %cond, label %for.end54, label %for.body9, !dbg !44 for.end54: ; preds = %for.body9 @@ -42,60 +42,60 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.module.flags = !{!56} !llvm.dbg.cu = !{!2} -!0 = metadata !{metadata !"0x2e\00test0001\00test0001\00\003\000\001\000\006\00256\001\000", metadata !54, null, metadata !3, i32 0, <4 x float> (float)* @test0001, null, null, metadata !51} ; [ DW_TAG_subprogram ] -!1 = metadata !{metadata !"0x29", metadata !54} ; [ DW_TAG_file_type ] -!2 = metadata !{metadata !"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", metadata !54, metadata !17, metadata !17, metadata !50, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !54, metadata !1, i32 0, metadata !4, i32 0} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{metadata !"0x16\00v4f32\0014\000\000\000\000", metadata !54, metadata !2, metadata !6} ; [ DW_TAG_typedef ] -!6 = metadata !{metadata !"0x1\00\000\00128\00128\000\000", metadata !54, metadata !2, metadata !7, metadata !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float] -!7 = metadata !{metadata !"0x24\00float\000\0032\0032\000\000\004", null, metadata !2} ; [ DW_TAG_base_type ] -!8 = metadata !{metadata !9} -!9 = metadata !{metadata !"0x21\000\004"} ; [ DW_TAG_subrange_type ] -!10 = metadata !{metadata !"0x2e\00main\00main\00\0059\000\001\000\006\00256\001\000", metadata !54, null, metadata !11, null, i32 (i32, i8**, i1)* @main, null, null, metadata !52} ; [ DW_TAG_subprogram ] [line 59] [def] [scope 0] [main] -!11 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !54, metadata !1, null, metadata !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!12 = metadata !{metadata !13} -!13 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, metadata !2} ; [ DW_TAG_base_type ] -!14 = metadata !{metadata !"0x2e\00printFV\00printFV\00\0041\001\001\000\006\00256\001\000", metadata !55, null, metadata !16, null, null, null, null, metadata !53} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [scope 0] [printFV] -!15 = metadata !{metadata !"0x29", metadata !55} ; [ DW_TAG_file_type ] -!16 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !55, metadata !15, null, metadata !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!17 = metadata !{null} -!18 = metadata !{metadata !"0x101\00a\0016777219\000", metadata !0, metadata !1, metadata !7} ; [ DW_TAG_arg_variable ] -!19 = metadata !{metadata !"0x101\00argc\0016777275\000", metadata !10, metadata !1, metadata !13} ; [ DW_TAG_arg_variable ] -!20 = metadata !{metadata !"0x101\00argv\0033554491\000", metadata !10, metadata !1, metadata !21} ; [ DW_TAG_arg_variable ] -!21 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !2, metadata !22} ; [ DW_TAG_pointer_type ] -!22 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !2, metadata !23} ; [ DW_TAG_pointer_type ] -!23 = metadata !{metadata !"0x24\00char\000\008\008\000\000\006", null, metadata !2} ; [ DW_TAG_base_type ] -!24 = metadata !{metadata !"0x100\00i\0060\000", metadata !25, metadata !1, metadata !13} ; [ DW_TAG_auto_variable ] -!25 = metadata !{metadata !"0xb\0059\0033\0014", metadata !1, metadata !10} ; [ DW_TAG_lexical_block ] -!26 = metadata !{metadata !"0x100\00j\0060\000", metadata !25, metadata !1, metadata !13} ; [ DW_TAG_auto_variable ] -!27 = metadata !{metadata !"0x100\00x\0061\000", metadata !25, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!28 = metadata !{metadata !"0x100\00y\0062\000", metadata !25, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!29 = metadata !{metadata !"0x100\00z\0063\000", metadata !25, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!30 = metadata !{metadata !"0x101\00F\0016777257\000", metadata !14, metadata !15, metadata !31} ; [ DW_TAG_arg_variable ] -!31 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !2, metadata !32} ; [ DW_TAG_pointer_type ] -!32 = metadata !{metadata !"0x16\00FV\0025\000\000\000\000", metadata !55, metadata !2, metadata !33} ; [ DW_TAG_typedef ] -!33 = metadata !{metadata !"0x17\00\0022\00128\00128\000\000\000", metadata !55, metadata !2, i32 0, metadata !34, null} ; [ DW_TAG_union_type ] -!34 = metadata !{metadata !35, metadata !37} -!35 = metadata !{metadata !"0xd\00V\0023\00128\00128\000\000", metadata !55, metadata !15, metadata !36} ; [ DW_TAG_member ] -!36 = metadata !{metadata !"0x16\00v4sf\003\000\000\000\000", metadata !55, metadata !2, metadata !6} ; [ DW_TAG_typedef ] -!37 = metadata !{metadata !"0xd\00A\0024\00128\0032\000\000", metadata !55, metadata !15, metadata !38} ; [ DW_TAG_member ] -!38 = metadata !{metadata !"0x1\00\000\00128\0032\000\000", null, metadata !2, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ] -!39 = metadata !{i32 79, i32 7, metadata !40, null} -!40 = metadata !{metadata !"0xb\0075\0035\0018", metadata !1, metadata !41} ; [ DW_TAG_lexical_block ] -!41 = metadata !{metadata !"0xb\0075\005\0017", metadata !1, metadata !42} ; [ DW_TAG_lexical_block ] -!42 = metadata !{metadata !"0xb\0071\0032\0016", metadata !1, metadata !43} ; [ DW_TAG_lexical_block ] -!43 = metadata !{metadata !"0xb\0071\003\0015", metadata !1, metadata !25} ; [ DW_TAG_lexical_block ] -!44 = metadata !{i32 75, i32 5, metadata !42, null} -!45 = metadata !{i32 42, i32 2, metadata !46, metadata !48} -!46 = metadata !{metadata !"0xb\0042\002\0020", metadata !15, metadata !47} ; [ DW_TAG_lexical_block ] -!47 = metadata !{metadata !"0xb\0041\0028\0019", metadata !15, metadata !14} ; [ DW_TAG_lexical_block ] -!48 = metadata !{i32 95, i32 3, metadata !25, null} -!49 = metadata !{i32 99, i32 3, metadata !25, null} -!50 = metadata !{metadata !0, metadata !10, metadata !14} -!51 = metadata !{metadata !18} -!52 = metadata !{metadata !19, metadata !20, metadata !24, metadata !26, metadata !27, metadata !28, metadata !29} -!53 = metadata !{metadata !30} -!54 = metadata !{metadata !"build2.c", metadata !"/private/tmp"} -!55 = metadata !{metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp"} -!56 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x2e\00test0001\00test0001\00\003\000\001\000\006\00256\001\000", !54, null, !3, i32 0, <4 x float> (float)* @test0001, null, null, !51} ; [ DW_TAG_subprogram ] +!1 = !{!"0x29", !54} ; [ DW_TAG_file_type ] +!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", !54, !17, !17, !50, null, null} ; [ DW_TAG_compile_unit ] +!3 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, i32 0, !4, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = !{!5} +!5 = !{!"0x16\00v4f32\0014\000\000\000\000", !54, !2, !6} ; [ DW_TAG_typedef ] +!6 = !{!"0x1\00\000\00128\00128\000\000", !54, !2, !7, !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float] +!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ] +!8 = !{!9} +!9 = !{!"0x21\000\004"} ; [ DW_TAG_subrange_type ] +!10 = !{!"0x2e\00main\00main\00\0059\000\001\000\006\00256\001\000", !54, null, !11, null, i32 (i32, i8**, i1)* @main, null, null, !52} ; [ DW_TAG_subprogram ] [line 59] [def] [scope 0] [main] +!11 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!12 = !{!13} +!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ] +!14 = !{!"0x2e\00printFV\00printFV\00\0041\001\001\000\006\00256\001\000", !55, null, !16, null, null, null, null, !53} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [scope 0] [printFV] +!15 = !{!"0x29", !55} ; [ DW_TAG_file_type ] +!16 = !{!"0x15\00\000\000\000\000\000\000", !55, !15, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!17 = !{null} +!18 = !{!"0x101\00a\0016777219\000", !0, !1, !7} ; [ DW_TAG_arg_variable ] +!19 = !{!"0x101\00argc\0016777275\000", !10, !1, !13} ; [ DW_TAG_arg_variable ] +!20 = !{!"0x101\00argv\0033554491\000", !10, !1, !21} ; [ DW_TAG_arg_variable ] +!21 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !22} ; [ DW_TAG_pointer_type ] +!22 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !23} ; [ DW_TAG_pointer_type ] +!23 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ] +!24 = !{!"0x100\00i\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ] +!25 = !{!"0xb\0059\0033\0014", !1, !10} ; [ DW_TAG_lexical_block ] +!26 = !{!"0x100\00j\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ] +!27 = !{!"0x100\00x\0061\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] +!28 = !{!"0x100\00y\0062\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] +!29 = !{!"0x100\00z\0063\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] +!30 = !{!"0x101\00F\0016777257\000", !14, !15, !31} ; [ DW_TAG_arg_variable ] +!31 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !32} ; [ DW_TAG_pointer_type ] +!32 = !{!"0x16\00FV\0025\000\000\000\000", !55, !2, !33} ; [ DW_TAG_typedef ] +!33 = !{!"0x17\00\0022\00128\00128\000\000\000", !55, !2, i32 0, !34, null} ; [ DW_TAG_union_type ] +!34 = !{!35, !37} +!35 = !{!"0xd\00V\0023\00128\00128\000\000", !55, !15, !36} ; [ DW_TAG_member ] +!36 = !{!"0x16\00v4sf\003\000\000\000\000", !55, !2, !6} ; [ DW_TAG_typedef ] +!37 = !{!"0xd\00A\0024\00128\0032\000\000", !55, !15, !38} ; [ DW_TAG_member ] +!38 = !{!"0x1\00\000\00128\0032\000\000", null, !2, !7, !8, i32 0, i32 0} ; [ DW_TAG_array_type ] +!39 = !MDLocation(line: 79, column: 7, scope: !40) +!40 = !{!"0xb\0075\0035\0018", !1, !41} ; [ DW_TAG_lexical_block ] +!41 = !{!"0xb\0075\005\0017", !1, !42} ; [ DW_TAG_lexical_block ] +!42 = !{!"0xb\0071\0032\0016", !1, !43} ; [ DW_TAG_lexical_block ] +!43 = !{!"0xb\0071\003\0015", !1, !25} ; [ DW_TAG_lexical_block ] +!44 = !MDLocation(line: 75, column: 5, scope: !42) +!45 = !MDLocation(line: 42, column: 2, scope: !46, inlinedAt: !48) +!46 = !{!"0xb\0042\002\0020", !15, !47} ; [ DW_TAG_lexical_block ] +!47 = !{!"0xb\0041\0028\0019", !15, !14} ; [ DW_TAG_lexical_block ] +!48 = !MDLocation(line: 95, column: 3, scope: !25) +!49 = !MDLocation(line: 99, column: 3, scope: !25) +!50 = !{!0, !10, !14} +!51 = !{!18} +!52 = !{!19, !20, !24, !26, !27, !28, !29} +!53 = !{!30} +!54 = !{!"build2.c", !"/private/tmp"} +!55 = !{!"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", !"/private/tmp"} +!56 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll index 9791987..85b510f 100644 --- a/test/CodeGen/ARM/debug-info-d16-reg.ll +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -12,9 +12,9 @@ target triple = "thumbv7-apple-darwin10" define i32 @inlineprinter(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !19, metadata !{metadata !"0x102"}), !dbg !26 - tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !20, metadata !{metadata !"0x102"}), !dbg !26 - tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !21, metadata !{metadata !"0x102"}), !dbg !26 + tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !19, metadata !{!"0x102"}), !dbg !26 + tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !20, metadata !{!"0x102"}), !dbg !26 + tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !21, metadata !{!"0x102"}), !dbg !26 %0 = zext i8 %c to i32, !dbg !27 %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27 ret i32 0, !dbg !29 @@ -22,9 +22,9 @@ entry: define i32 @printer(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize noinline { entry: - tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !16, metadata !{metadata !"0x102"}), !dbg !30 - tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !17, metadata !{metadata !"0x102"}), !dbg !30 - tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !18, metadata !{metadata !"0x102"}), !dbg !30 + tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !30 + tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !30 + tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !30 %0 = zext i8 %c to i32, !dbg !31 %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31 ret i32 0, !dbg !33 @@ -36,18 +36,18 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize { entry: - tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !22, metadata !{metadata !"0x102"}), !dbg !34 - tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !23, metadata !{metadata !"0x102"}), !dbg !34 + tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !34 + tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !23, metadata !{!"0x102"}), !dbg !34 %0 = sitofp i32 %argc to double, !dbg !35 %1 = fadd double %0, 5.555552e+05, !dbg !35 - tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !24, metadata !{metadata !"0x102"}), !dbg !35 + tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !24, metadata !{!"0x102"}), !dbg !35 %2 = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind, !dbg !36 %3 = getelementptr inbounds i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !37 %4 = trunc i32 %argc to i8, !dbg !37 %5 = add i8 %4, 97, !dbg !37 - tail call void @llvm.dbg.value(metadata !{i8* %3}, i64 0, metadata !19, metadata !{metadata !"0x102"}) nounwind, !dbg !38 - tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !20, metadata !{metadata !"0x102"}) nounwind, !dbg !38 - tail call void @llvm.dbg.value(metadata !{i8 %5}, i64 0, metadata !21, metadata !{metadata !"0x102"}) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata i8* %3, i64 0, metadata !19, metadata !{!"0x102"}) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !20, metadata !{!"0x102"}) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata i8 %5, i64 0, metadata !21, metadata !{!"0x102"}) nounwind, !dbg !38 %6 = zext i8 %5 to i32, !dbg !39 %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39 %8 = tail call i32 @printer(i8* %3, double %1, i8 zeroext %5) nounwind, !dbg !40 @@ -59,52 +59,52 @@ declare i32 @puts(i8* nocapture) nounwind !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!48} -!0 = metadata !{metadata !"0x2e\00printer\00printer\00printer\0012\000\001\000\006\00256\001\0012", metadata !46, metadata !1, metadata !3, null, i32 (i8*, double, i8)* @printer, null, null, metadata !43} ; [ DW_TAG_subprogram ] -!1 = metadata !{metadata !"0x29", metadata !46} ; [ DW_TAG_file_type ] -!2 = metadata !{metadata !"0x11\001\00(LLVM build 00)\001\00\000\00\001", metadata !46, metadata !47, metadata !47, metadata !42, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !46, metadata !1, null, metadata !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!4 = metadata !{metadata !5, metadata !6, metadata !7, metadata !8} -!5 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", metadata !46, metadata !1} ; [ DW_TAG_base_type ] -!6 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", metadata !46, metadata !1, null} ; [ DW_TAG_pointer_type ] -!7 = metadata !{metadata !"0x24\00double\000\0064\0032\000\000\004", metadata !46, metadata !1} ; [ DW_TAG_base_type ] -!8 = metadata !{metadata !"0x24\00unsigned char\000\008\008\000\000\008", metadata !46, metadata !1} ; [ DW_TAG_base_type ] -!9 = metadata !{metadata !"0x2e\00inlineprinter\00inlineprinter\00inlineprinter\005\000\001\000\006\00256\001\005", metadata !46, metadata !1, metadata !3, null, i32 (i8*, double, i8)* @inlineprinter, null, null, metadata !44} ; [ DW_TAG_subprogram ] -!10 = metadata !{metadata !"0x2e\00main\00main\00main\0018\000\001\000\006\00256\001\0018", metadata !46, metadata !1, metadata !11, null, i32 (i32, i8**)* @main, null, null, metadata !45} ; [ DW_TAG_subprogram ] -!11 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !46, metadata !1, null, metadata !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!12 = metadata !{metadata !5, metadata !5, metadata !13} -!13 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", metadata !46, metadata !1, metadata !14} ; [ DW_TAG_pointer_type ] -!14 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", metadata !46, metadata !1, metadata !15} ; [ DW_TAG_pointer_type ] -!15 = metadata !{metadata !"0x24\00char\000\008\008\000\000\006", metadata !46, metadata !1} ; [ DW_TAG_base_type ] -!16 = metadata !{metadata !"0x101\00ptr\0011\000", metadata !0, metadata !1, metadata !6} ; [ DW_TAG_arg_variable ] -!17 = metadata !{metadata !"0x101\00val\0011\000", metadata !0, metadata !1, metadata !7} ; [ DW_TAG_arg_variable ] -!18 = metadata !{metadata !"0x101\00c\0011\000", metadata !0, metadata !1, metadata !8} ; [ DW_TAG_arg_variable ] -!19 = metadata !{metadata !"0x101\00ptr\004\000", metadata !9, metadata !1, metadata !6} ; [ DW_TAG_arg_variable ] -!20 = metadata !{metadata !"0x101\00val\004\000", metadata !9, metadata !1, metadata !7} ; [ DW_TAG_arg_variable ] -!21 = metadata !{metadata !"0x101\00c\004\000", metadata !9, metadata !1, metadata !8} ; [ DW_TAG_arg_variable ] -!22 = metadata !{metadata !"0x101\00argc\0017\000", metadata !10, metadata !1, metadata !5} ; [ DW_TAG_arg_variable ] -!23 = metadata !{metadata !"0x101\00argv\0017\000", metadata !10, metadata !1, metadata !13} ; [ DW_TAG_arg_variable ] -!24 = metadata !{metadata !"0x100\00dval\0019\000", metadata !25, metadata !1, metadata !7} ; [ DW_TAG_auto_variable ] -!25 = metadata !{metadata !"0xb\0018\000\002", metadata !46, metadata !10} ; [ DW_TAG_lexical_block ] -!26 = metadata !{i32 4, i32 0, metadata !9, null} -!27 = metadata !{i32 6, i32 0, metadata !28, null} -!28 = metadata !{metadata !"0xb\005\000\001", metadata !46, metadata !9} ; [ DW_TAG_lexical_block ] -!29 = metadata !{i32 7, i32 0, metadata !28, null} -!30 = metadata !{i32 11, i32 0, metadata !0, null} -!31 = metadata !{i32 13, i32 0, metadata !32, null} -!32 = metadata !{metadata !"0xb\0012\000\000", metadata !46, metadata !0} ; [ DW_TAG_lexical_block ] -!33 = metadata !{i32 14, i32 0, metadata !32, null} -!34 = metadata !{i32 17, i32 0, metadata !10, null} -!35 = metadata !{i32 19, i32 0, metadata !25, null} -!36 = metadata !{i32 20, i32 0, metadata !25, null} -!37 = metadata !{i32 21, i32 0, metadata !25, null} -!38 = metadata !{i32 4, i32 0, metadata !9, metadata !37} -!39 = metadata !{i32 6, i32 0, metadata !28, metadata !37} -!40 = metadata !{i32 22, i32 0, metadata !25, null} -!41 = metadata !{i32 23, i32 0, metadata !25, null} -!42 = metadata !{metadata !0, metadata !9, metadata !10} -!43 = metadata !{metadata !16, metadata !17, metadata !18} -!44 = metadata !{metadata !19, metadata !20, metadata !21} -!45 = metadata !{metadata !22, metadata !23, metadata !24} -!46 = metadata !{metadata !"a.c", metadata !"/tmp/"} -!47 = metadata !{i32 0} -!48 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x2e\00printer\00printer\00printer\0012\000\001\000\006\00256\001\0012", !46, !1, !3, null, i32 (i8*, double, i8)* @printer, null, null, !43} ; [ DW_TAG_subprogram ] +!1 = !{!"0x29", !46} ; [ DW_TAG_file_type ] +!2 = !{!"0x11\001\00(LLVM build 00)\001\00\000\00\001", !46, !47, !47, !42, null, null} ; [ DW_TAG_compile_unit ] +!3 = !{!"0x15\00\000\000\000\000\000\000", !46, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !{!5, !6, !7, !8} +!5 = !{!"0x24\00int\000\0032\0032\000\000\005", !46, !1} ; [ DW_TAG_base_type ] +!6 = !{!"0xf\00\000\0032\0032\000\000", !46, !1, null} ; [ DW_TAG_pointer_type ] +!7 = !{!"0x24\00double\000\0064\0032\000\000\004", !46, !1} ; [ DW_TAG_base_type ] +!8 = !{!"0x24\00unsigned char\000\008\008\000\000\008", !46, !1} ; [ DW_TAG_base_type ] +!9 = !{!"0x2e\00inlineprinter\00inlineprinter\00inlineprinter\005\000\001\000\006\00256\001\005", !46, !1, !3, null, i32 (i8*, double, i8)* @inlineprinter, null, null, !44} ; [ DW_TAG_subprogram ] +!10 = !{!"0x2e\00main\00main\00main\0018\000\001\000\006\00256\001\0018", !46, !1, !11, null, i32 (i32, i8**)* @main, null, null, !45} ; [ DW_TAG_subprogram ] +!11 = !{!"0x15\00\000\000\000\000\000\000", !46, !1, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!12 = !{!5, !5, !13} +!13 = !{!"0xf\00\000\0032\0032\000\000", !46, !1, !14} ; [ DW_TAG_pointer_type ] +!14 = !{!"0xf\00\000\0032\0032\000\000", !46, !1, !15} ; [ DW_TAG_pointer_type ] +!15 = !{!"0x24\00char\000\008\008\000\000\006", !46, !1} ; [ DW_TAG_base_type ] +!16 = !{!"0x101\00ptr\0011\000", !0, !1, !6} ; [ DW_TAG_arg_variable ] +!17 = !{!"0x101\00val\0011\000", !0, !1, !7} ; [ DW_TAG_arg_variable ] +!18 = !{!"0x101\00c\0011\000", !0, !1, !8} ; [ DW_TAG_arg_variable ] +!19 = !{!"0x101\00ptr\004\000", !9, !1, !6} ; [ DW_TAG_arg_variable ] +!20 = !{!"0x101\00val\004\000", !9, !1, !7} ; [ DW_TAG_arg_variable ] +!21 = !{!"0x101\00c\004\000", !9, !1, !8} ; [ DW_TAG_arg_variable ] +!22 = !{!"0x101\00argc\0017\000", !10, !1, !5} ; [ DW_TAG_arg_variable ] +!23 = !{!"0x101\00argv\0017\000", !10, !1, !13} ; [ DW_TAG_arg_variable ] +!24 = !{!"0x100\00dval\0019\000", !25, !1, !7} ; [ DW_TAG_auto_variable ] +!25 = !{!"0xb\0018\000\002", !46, !10} ; [ DW_TAG_lexical_block ] +!26 = !MDLocation(line: 4, scope: !9) +!27 = !MDLocation(line: 6, scope: !28) +!28 = !{!"0xb\005\000\001", !46, !9} ; [ DW_TAG_lexical_block ] +!29 = !MDLocation(line: 7, scope: !28) +!30 = !MDLocation(line: 11, scope: !0) +!31 = !MDLocation(line: 13, scope: !32) +!32 = !{!"0xb\0012\000\000", !46, !0} ; [ DW_TAG_lexical_block ] +!33 = !MDLocation(line: 14, scope: !32) +!34 = !MDLocation(line: 17, scope: !10) +!35 = !MDLocation(line: 19, scope: !25) +!36 = !MDLocation(line: 20, scope: !25) +!37 = !MDLocation(line: 21, scope: !25) +!38 = !MDLocation(line: 4, scope: !9, inlinedAt: !37) +!39 = !MDLocation(line: 6, scope: !28, inlinedAt: !37) +!40 = !MDLocation(line: 22, scope: !25) +!41 = !MDLocation(line: 23, scope: !25) +!42 = !{!0, !9, !10} +!43 = !{!16, !17, !18} +!44 = !{!19, !20, !21} +!45 = !{!22, !23, !24} +!46 = !{!"a.c", !"/tmp/"} +!47 = !{i32 0} +!48 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll index cfcefb8..c05df6a 100644 --- a/test/CodeGen/ARM/debug-info-qreg.ll +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -2,13 +2,11 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-macosx10.6.7" -;CHECK: sub-register -;CHECK-NEXT: DW_OP_regx +;CHECK: sub-register DW_OP_regx ;CHECK-NEXT: ascii ;CHECK-NEXT: DW_OP_piece ;CHECK-NEXT: byte 8 -;CHECK-NEXT: sub-register -;CHECK-NEXT: DW_OP_regx +;CHECK-NEXT: sub-register DW_OP_regx ;CHECK-NEXT: ascii ;CHECK-NEXT: DW_OP_piece ;CHECK-NEXT: byte 8 @@ -26,7 +24,7 @@ for.body9: ; preds = %for.body9, %entry br i1 undef, label %for.end54, label %for.body9, !dbg !44 for.end54: ; preds = %for.body9 - tail call void @llvm.dbg.value(metadata !{<4 x float> %add19}, i64 0, metadata !27, metadata !{metadata !"0x102"}), !dbg !39 + tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !{!"0x102"}), !dbg !39 %tmp115 = extractelement <4 x float> %add19, i32 1 %conv6.i75 = fpext float %tmp115 to double, !dbg !45 %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 @@ -40,60 +38,60 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!56} -!0 = metadata !{metadata !"0x2e\00test0001\00test0001\00\003\000\001\000\006\00256\001\003", metadata !54, metadata !1, metadata !3, null, <4 x float> (float)* @test0001, null, null, metadata !51} ; [ DW_TAG_subprogram ] [line 3] [def] [test0001] -!1 = metadata !{metadata !"0x29", metadata !54} ; [ DW_TAG_file_type ] -!2 = metadata !{metadata !"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", metadata !54, metadata !17, metadata !17, metadata !50, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !54, metadata !1, null, metadata !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!4 = metadata !{metadata !5} -!5 = metadata !{metadata !"0x16\00v4f32\0014\000\000\000\000", metadata !54, metadata !2, metadata !6} ; [ DW_TAG_typedef ] -!6 = metadata !{metadata !"0x1\00\000\00128\00128\000\000", metadata !2, null, metadata !7, metadata !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float] -!7 = metadata !{metadata !"0x24\00float\000\0032\0032\000\000\004", null, metadata !2} ; [ DW_TAG_base_type ] -!8 = metadata !{metadata !9} -!9 = metadata !{metadata !"0x21\000\004"} ; [ DW_TAG_subrange_type ] -!10 = metadata !{metadata !"0x2e\00main\00main\00\0059\000\001\000\006\00256\001\0059", metadata !54, metadata !1, metadata !11, null, i32 (i32, i8**)* @main, null, null, metadata !52} ; [ DW_TAG_subprogram ] [line 59] [def] [main] -!11 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !54, metadata !1, null, metadata !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!12 = metadata !{metadata !13} -!13 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, metadata !2} ; [ DW_TAG_base_type ] -!14 = metadata !{metadata !"0x2e\00printFV\00printFV\00\0041\001\001\000\006\00256\001\0041", metadata !55, metadata !15, metadata !16, null, null, null, null, metadata !53} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [printFV] -!15 = metadata !{metadata !"0x29", metadata !55} ; [ DW_TAG_file_type ] -!16 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !55, metadata !15, null, metadata !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!17 = metadata !{null} -!18 = metadata !{metadata !"0x101\00a\0016777219\000", metadata !0, metadata !1, metadata !7} ; [ DW_TAG_arg_variable ] -!19 = metadata !{metadata !"0x101\00argc\0016777275\000", metadata !10, metadata !1, metadata !13} ; [ DW_TAG_arg_variable ] -!20 = metadata !{metadata !"0x101\00argv\0033554491\000", metadata !10, metadata !1, metadata !21} ; [ DW_TAG_arg_variable ] -!21 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !2, metadata !22} ; [ DW_TAG_pointer_type ] -!22 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !2, metadata !23} ; [ DW_TAG_pointer_type ] -!23 = metadata !{metadata !"0x24\00char\000\008\008\000\000\006", null, metadata !2} ; [ DW_TAG_base_type ] -!24 = metadata !{metadata !"0x100\00i\0060\000", metadata !25, metadata !1, metadata !13} ; [ DW_TAG_auto_variable ] -!25 = metadata !{metadata !"0xb\0059\0033\0014", metadata !54, metadata !10} ; [ DW_TAG_lexical_block ] -!26 = metadata !{metadata !"0x100\00j\0060\000", metadata !25, metadata !1, metadata !13} ; [ DW_TAG_auto_variable ] -!27 = metadata !{metadata !"0x100\00x\0061\000", metadata !25, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!28 = metadata !{metadata !"0x100\00y\0062\000", metadata !25, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!29 = metadata !{metadata !"0x100\00z\0063\000", metadata !25, metadata !1, metadata !5} ; [ DW_TAG_auto_variable ] -!30 = metadata !{metadata !"0x101\00F\0016777257\000", metadata !14, metadata !15, metadata !31} ; [ DW_TAG_arg_variable ] -!31 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !2, metadata !32} ; [ DW_TAG_pointer_type ] -!32 = metadata !{metadata !"0x16\00FV\0025\000\000\000\000", metadata !55, metadata !2, metadata !33} ; [ DW_TAG_typedef ] -!33 = metadata !{metadata !"0x17\00\0022\00128\00128\000\000\000", metadata !55, metadata !2, i32 0, metadata !34, null} ; [ DW_TAG_union_type ] -!34 = metadata !{metadata !35, metadata !37} -!35 = metadata !{metadata !"0xd\00V\0023\00128\00128\000\000", metadata !55, metadata !15, metadata !36} ; [ DW_TAG_member ] -!36 = metadata !{metadata !"0x16\00v4sf\003\000\000\000\000", metadata !55, metadata !2, metadata !6} ; [ DW_TAG_typedef ] -!37 = metadata !{metadata !"0xd\00A\0024\00128\0032\000\000", metadata !55, metadata !15, metadata !38} ; [ DW_TAG_member ] -!38 = metadata !{metadata !"0x1\00\000\00128\0032\000\000", null, metadata !2, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ] -!39 = metadata !{i32 79, i32 7, metadata !40, null} -!40 = metadata !{metadata !"0xb\0075\0035\0018", metadata !54, metadata !41} ; [ DW_TAG_lexical_block ] -!41 = metadata !{metadata !"0xb\0075\005\0017", metadata !54, metadata !42} ; [ DW_TAG_lexical_block ] -!42 = metadata !{metadata !"0xb\0071\0032\0016", metadata !54, metadata !43} ; [ DW_TAG_lexical_block ] -!43 = metadata !{metadata !"0xb\0071\003\0015", metadata !54, metadata !25} ; [ DW_TAG_lexical_block ] -!44 = metadata !{i32 75, i32 5, metadata !42, null} -!45 = metadata !{i32 42, i32 2, metadata !46, metadata !48} -!46 = metadata !{metadata !"0xb\0042\002\0020", metadata !55, metadata !47} ; [ DW_TAG_lexical_block ] -!47 = metadata !{metadata !"0xb\0041\0028\0019", metadata !55, metadata !14} ; [ DW_TAG_lexical_block ] -!48 = metadata !{i32 95, i32 3, metadata !25, null} -!49 = metadata !{i32 99, i32 3, metadata !25, null} -!50 = metadata !{metadata !0, metadata !10, metadata !14} -!51 = metadata !{metadata !18} -!52 = metadata !{metadata !19, metadata !20, metadata !24, metadata !26, metadata !27, metadata !28, metadata !29} -!53 = metadata !{metadata !30} -!54 = metadata !{metadata !"build2.c", metadata !"/private/tmp"} -!55 = metadata !{metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp"} -!56 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x2e\00test0001\00test0001\00\003\000\001\000\006\00256\001\003", !54, !1, !3, null, <4 x float> (float)* @test0001, null, null, !51} ; [ DW_TAG_subprogram ] [line 3] [def] [test0001] +!1 = !{!"0x29", !54} ; [ DW_TAG_file_type ] +!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", !54, !17, !17, !50, null, null} ; [ DW_TAG_compile_unit ] +!3 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !{!5} +!5 = !{!"0x16\00v4f32\0014\000\000\000\000", !54, !2, !6} ; [ DW_TAG_typedef ] +!6 = !{!"0x1\00\000\00128\00128\000\000", !2, null, !7, !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float] +!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ] +!8 = !{!9} +!9 = !{!"0x21\000\004"} ; [ DW_TAG_subrange_type ] +!10 = !{!"0x2e\00main\00main\00\0059\000\001\000\006\00256\001\0059", !54, !1, !11, null, i32 (i32, i8**)* @main, null, null, !52} ; [ DW_TAG_subprogram ] [line 59] [def] [main] +!11 = !{!"0x15\00\000\000\000\000\000\000", !54, !1, null, !12, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!12 = !{!13} +!13 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ] +!14 = !{!"0x2e\00printFV\00printFV\00\0041\001\001\000\006\00256\001\0041", !55, !15, !16, null, null, null, null, !53} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [printFV] +!15 = !{!"0x29", !55} ; [ DW_TAG_file_type ] +!16 = !{!"0x15\00\000\000\000\000\000\000", !55, !15, null, !17, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!17 = !{null} +!18 = !{!"0x101\00a\0016777219\000", !0, !1, !7} ; [ DW_TAG_arg_variable ] +!19 = !{!"0x101\00argc\0016777275\000", !10, !1, !13} ; [ DW_TAG_arg_variable ] +!20 = !{!"0x101\00argv\0033554491\000", !10, !1, !21} ; [ DW_TAG_arg_variable ] +!21 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !22} ; [ DW_TAG_pointer_type ] +!22 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !23} ; [ DW_TAG_pointer_type ] +!23 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ] +!24 = !{!"0x100\00i\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ] +!25 = !{!"0xb\0059\0033\0014", !54, !10} ; [ DW_TAG_lexical_block ] +!26 = !{!"0x100\00j\0060\000", !25, !1, !13} ; [ DW_TAG_auto_variable ] +!27 = !{!"0x100\00x\0061\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] +!28 = !{!"0x100\00y\0062\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] +!29 = !{!"0x100\00z\0063\000", !25, !1, !5} ; [ DW_TAG_auto_variable ] +!30 = !{!"0x101\00F\0016777257\000", !14, !15, !31} ; [ DW_TAG_arg_variable ] +!31 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !32} ; [ DW_TAG_pointer_type ] +!32 = !{!"0x16\00FV\0025\000\000\000\000", !55, !2, !33} ; [ DW_TAG_typedef ] +!33 = !{!"0x17\00\0022\00128\00128\000\000\000", !55, !2, i32 0, !34, null} ; [ DW_TAG_union_type ] +!34 = !{!35, !37} +!35 = !{!"0xd\00V\0023\00128\00128\000\000", !55, !15, !36} ; [ DW_TAG_member ] +!36 = !{!"0x16\00v4sf\003\000\000\000\000", !55, !2, !6} ; [ DW_TAG_typedef ] +!37 = !{!"0xd\00A\0024\00128\0032\000\000", !55, !15, !38} ; [ DW_TAG_member ] +!38 = !{!"0x1\00\000\00128\0032\000\000", null, !2, !7, !8, i32 0, i32 0} ; [ DW_TAG_array_type ] +!39 = !MDLocation(line: 79, column: 7, scope: !40) +!40 = !{!"0xb\0075\0035\0018", !54, !41} ; [ DW_TAG_lexical_block ] +!41 = !{!"0xb\0075\005\0017", !54, !42} ; [ DW_TAG_lexical_block ] +!42 = !{!"0xb\0071\0032\0016", !54, !43} ; [ DW_TAG_lexical_block ] +!43 = !{!"0xb\0071\003\0015", !54, !25} ; [ DW_TAG_lexical_block ] +!44 = !MDLocation(line: 75, column: 5, scope: !42) +!45 = !MDLocation(line: 42, column: 2, scope: !46, inlinedAt: !48) +!46 = !{!"0xb\0042\002\0020", !55, !47} ; [ DW_TAG_lexical_block ] +!47 = !{!"0xb\0041\0028\0019", !55, !14} ; [ DW_TAG_lexical_block ] +!48 = !MDLocation(line: 95, column: 3, scope: !25) +!49 = !MDLocation(line: 99, column: 3, scope: !25) +!50 = !{!0, !10, !14} +!51 = !{!18} +!52 = !{!19, !20, !24, !26, !27, !28, !29} +!53 = !{!30} +!54 = !{!"build2.c", !"/private/tmp"} +!55 = !{!"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", !"/private/tmp"} +!56 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll index 6bd7172..9b303dd 100644 --- a/test/CodeGen/ARM/debug-info-s16-reg.ll +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -1,8 +1,7 @@ ; RUN: llc < %s - | FileCheck %s ; Radar 9309221 ; Test dwarf reg no for s16 -;CHECK: super-register -;CHECK-NEXT: DW_OP_regx +;CHECK: super-register DW_OP_regx ;CHECK-NEXT: ascii ;CHECK-NEXT: DW_OP_piece ;CHECK-NEXT: 4 @@ -15,9 +14,9 @@ target triple = "thumbv7-apple-macosx10.6.7" define i32 @inlineprinter(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !8, metadata !{metadata !"0x102"}), !dbg !24 - tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !10, metadata !{metadata !"0x102"}), !dbg !25 - tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !12, metadata !{metadata !"0x102"}), !dbg !26 + tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !8, metadata !{!"0x102"}), !dbg !24 + tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !10, metadata !{!"0x102"}), !dbg !25 + tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !12, metadata !{!"0x102"}), !dbg !26 %conv = fpext float %val to double, !dbg !27 %conv3 = zext i8 %c to i32, !dbg !27 %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27 @@ -28,9 +27,9 @@ declare i32 @printf(i8* nocapture, ...) nounwind optsize define i32 @printer(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize noinline ssp { entry: - tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !14, metadata !{metadata !"0x102"}), !dbg !30 - tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !15, metadata !{metadata !"0x102"}), !dbg !31 - tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !16, metadata !{metadata !"0x102"}), !dbg !32 + tail call void @llvm.dbg.value(metadata i8* %ptr, i64 0, metadata !14, metadata !{!"0x102"}), !dbg !30 + tail call void @llvm.dbg.value(metadata float %val, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !31 + tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !32 %conv = fpext float %val to double, !dbg !33 %conv3 = zext i8 %c to i32, !dbg !33 %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33 @@ -39,19 +38,19 @@ entry: define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize ssp { entry: - tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !17, metadata !{metadata !"0x102"}), !dbg !36 - tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !18, metadata !{metadata !"0x102"}), !dbg !37 + tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !17, metadata !{!"0x102"}), !dbg !36 + tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !18, metadata !{!"0x102"}), !dbg !37 %conv = sitofp i32 %argc to double, !dbg !38 %add = fadd double %conv, 5.555552e+05, !dbg !38 %conv1 = fptrunc double %add to float, !dbg !38 - tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !22, metadata !{metadata !"0x102"}), !dbg !38 + tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !22, metadata !{!"0x102"}), !dbg !38 %call = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind optsize, !dbg !39 %add.ptr = getelementptr i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !40 %add5 = add nsw i32 %argc, 97, !dbg !40 %conv6 = trunc i32 %add5 to i8, !dbg !40 - tail call void @llvm.dbg.value(metadata !{i8* %add.ptr}, i64 0, metadata !8, metadata !{metadata !"0x102"}) nounwind, !dbg !41 - tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !10, metadata !{metadata !"0x102"}) nounwind, !dbg !42 - tail call void @llvm.dbg.value(metadata !{i8 %conv6}, i64 0, metadata !12, metadata !{metadata !"0x102"}) nounwind, !dbg !43 + tail call void @llvm.dbg.value(metadata i8* %add.ptr, i64 0, metadata !8, metadata !{!"0x102"}) nounwind, !dbg !41 + tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !10, metadata !{!"0x102"}) nounwind, !dbg !42 + tail call void @llvm.dbg.value(metadata i8 %conv6, i64 0, metadata !12, metadata !{!"0x102"}) nounwind, !dbg !43 %conv.i = fpext float %conv1 to double, !dbg !44 %conv3.i = and i32 %add5, 255, !dbg !44 %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44 @@ -66,57 +65,57 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!53} -!0 = metadata !{metadata !"0x2e\00inlineprinter\00inlineprinter\00\005\000\001\000\006\00256\001\005", metadata !51, metadata !1, metadata !3, null, i32 (i8*, float, i8)* @inlineprinter, null, null, metadata !48} ; [ DW_TAG_subprogram ] [line 5] [def] [inlineprinter] -!1 = metadata !{metadata !"0x29", metadata !51} ; [ DW_TAG_file_type ] -!2 = metadata !{metadata !"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", metadata !51, metadata !52, metadata !52, metadata !47, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !51, metadata !1, null, metadata !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!4 = metadata !{metadata !5} -!5 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, metadata !2} ; [ DW_TAG_base_type ] -!6 = metadata !{metadata !"0x2e\00printer\00printer\00\0012\000\001\000\006\00256\001\0012", metadata !51, metadata !1, metadata !3, null, i32 (i8*, float, i8)* @printer, null, null, metadata !49} ; [ DW_TAG_subprogram ] [line 12] [def] [printer] -!7 = metadata !{metadata !"0x2e\00main\00main\00\0018\000\001\000\006\00256\001\0018", metadata !51, metadata !1, metadata !3, null, i32 (i32, i8**)* @main, null, null, metadata !50} ; [ DW_TAG_subprogram ] [line 18] [def] [main] -!8 = metadata !{metadata !"0x101\00ptr\0016777220\000", metadata !0, metadata !1, metadata !9} ; [ DW_TAG_arg_variable ] -!9 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !2, null} ; [ DW_TAG_pointer_type ] -!10 = metadata !{metadata !"0x101\00val\0033554436\000", metadata !0, metadata !1, metadata !11} ; [ DW_TAG_arg_variable ] -!11 = metadata !{metadata !"0x24\00float\000\0032\0032\000\000\004", null, metadata !2} ; [ DW_TAG_base_type ] -!12 = metadata !{metadata !"0x101\00c\0050331652\000", metadata !0, metadata !1, metadata !13} ; [ DW_TAG_arg_variable ] -!13 = metadata !{metadata !"0x24\00unsigned char\000\008\008\000\000\008", null, metadata !2} ; [ DW_TAG_base_type ] -!14 = metadata !{metadata !"0x101\00ptr\0016777227\000", metadata !6, metadata !1, metadata !9} ; [ DW_TAG_arg_variable ] -!15 = metadata !{metadata !"0x101\00val\0033554443\000", metadata !6, metadata !1, metadata !11} ; [ DW_TAG_arg_variable ] -!16 = metadata !{metadata !"0x101\00c\0050331659\000", metadata !6, metadata !1, metadata !13} ; [ DW_TAG_arg_variable ] -!17 = metadata !{metadata !"0x101\00argc\0016777233\000", metadata !7, metadata !1, metadata !5} ; [ DW_TAG_arg_variable ] -!18 = metadata !{metadata !"0x101\00argv\0033554449\000", metadata !7, metadata !1, metadata !19} ; [ DW_TAG_arg_variable ] -!19 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !2, metadata !20} ; [ DW_TAG_pointer_type ] -!20 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, metadata !2, metadata !21} ; [ DW_TAG_pointer_type ] -!21 = metadata !{metadata !"0x24\00char\000\008\008\000\000\006", null, metadata !2} ; [ DW_TAG_base_type ] -!22 = metadata !{metadata !"0x100\00dval\0019\000", metadata !23, metadata !1, metadata !11} ; [ DW_TAG_auto_variable ] -!23 = metadata !{metadata !"0xb\0018\001\002", metadata !51, metadata !7} ; [ DW_TAG_lexical_block ] -!24 = metadata !{i32 4, i32 22, metadata !0, null} -!25 = metadata !{i32 4, i32 33, metadata !0, null} -!26 = metadata !{i32 4, i32 52, metadata !0, null} -!27 = metadata !{i32 6, i32 3, metadata !28, null} -!28 = metadata !{metadata !"0xb\005\001\000", metadata !51, metadata !0} ; [ DW_TAG_lexical_block ] -!29 = metadata !{i32 7, i32 3, metadata !28, null} -!30 = metadata !{i32 11, i32 42, metadata !6, null} -!31 = metadata !{i32 11, i32 53, metadata !6, null} -!32 = metadata !{i32 11, i32 72, metadata !6, null} -!33 = metadata !{i32 13, i32 3, metadata !34, null} -!34 = metadata !{metadata !"0xb\0012\001\001", metadata !51, metadata !6} ; [ DW_TAG_lexical_block ] -!35 = metadata !{i32 14, i32 3, metadata !34, null} -!36 = metadata !{i32 17, i32 15, metadata !7, null} -!37 = metadata !{i32 17, i32 28, metadata !7, null} -!38 = metadata !{i32 19, i32 31, metadata !23, null} -!39 = metadata !{i32 20, i32 3, metadata !23, null} -!40 = metadata !{i32 21, i32 3, metadata !23, null} -!41 = metadata !{i32 4, i32 22, metadata !0, metadata !40} -!42 = metadata !{i32 4, i32 33, metadata !0, metadata !40} -!43 = metadata !{i32 4, i32 52, metadata !0, metadata !40} -!44 = metadata !{i32 6, i32 3, metadata !28, metadata !40} -!45 = metadata !{i32 22, i32 3, metadata !23, null} -!46 = metadata !{i32 23, i32 1, metadata !23, null} -!47 = metadata !{metadata !0, metadata !6, metadata !7} -!48 = metadata !{metadata !8, metadata !10, metadata !12} -!49 = metadata !{metadata !14, metadata !15, metadata !16} -!50 = metadata !{metadata !17, metadata !18, metadata !22} -!51 = metadata !{metadata !"a.c", metadata !"/private/tmp"} -!52 = metadata !{i32 0} -!53 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x2e\00inlineprinter\00inlineprinter\00\005\000\001\000\006\00256\001\005", !51, !1, !3, null, i32 (i8*, float, i8)* @inlineprinter, null, null, !48} ; [ DW_TAG_subprogram ] [line 5] [def] [inlineprinter] +!1 = !{!"0x29", !51} ; [ DW_TAG_file_type ] +!2 = !{!"0x11\0012\00clang version 3.0 (trunk 129915)\001\00\000\00\001", !51, !52, !52, !47, null, null} ; [ DW_TAG_compile_unit ] +!3 = !{!"0x15\00\000\000\000\000\000\000", !51, !1, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !{!5} +!5 = !{!"0x24\00int\000\0032\0032\000\000\005", null, !2} ; [ DW_TAG_base_type ] +!6 = !{!"0x2e\00printer\00printer\00\0012\000\001\000\006\00256\001\0012", !51, !1, !3, null, i32 (i8*, float, i8)* @printer, null, null, !49} ; [ DW_TAG_subprogram ] [line 12] [def] [printer] +!7 = !{!"0x2e\00main\00main\00\0018\000\001\000\006\00256\001\0018", !51, !1, !3, null, i32 (i32, i8**)* @main, null, null, !50} ; [ DW_TAG_subprogram ] [line 18] [def] [main] +!8 = !{!"0x101\00ptr\0016777220\000", !0, !1, !9} ; [ DW_TAG_arg_variable ] +!9 = !{!"0xf\00\000\0032\0032\000\000", null, !2, null} ; [ DW_TAG_pointer_type ] +!10 = !{!"0x101\00val\0033554436\000", !0, !1, !11} ; [ DW_TAG_arg_variable ] +!11 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !2} ; [ DW_TAG_base_type ] +!12 = !{!"0x101\00c\0050331652\000", !0, !1, !13} ; [ DW_TAG_arg_variable ] +!13 = !{!"0x24\00unsigned char\000\008\008\000\000\008", null, !2} ; [ DW_TAG_base_type ] +!14 = !{!"0x101\00ptr\0016777227\000", !6, !1, !9} ; [ DW_TAG_arg_variable ] +!15 = !{!"0x101\00val\0033554443\000", !6, !1, !11} ; [ DW_TAG_arg_variable ] +!16 = !{!"0x101\00c\0050331659\000", !6, !1, !13} ; [ DW_TAG_arg_variable ] +!17 = !{!"0x101\00argc\0016777233\000", !7, !1, !5} ; [ DW_TAG_arg_variable ] +!18 = !{!"0x101\00argv\0033554449\000", !7, !1, !19} ; [ DW_TAG_arg_variable ] +!19 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !20} ; [ DW_TAG_pointer_type ] +!20 = !{!"0xf\00\000\0032\0032\000\000", null, !2, !21} ; [ DW_TAG_pointer_type ] +!21 = !{!"0x24\00char\000\008\008\000\000\006", null, !2} ; [ DW_TAG_base_type ] +!22 = !{!"0x100\00dval\0019\000", !23, !1, !11} ; [ DW_TAG_auto_variable ] +!23 = !{!"0xb\0018\001\002", !51, !7} ; [ DW_TAG_lexical_block ] +!24 = !MDLocation(line: 4, column: 22, scope: !0) +!25 = !MDLocation(line: 4, column: 33, scope: !0) +!26 = !MDLocation(line: 4, column: 52, scope: !0) +!27 = !MDLocation(line: 6, column: 3, scope: !28) +!28 = !{!"0xb\005\001\000", !51, !0} ; [ DW_TAG_lexical_block ] +!29 = !MDLocation(line: 7, column: 3, scope: !28) +!30 = !MDLocation(line: 11, column: 42, scope: !6) +!31 = !MDLocation(line: 11, column: 53, scope: !6) +!32 = !MDLocation(line: 11, column: 72, scope: !6) +!33 = !MDLocation(line: 13, column: 3, scope: !34) +!34 = !{!"0xb\0012\001\001", !51, !6} ; [ DW_TAG_lexical_block ] +!35 = !MDLocation(line: 14, column: 3, scope: !34) +!36 = !MDLocation(line: 17, column: 15, scope: !7) +!37 = !MDLocation(line: 17, column: 28, scope: !7) +!38 = !MDLocation(line: 19, column: 31, scope: !23) +!39 = !MDLocation(line: 20, column: 3, scope: !23) +!40 = !MDLocation(line: 21, column: 3, scope: !23) +!41 = !MDLocation(line: 4, column: 22, scope: !0, inlinedAt: !40) +!42 = !MDLocation(line: 4, column: 33, scope: !0, inlinedAt: !40) +!43 = !MDLocation(line: 4, column: 52, scope: !0, inlinedAt: !40) +!44 = !MDLocation(line: 6, column: 3, scope: !28, inlinedAt: !40) +!45 = !MDLocation(line: 22, column: 3, scope: !23) +!46 = !MDLocation(line: 23, column: 1, scope: !23) +!47 = !{!0, !6, !7} +!48 = !{!8, !10, !12} +!49 = !{!14, !15, !16} +!50 = !{!17, !18, !22} +!51 = !{!"a.c", !"/private/tmp"} +!52 = !{i32 0} +!53 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll index 4374b9e..977a6f2 100644 --- a/test/CodeGen/ARM/debug-info-sreg2.ll +++ b/test/CodeGen/ARM/debug-info-sreg2.ll @@ -15,7 +15,7 @@ target triple = "thumbv7-apple-macosx10.6.7" define void @_Z3foov() optsize ssp { entry: %call = tail call float @_Z3barv() optsize, !dbg !11 - tail call void @llvm.dbg.value(metadata !{float %call}, i64 0, metadata !5, metadata !{metadata !"0x102"}), !dbg !11 + tail call void @llvm.dbg.value(metadata float %call, i64 0, metadata !5, metadata !{!"0x102"}), !dbg !11 %call16 = tail call float @_Z2f2v() optsize, !dbg !12 %cmp7 = fcmp olt float %call, %call16, !dbg !12 br i1 %cmp7, label %for.body, label %for.end, !dbg !12 @@ -43,24 +43,24 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!20} -!0 = metadata !{metadata !"0x11\004\00clang version 3.0 (trunk 130845)\001\00\000\00\001", metadata !18, metadata !19, metadata !19, metadata !16, null, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{metadata !"0x2e\00foo\00foo\00_Z3foov\005\000\001\000\006\00256\001\005", metadata !18, metadata !2, metadata !3, null, void ()* @_Z3foov, null, null, metadata !17} ; [ DW_TAG_subprogram ] [line 5] [def] [foo] -!2 = metadata !{metadata !"0x29", metadata !18} ; [ DW_TAG_file_type ] -!3 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", metadata !18, metadata !2, null, metadata !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!4 = metadata !{null} -!5 = metadata !{metadata !"0x100\00k\006\000", metadata !6, metadata !2, metadata !7} ; [ DW_TAG_auto_variable ] -!6 = metadata !{metadata !"0xb\005\0012\000", metadata !18, metadata !1} ; [ DW_TAG_lexical_block ] -!7 = metadata !{metadata !"0x24\00float\000\0032\0032\000\000\004", null, metadata !0} ; [ DW_TAG_base_type ] -!8 = metadata !{metadata !"0x100\00y\008\000", metadata !9, metadata !2, metadata !7} ; [ DW_TAG_auto_variable ] -!9 = metadata !{metadata !"0xb\007\0025\002", metadata !18, metadata !10} ; [ DW_TAG_lexical_block ] -!10 = metadata !{metadata !"0xb\007\003\001", metadata !18, metadata !6} ; [ DW_TAG_lexical_block ] -!11 = metadata !{i32 6, i32 18, metadata !6, null} -!12 = metadata !{i32 7, i32 3, metadata !6, null} -!13 = metadata !{i32 8, i32 20, metadata !9, null} -!14 = metadata !{i32 7, i32 20, metadata !10, null} -!15 = metadata !{i32 10, i32 1, metadata !6, null} -!16 = metadata !{metadata !1} -!17 = metadata !{metadata !5, metadata !8} -!18 = metadata !{metadata !"k.cc", metadata !"/private/tmp"} -!19 = metadata !{i32 0} -!20 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x11\004\00clang version 3.0 (trunk 130845)\001\00\000\00\001", !18, !19, !19, !16, null, null} ; [ DW_TAG_compile_unit ] +!1 = !{!"0x2e\00foo\00foo\00_Z3foov\005\000\001\000\006\00256\001\005", !18, !2, !3, null, void ()* @_Z3foov, null, null, !17} ; [ DW_TAG_subprogram ] [line 5] [def] [foo] +!2 = !{!"0x29", !18} ; [ DW_TAG_file_type ] +!3 = !{!"0x15\00\000\000\000\000\000\000", !18, !2, null, !4, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!4 = !{null} +!5 = !{!"0x100\00k\006\000", !6, !2, !7} ; [ DW_TAG_auto_variable ] +!6 = !{!"0xb\005\0012\000", !18, !1} ; [ DW_TAG_lexical_block ] +!7 = !{!"0x24\00float\000\0032\0032\000\000\004", null, !0} ; [ DW_TAG_base_type ] +!8 = !{!"0x100\00y\008\000", !9, !2, !7} ; [ DW_TAG_auto_variable ] +!9 = !{!"0xb\007\0025\002", !18, !10} ; [ DW_TAG_lexical_block ] +!10 = !{!"0xb\007\003\001", !18, !6} ; [ DW_TAG_lexical_block ] +!11 = !MDLocation(line: 6, column: 18, scope: !6) +!12 = !MDLocation(line: 7, column: 3, scope: !6) +!13 = !MDLocation(line: 8, column: 20, scope: !9) +!14 = !MDLocation(line: 7, column: 20, scope: !10) +!15 = !MDLocation(line: 10, column: 1, scope: !6) +!16 = !{!1} +!17 = !{!5, !8} +!18 = !{!"k.cc", !"/private/tmp"} +!19 = !{i32 0} +!20 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/debug-segmented-stacks.ll b/test/CodeGen/ARM/debug-segmented-stacks.ll index 2123fa7..7ea5665 100644 --- a/test/CodeGen/ARM/debug-segmented-stacks.ll +++ b/test/CodeGen/ARM/debug-segmented-stacks.ll @@ -39,40 +39,40 @@ define void @test_basic() #0 { ; ARM-linux .cfi_same_value r5 } -!0 = metadata !{metadata !"0x11\0012\00clang version 3.5 \000\00\000\00\000", metadata !1, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2} ; [ DW_TAG_compile_unit ] [/tmp/var.c] [DW_LANG_C99] -!1 = metadata !{metadata !"var.c", metadata !"/tmp"} -!2 = metadata !{} -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !"0x2e\00test_basic\00test_basic\00\005\000\001\000\006\00256\000\005", metadata !1, metadata !5, metadata !6, null, void ()* @test_basic, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 5] [def] [sum] -!5 = metadata !{metadata !"0x29", metadata !1} ; [ DW_TAG_file_type ] [/tmp/var.c] -!6 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!7 = metadata !{metadata !8, metadata !8} -!8 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] -!9 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} -!10 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} -!11 = metadata !{metadata !"clang version 3.5 "} -!12 = metadata !{metadata !"0x101\00count\0016777221\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [count] [line 5] -!13 = metadata !{i32 5, i32 0, metadata !4, null} -!14 = metadata !{metadata !"0x100\00vl\006\000", metadata !4, metadata !5, metadata !15} ; [ DW_TAG_auto_variable ] [vl] [line 6] -!15 = metadata !{metadata !"0x16\00va_list\0030\000\000\000\000", metadata !16, null, metadata !17} ; [ DW_TAG_typedef ] [va_list] [line 30, size 0, align 0, offset 0] [from __builtin_va_list] -!16 = metadata !{metadata !"/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", metadata !"/tmp"} -!17 = metadata !{metadata !"0x16\00__builtin_va_list\006\000\000\000\000", metadata !1, null, metadata !18} ; [ DW_TAG_typedef ] [__builtin_va_list] [line 6, size 0, align 0, offset 0] [from __va_list] -!18 = metadata !{metadata !"0x13\00__va_list\006\0032\0032\000\000\000", metadata !1, null, null, metadata !19, null, null, null} ; [ DW_TAG_structure_type ] [__va_list] [line 6, size 32, align 32, offset 0] [def] [from ] -!19 = metadata !{metadata !20} -!20 = metadata !{metadata !"0xd\00__ap\006\0032\0032\000\000", metadata !1, metadata !18, metadata !21} ; [ DW_TAG_member ] [__ap] [line 6, size 32, align 32, offset 0] [from ] -!21 = metadata !{metadata !"0xf\00\000\0032\0032\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from ] -!22 = metadata !{i32 6, i32 0, metadata !4, null} -!23 = metadata !{i32 7, i32 0, metadata !4, null} -!24 = metadata !{metadata !"0x100\00test_basic\008\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [sum] [line 8] -!25 = metadata !{i32 8, i32 0, metadata !4, null} -!26 = metadata !{metadata !"0x100\00i\009\000", metadata !27, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 9] -!27 = metadata !{metadata !"0xb\009\000\000", metadata !1, metadata !4} ; [ DW_TAG_lexical_block ] [/tmp/var.c] -!28 = metadata !{i32 9, i32 0, metadata !27, null} -!29 = metadata !{i32 10, i32 0, metadata !30, null} -!30 = metadata !{metadata !"0xb\009\000\001", metadata !1, metadata !27} ; [ DW_TAG_lexical_block ] [/tmp/var.c] -!31 = metadata !{i32 11, i32 0, metadata !30, null} -!32 = metadata !{i32 12, i32 0, metadata !4, null} -!33 = metadata !{i32 13, i32 0, metadata !4, null} +!0 = !{!"0x11\0012\00clang version 3.5 \000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/var.c] [DW_LANG_C99] +!1 = !{!"var.c", !"/tmp"} +!2 = !{} +!3 = !{!4} +!4 = !{!"0x2e\00test_basic\00test_basic\00\005\000\001\000\006\00256\000\005", !1, !5, !6, null, void ()* @test_basic, null, null, !2} ; [ DW_TAG_subprogram ] [line 5] [def] [sum] +!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/tmp/var.c] +!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = !{!8, !8} +!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = !{i32 2, !"Dwarf Version", i32 4} +!10 = !{i32 1, !"Debug Info Version", i32 2} +!11 = !{!"clang version 3.5 "} +!12 = !{!"0x101\00count\0016777221\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [count] [line 5] +!13 = !MDLocation(line: 5, scope: !4) +!14 = !{!"0x100\00vl\006\000", !4, !5, !15} ; [ DW_TAG_auto_variable ] [vl] [line 6] +!15 = !{!"0x16\00va_list\0030\000\000\000\000", !16, null, !17} ; [ DW_TAG_typedef ] [va_list] [line 30, size 0, align 0, offset 0] [from __builtin_va_list] +!16 = !{!"/linux-x86_64-high/gcc_4.7.2/dbg/llvm/bin/../lib/clang/3.5/include/stdarg.h", !"/tmp"} +!17 = !{!"0x16\00__builtin_va_list\006\000\000\000\000", !1, null, !18} ; [ DW_TAG_typedef ] [__builtin_va_list] [line 6, size 0, align 0, offset 0] [from __va_list] +!18 = !{!"0x13\00__va_list\006\0032\0032\000\000\000", !1, null, null, !19, null, null, null} ; [ DW_TAG_structure_type ] [__va_list] [line 6, size 32, align 32, offset 0] [def] [from ] +!19 = !{!20} +!20 = !{!"0xd\00__ap\006\0032\0032\000\000", !1, !18, !21} ; [ DW_TAG_member ] [__ap] [line 6, size 32, align 32, offset 0] [from ] +!21 = !{!"0xf\00\000\0032\0032\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 32, align 32, offset 0] [from ] +!22 = !MDLocation(line: 6, scope: !4) +!23 = !MDLocation(line: 7, scope: !4) +!24 = !{!"0x100\00test_basic\008\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [sum] [line 8] +!25 = !MDLocation(line: 8, scope: !4) +!26 = !{!"0x100\00i\009\000", !27, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 9] +!27 = !{!"0xb\009\000\000", !1, !4} ; [ DW_TAG_lexical_block ] [/tmp/var.c] +!28 = !MDLocation(line: 9, scope: !27) +!29 = !MDLocation(line: 10, scope: !30) +!30 = !{!"0xb\009\000\001", !1, !27} ; [ DW_TAG_lexical_block ] [/tmp/var.c] +!31 = !MDLocation(line: 11, scope: !30) +!32 = !MDLocation(line: 12, scope: !4) +!33 = !MDLocation(line: 13, scope: !4) ; Just to prevent the alloca from being optimized away declare void @dummy_use(i32*, i32) diff --git a/test/CodeGen/ARM/dyn-stackalloc.ll b/test/CodeGen/ARM/dyn-stackalloc.ll index 4ac5b8a..05c143d 100644 --- a/test/CodeGen/ARM/dyn-stackalloc.ll +++ b/test/CodeGen/ARM/dyn-stackalloc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=arm-eabi %s -o /dev/null +; RUN: llc -mcpu=generic -mtriple=arm-eabi -verify-machineinstrs < %s | FileCheck %s %struct.comment = type { i8**, i32*, i32, i8* } %struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* } @@ -7,6 +7,18 @@ @str215 = external global [2 x i8] define void @t1(%struct.state* %v) { + +; Make sure we generate: +; sub sp, sp, r1 +; instead of: +; sub r1, sp, r1 +; mov sp, r1 + +; CHECK-LABEL: @t1 +; CHECK: bic [[REG1:r[0-9]+]], +; CHECK-NOT: sub r{{[0-9]+}}, sp, [[REG1]] +; CHECK: sub sp, sp, [[REG1]] + %tmp6 = load i32* null %tmp8 = alloca float, i32 %tmp6 store i32 1, i32* null diff --git a/test/CodeGen/ARM/emit-big-cst.ll b/test/CodeGen/ARM/emit-big-cst.ll index 9a3367d..01d789c 100644 --- a/test/CodeGen/ARM/emit-big-cst.ll +++ b/test/CodeGen/ARM/emit-big-cst.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv7-unknown-unknown < %s | FileCheck %s +; RUN: llc -mtriple=thumbv7-unknown-unknown -target-abi apcs < %s | FileCheck %s ; Check assembly printing of odd constants. ; CHECK: bigCst: diff --git a/test/CodeGen/ARM/fold-stack-adjust.ll b/test/CodeGen/ARM/fold-stack-adjust.ll index 514d4a9..c5ff82e 100644 --- a/test/CodeGen/ARM/fold-stack-adjust.ll +++ b/test/CodeGen/ARM/fold-stack-adjust.ll @@ -71,7 +71,7 @@ define void @check_vfp_fold() minsize { ; CHECK-IOS-LABEL: check_vfp_fold: ; CHECK-IOS: push {r0, r1, r2, r3, r4, r7, lr} ; CHECK-IOS: sub.w r4, sp, #16 -; CHECK-IOS: bic r4, r4, #15 +; CHECK-IOS: bfc r4, #0, #4 ; CHECK-IOS: mov sp, r4 ; CHECK-IOS: vst1.64 {d8, d9}, [r4:128] ; ... diff --git a/test/CodeGen/ARM/frame-register.ll b/test/CodeGen/ARM/frame-register.ll index e6a55bd..b04e376 100644 --- a/test/CodeGen/ARM/frame-register.ll +++ b/test/CodeGen/ARM/frame-register.ll @@ -30,9 +30,9 @@ entry: ; CHECK-ARM: push {r11, lr} ; CHECK-ARM: mov r11, sp -; CHECK-THUMB: push {r4, r6, r7, lr} -; CHECK-THUMB: add r7, sp, #8 +; CHECK-THUMB: push {r7, lr} +; CHECK-THUMB: add r7, sp, #0 ; CHECK-DARWIN-ARM: push {r7, lr} -; CHECK-DARWIN-THUMB: push {r4, r7, lr} +; CHECK-DARWIN-THUMB: push {r7, lr} diff --git a/test/CodeGen/ARM/ghc-tcreturn-lowered.ll b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll new file mode 100644 index 0000000..623b422 --- /dev/null +++ b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=thumbv7-eabi -o - %s | FileCheck %s + +declare ghccc void @g() + +define ghccc void @test_direct_tail() { +; CHECK-LABEL: test_direct_tail: +; CHECK: b g + + tail call ghccc void @g() + ret void +} + +@ind_func = global void()* zeroinitializer + +define ghccc void @test_indirect_tail() { +; CHECK-LABEL: test_indirect_tail: +; CHECK: bx {{r[0-9]+}} + %func = load void()** @ind_func + tail call ghccc void()* %func() + ret void +} diff --git a/test/CodeGen/ARM/global-merge-1.ll b/test/CodeGen/ARM/global-merge-1.ll index 341597e..e5d4def 100644 --- a/test/CodeGen/ARM/global-merge-1.ll +++ b/test/CodeGen/ARM/global-merge-1.ll @@ -78,8 +78,8 @@ attributes #3 = { nounwind } !llvm.ident = !{!0} -!0 = metadata !{metadata !"LLVM version 3.4 "} -!1 = metadata !{metadata !2, metadata !2, i64 0} -!2 = metadata !{metadata !"int", metadata !3, i64 0} -!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0} -!4 = metadata !{metadata !"Simple C/C++ TBAA"} +!0 = !{!"LLVM version 3.4 "} +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index 3101500..2c599bf 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -43,6 +43,7 @@ define i32 @test1() { ; DarwinPIC: LPC0_0: ; DarwinPIC: ldr r0, [pc, r0] ; DarwinPIC: ldr r0, [r0] +; DarwinPIC-NOT: ldr ; DarwinPIC: bx lr ; DarwinPIC: .align 2 diff --git a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll index 5d8e477..f76fd30 100644 --- a/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll +++ b/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll @@ -59,5 +59,5 @@ declare %classL* @_ZN1M1JI1LS1_EcvPS1_Ev(%classM2*) declare void @_ZN1F10handleMoveEb(%classF*, i1 zeroext) declare void @_Z3fn1v() -!0 = metadata !{metadata !"clang version 3.5"} -!1 = metadata !{metadata !"branch_weights", i32 62, i32 62} +!0 = !{!"clang version 3.5"} +!1 = !{!"branch_weights", i32 62, i32 62} diff --git a/test/CodeGen/ARM/ifcvt-branch-weight.ll b/test/CodeGen/ARM/ifcvt-branch-weight.ll index a994d3d..2d12a89 100644 --- a/test/CodeGen/ARM/ifcvt-branch-weight.ll +++ b/test/CodeGen/ARM/ifcvt-branch-weight.ll @@ -38,5 +38,5 @@ return: ret i8 1 } -!0 = metadata !{metadata !"branch_weights", i32 4, i32 12} -!1 = metadata !{metadata !"branch_weights", i32 8, i32 16} +!0 = !{!"branch_weights", i32 4, i32 12} +!1 = !{!"branch_weights", i32 8, i32 16} diff --git a/test/CodeGen/ARM/inline-diagnostics.ll b/test/CodeGen/ARM/inline-diagnostics.ll index 7b77da2..0276abf 100644 --- a/test/CodeGen/ARM/inline-diagnostics.ll +++ b/test/CodeGen/ARM/inline-diagnostics.ll @@ -13,4 +13,4 @@ define float @inline_func(float %f1, float %f2) #0 { ret float %1 } -!1 = metadata !{i32 271, i32 305} +!1 = !{i32 271, i32 305} diff --git a/test/CodeGen/ARM/interrupt-attr.ll b/test/CodeGen/ARM/interrupt-attr.ll index 96d1ee2..c6da09d 100644 --- a/test/CodeGen/ARM/interrupt-attr.ll +++ b/test/CodeGen/ARM/interrupt-attr.ll @@ -15,7 +15,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: add r11, sp, #20 ; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; CHECK-A: bl bar ; CHECK-A: sub sp, r11, #20 ; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} @@ -25,7 +25,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-A-THUMB: push.w {r0, r1, r2, r3, r4, r7, r12, lr} ; CHECK-A-THUMB: add r7, sp, #20 ; CHECK-A-THUMB: mov r4, sp -; CHECK-A-THUMB: bic r4, r4, #7 +; CHECK-A-THUMB: bfc r4, #0, #3 ; CHECK-A-THUMB: bl bar ; CHECK-A-THUMB: sub.w r4, r7, #20 ; CHECK-A-THUMB: mov sp, r4 @@ -38,7 +38,7 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; CHECK-M: push.w {r4, r10, r11, lr} ; CHECK-M: add.w r11, sp, #8 ; CHECK-M: mov r4, sp -; CHECK-M: bic r4, r4, #7 +; CHECK-M: bfc r4, #0, #3 ; CHECK-M: mov sp, r4 ; CHECK-M: bl _bar ; CHECK-M: sub.w r4, r11, #8 @@ -56,7 +56,7 @@ define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" { ; 32 to get past r0, r1, ..., r7 ; CHECK-A: add r11, sp, #32 ; CHECK-A: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; [...] ; 32 must match above ; CHECK-A: sub sp, r11, #32 @@ -75,7 +75,7 @@ define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" { ; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} ; CHECK-A: add r11, sp, #44 ; CHECK-A: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; [...] ; CHECK-A: sub sp, r11, #44 ; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} @@ -91,7 +91,7 @@ define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" { ; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: add r11, sp, #20 ; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; [...] ; CHECK-A: sub sp, r11, #20 ; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} @@ -106,7 +106,7 @@ define arm_aapcscc void @abort_fn() alignstack(8) "interrupt"="ABORT" { ; CHECK-A: push {r0, r1, r2, r3, r10, r11, r12, lr} ; CHECK-A: add r11, sp, #20 ; CHECK-A-NOT: sub sp, sp, #{{[0-9]+}} -; CHECK-A: bic sp, sp, #7 +; CHECK-A: bfc sp, #0, #3 ; [...] ; CHECK-A: sub sp, r11, #20 ; CHECK-A: pop {r0, r1, r2, r3, r10, r11, r12, lr} diff --git a/test/CodeGen/ARM/isel-v8i32-crash.ll b/test/CodeGen/ARM/isel-v8i32-crash.ll new file mode 100644 index 0000000..0116fe8 --- /dev/null +++ b/test/CodeGen/ARM/isel-v8i32-crash.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -mtriple=armv7-linux-gnu | FileCheck %s + +; Check we don't crash when trying to combine: +; (d1 = ) (power of 2) +; vmul.f32 d0, d1, d0 +; vcvt.s32.f32 d0, d0 +; into: +; vcvt.s32.f32 d0, d0, #3 +; when we have a vector length of 8, due to use of v8i32 types. + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" + +; CHECK: func: +; CHECK: vcvt.s32.f32 q[[R:[0-9]]], q[[R]], #3 +define void @func(i16* nocapture %pb, float* nocapture readonly %pf) #0 { +entry: + %0 = bitcast float* %pf to <8 x float>* + %1 = load <8 x float>* %0, align 4 + %2 = fmul <8 x float> %1, + %3 = fptosi <8 x float> %2 to <8 x i16> + %4 = bitcast i16* %pb to <8 x i16>* + store <8 x i16> %3, <8 x i16>* %4, align 2 + ret void +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/ARM/krait-cpu-div-attribute.ll b/test/CodeGen/ARM/krait-cpu-div-attribute.ll new file mode 100644 index 0000000..b7a1dcc --- /dev/null +++ b/test/CodeGen/ARM/krait-cpu-div-attribute.ll @@ -0,0 +1,36 @@ +; Tests the genration of ".arch_extension" attribute for hardware +; division on krait CPU. For now, krait is recognized as "cortex-a9" + hwdiv +; Also, tests for the hwdiv instruction on krait CPU + +; check for arch_extension/cpu directive +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait | FileCheck %s --check-prefix=DIV_EXTENSION +; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=krait | FileCheck %s --check-prefix=DIV_EXTENSION +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=NODIV_KRAIT +; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-a9 | FileCheck %s --check-prefix=NODIV_KRAIT +; RUN: llc < %s -mcpu=krait -mattr=-hwdiv,-hwdiv-arm | FileCheck %s --check-prefix=NODIV_KRAIT + +; check if correct instruction is emitted by integrated assembler +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump -mcpu=krait -triple armv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV +; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=krait -filetype=obj | llvm-objdump -mcpu=krait -triple thumbv7-linux-gnueabi -d - | FileCheck %s --check-prefix=HWDIV + +; arch_extension attribute +; DIV_EXTENSION: .cpu cortex-a9 +; DIV_EXTENSION: .arch_extension idiv +; NODIV_KRAIT-NOT: .arch_extension idiv +; HWDIV: sdiv + +define i32 @main() #0 { +entry: + %retval = alloca i32, align 4 + %a = alloca i32, align 4 + %b = alloca i32, align 4 + %c = alloca i32, align 4 + store i32 0, i32* %retval + store volatile i32 100, i32* %b, align 4 + store volatile i32 32, i32* %c, align 4 + %0 = load volatile i32* %b, align 4 + %1 = load volatile i32* %c, align 4 + %div = sdiv i32 %0, %1 + store volatile i32 %div, i32* %a, align 4 + ret i32 0 +} diff --git a/test/CodeGen/ARM/longMAC.ll b/test/CodeGen/ARM/longMAC.ll index fed6ec0..3f30fd4 100644 --- a/test/CodeGen/ARM/longMAC.ll +++ b/test/CodeGen/ARM/longMAC.ll @@ -75,3 +75,44 @@ define i64 @MACLongTest5(i64 %c, i32 %a, i32 %b) { %add = add i64 %mul, %c ret i64 %add } + +define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) { +;CHECK-LABEL: MACLongTest6: +;CHECK: smull r12, lr, r1, r0 +;CHECK: smlal r12, lr, r3, r2 + %conv = sext i32 %a to i64 + %conv1 = sext i32 %b to i64 + %mul = mul nsw i64 %conv1, %conv + %conv2 = sext i32 %c to i64 + %conv3 = sext i32 %d to i64 + %mul4 = mul nsw i64 %conv3, %conv2 + %add = add nsw i64 %mul4, %mul + ret i64 %add +} + +define i64 @MACLongTest7(i64 %acc, i32 %lhs, i32 %rhs) { +;CHECK-LABEL: MACLongTest7: +;CHECK-NOT: smlal + %conv = sext i32 %lhs to i64 + %conv1 = sext i32 %rhs to i64 + %mul = mul nsw i64 %conv1, %conv + %shl = shl i64 %mul, 32 + %shr = lshr i64 %mul, 32 + %or = or i64 %shl, %shr + %add = add i64 %or, %acc + ret i64 %add +} + +define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) { +;CHECK-LABEL: MACLongTest8: +;CHECK-NOT: smlal + %conv = zext i32 %lhs to i64 + %conv1 = zext i32 %rhs to i64 + %mul = mul nuw i64 %conv1, %conv + %and = and i64 %mul, 4294967295 + %shl = shl i64 %mul, 32 + %or = or i64 %and, %shl + %add = add i64 %or, %acc + ret i64 %add +} + diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll index 84ce4a7..33ac4e1 100644 --- a/test/CodeGen/ARM/memcpy-inline.ll +++ b/test/CodeGen/ARM/memcpy-inline.ll @@ -46,10 +46,8 @@ entry: ; CHECK: movw [[REG2:r[0-9]+]], #16716 ; CHECK: movt [[REG2:r[0-9]+]], #72 ; CHECK: str [[REG2]], [r0, #32] -; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] -; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] -; CHECK: adds r0, #16 -; CHECK: adds r1, #16 +; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]! +; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]! ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8]* @.str2, i64 0, i64 0), i64 36, i32 1, i1 false) @@ -59,10 +57,8 @@ entry: define void @t3(i8* nocapture %C) nounwind { entry: ; CHECK-LABEL: t3: -; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] -; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] -; CHECK: adds r0, #16 -; CHECK: adds r1, #16 +; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]! +; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]! ; CHECK: vld1.8 {d{{[0-9]+}}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}}, [r0] tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8]* @.str3, i64 0, i64 0), i64 24, i32 1, i1 false) @@ -73,7 +69,8 @@ define void @t4(i8* nocapture %C) nounwind { entry: ; CHECK-LABEL: t4: ; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1] -; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0] +; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]! +; CHECK: strh [[REG5:r[0-9]+]], [r0] tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false) ret void } diff --git a/test/CodeGen/ARM/metadata-default.ll b/test/CodeGen/ARM/metadata-default.ll index f6a3fe2..f8e40b4 100644 --- a/test/CodeGen/ARM/metadata-default.ll +++ b/test/CodeGen/ARM/metadata-default.ll @@ -9,8 +9,8 @@ define i32 @f(i64 %z) { !llvm.module.flags = !{!0, !1} -!0 = metadata !{i32 1, metadata !"wchar_size", i32 4} -!1 = metadata !{i32 1, metadata !"min_enum_size", i32 4} +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"min_enum_size", i32 4} ; CHECK: .eabi_attribute 18, 4 @ Tag_ABI_PCS_wchar_t ; CHECK: .eabi_attribute 26, 2 @ Tag_ABI_enum_size diff --git a/test/CodeGen/ARM/metadata-short-enums.ll b/test/CodeGen/ARM/metadata-short-enums.ll index bccd332..2f1586d 100644 --- a/test/CodeGen/ARM/metadata-short-enums.ll +++ b/test/CodeGen/ARM/metadata-short-enums.ll @@ -9,8 +9,8 @@ define i32 @f(i64 %z) { !llvm.module.flags = !{!0, !1} -!0 = metadata !{i32 1, metadata !"wchar_size", i32 4} -!1 = metadata !{i32 1, metadata !"min_enum_size", i32 1} +!0 = !{i32 1, !"wchar_size", i32 4} +!1 = !{i32 1, !"min_enum_size", i32 1} ; CHECK: .eabi_attribute 18, 4 @ Tag_ABI_PCS_wchar_t ; CHECK: .eabi_attribute 26, 1 @ Tag_ABI_enum_size diff --git a/test/CodeGen/ARM/metadata-short-wchar.ll b/test/CodeGen/ARM/metadata-short-wchar.ll index 6de9bf1..b7f5833 100644 --- a/test/CodeGen/ARM/metadata-short-wchar.ll +++ b/test/CodeGen/ARM/metadata-short-wchar.ll @@ -9,8 +9,8 @@ define i32 @f(i64 %z) { !llvm.module.flags = !{!0, !1} -!0 = metadata !{i32 1, metadata !"wchar_size", i32 2} -!1 = metadata !{i32 1, metadata !"min_enum_size", i32 4} +!0 = !{i32 1, !"wchar_size", i32 2} +!1 = !{i32 1, !"min_enum_size", i32 4} ; CHECK: .eabi_attribute 18, 2 @ Tag_ABI_PCS_wchar_t ; CHECK: .eabi_attribute 26, 2 @ Tag_ABI_enum_size diff --git a/test/CodeGen/ARM/named-reg-alloc.ll b/test/CodeGen/ARM/named-reg-alloc.ll index 3c27d22..380cf39 100644 --- a/test/CodeGen/ARM/named-reg-alloc.ll +++ b/test/CodeGen/ARM/named-reg-alloc.ll @@ -11,4 +11,4 @@ entry: declare i32 @llvm.read_register.i32(metadata) nounwind -!0 = metadata !{metadata !"r5\00"} +!0 = !{!"r5\00"} diff --git a/test/CodeGen/ARM/named-reg-notareg.ll b/test/CodeGen/ARM/named-reg-notareg.ll index af38b60..3ac03f4 100644 --- a/test/CodeGen/ARM/named-reg-notareg.ll +++ b/test/CodeGen/ARM/named-reg-notareg.ll @@ -10,4 +10,4 @@ entry: declare i32 @llvm.read_register.i32(metadata) nounwind -!0 = metadata !{metadata !"notareg\00"} +!0 = !{!"notareg\00"} diff --git a/test/CodeGen/ARM/none-macho-v4t.ll b/test/CodeGen/ARM/none-macho-v4t.ll index 4c6e68e..b6018de 100644 --- a/test/CodeGen/ARM/none-macho-v4t.ll +++ b/test/CodeGen/ARM/none-macho-v4t.ll @@ -11,11 +11,15 @@ define void @test_call() { ; CHECK: [[PC_LABEL:LPC[0-9]+_[0-9]+]]: ; CHECK-NEXT: add r[[CALLEE_STUB]], pc ; CHECK: ldr [[CALLEE:r[0-9]+]], [r[[CALLEE_STUB]]] -; CHECK: mov lr, pc -; CHECK: bx [[CALLEE]] +; CHECK-NOT: mov lr, pc +; CHECK: bl [[INDIRECT_PAD:Ltmp[0-9]+]] ; CHECK: [[LITPOOL]]: ; CHECK-NEXT: .long L_callee$non_lazy_ptr-([[PC_LABEL]]+4) + +; CHECK: [[INDIRECT_PAD]]: +; CHECK: bx [[CALLEE]] + call void @callee() ret void } diff --git a/test/CodeGen/ARM/null-streamer.ll b/test/CodeGen/ARM/null-streamer.ll index 350c45e..19ad22a 100644 --- a/test/CodeGen/ARM/null-streamer.ll +++ b/test/CodeGen/ARM/null-streamer.ll @@ -5,3 +5,5 @@ define i32 @main() { entry: ret i32 0 } + +module asm ".fnstart" diff --git a/test/CodeGen/ARM/odr_comdat.ll b/test/CodeGen/ARM/odr_comdat.ll deleted file mode 100644 index e28b578..0000000 --- a/test/CodeGen/ARM/odr_comdat.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ARMGNUEABI - -; Checking that a comdat group gets generated correctly for a static member -; of instantiated C++ templates. -; see http://sourcery.mentor.com/public/cxx-abi/abi.html#vague-itemplate -; section 5.2.6 Instantiated templates -; "Any static member data object is emitted in a COMDAT identified by its mangled -; name, in any object file with a reference to its name symbol." - -; Case 1: variable is not explicitly initialized, and ends up in a .bss section -; ARMGNUEABI: .section .bss._ZN1CIiE1iE,"aGw",%nobits,_ZN1CIiE1iE,comdat -@_ZN1CIiE1iE = weak_odr global i32 0, align 4 - -; Case 2: variable is explicitly initialized, and ends up in a .data section -; ARMGNUEABI: .section .data._ZN1CIiE1jE,"aGw",%progbits,_ZN1CIiE1jE,comdat -@_ZN1CIiE1jE = weak_odr global i32 12, align 4 diff --git a/test/CodeGen/ARM/out-of-registers.ll b/test/CodeGen/ARM/out-of-registers.ll index 790e416..a83923d 100644 --- a/test/CodeGen/ARM/out-of-registers.ll +++ b/test/CodeGen/ARM/out-of-registers.ll @@ -38,5 +38,5 @@ attributes #2 = { nounwind readonly } !llvm.ident = !{!0} -!0 = metadata !{metadata !"Snapdragon LLVM ARM Compiler 3.4"} -!1 = metadata !{metadata !1} +!0 = !{!"Snapdragon LLVM ARM Compiler 3.4"} +!1 = !{!1} diff --git a/test/CodeGen/ARM/section-name.ll b/test/CodeGen/ARM/section-name.ll index a0aad47..a4c6054 100644 --- a/test/CodeGen/ARM/section-name.ll +++ b/test/CodeGen/ARM/section-name.ll @@ -16,7 +16,7 @@ entry: ret void } -; CHECK: .section .text.test3,"axG",%progbits,test3,comdat +; CHECK: .text ; CHECK: .weak test3 ; CHECK: .type test3,%function define linkonce_odr void @test3() { diff --git a/test/CodeGen/ARM/setcc-type-mismatch.ll b/test/CodeGen/ARM/setcc-type-mismatch.ll new file mode 100644 index 0000000..2cfdba1 --- /dev/null +++ b/test/CodeGen/ARM/setcc-type-mismatch.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s + +define void @test_mismatched_setcc(<4 x i22> %l, <4 x i22> %r, <4 x i1>* %addr) { +; CHECK-LABEL: test_mismatched_setcc: +; CHECK: vceq.i32 [[CMP128:q[0-9]+]], {{q[0-9]+}}, {{q[0-9]+}} +; CHECK: vmovn.i32 {{d[0-9]+}}, [[CMP128]] + + %tst = icmp eq <4 x i22> %l, %r + store <4 x i1> %tst, <4 x i1>* %addr + ret void +} diff --git a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll index d8241d0..a7bc22f 100644 --- a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll +++ b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O1 -mtriple thumbv7-apple-ios6 +; RUN: llc < %s -O1 -mtriple thumbv7-apple-ios6 | FileCheck %s ; Just make sure no one tries to make the assumption that the normal edge of an ; invoke is never a critical edge. Previously, this code would assert. @@ -65,3 +65,129 @@ declare i32 @__gxx_personality_sj0(...) declare void @release(i8*) declare void @terminatev() + +; Make sure that the instruction DemoteRegToStack inserts to reload +; %call.i.i.i14.i.i follows the instruction that saves the value to the stack in +; basic block %entry.do.body.i.i.i_crit_edge. +; Previously, DemoteRegToStack would insert a load instruction into the entry +; block to reload %call.i.i.i14.i.i before the phi instruction (%0) in block +; %do.body.i.i.i. + +; CHECK-LABEL: __Z4foo1c: +; CHECK: blx __Znwm +; CHECK: {{.*}}@ %entry.do.body.i.i.i_crit_edge +; CHECK: str r0, [sp, [[OFFSET:#[0-9]+]]] +; CHECK: ldr [[R0:r[0-9]+]], [sp, [[OFFSET]]] +; CHECK: {{.*}}@ %do.body.i.i.i +; CHECK: cmp [[R0]], #0 + +%"class.std::__1::basic_string" = type { %"class.std::__1::__compressed_pair" } +%"class.std::__1::__compressed_pair" = type { %"class.std::__1::__libcpp_compressed_pair_imp" } +%"class.std::__1::__libcpp_compressed_pair_imp" = type { %"struct.std::__1::basic_string, std::__1::allocator >::__rep" } +%"struct.std::__1::basic_string, std::__1::allocator >::__rep" = type { %union.anon } +%union.anon = type { %"struct.std::__1::basic_string, std::__1::allocator >::__long" } +%"struct.std::__1::basic_string, std::__1::allocator >::__long" = type { i32, i32, i8* } + +@.str = private unnamed_addr constant [12 x i8] c"some_string\00", align 1 + +define void @_Z4foo1c(i8 signext %a) { +entry: + %s1 = alloca %"class.std::__1::basic_string", align 4 + call void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(%"class.std::__1::basic_string"* %s1, i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), i32 11) + %call.i.i.i14.i.i = invoke noalias i8* @_Znwm(i32 1024) + to label %do.body.i.i.i unwind label %lpad.body + +do.body.i.i.i: ; preds = %entry, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i + %lsr.iv = phi i32 [ %lsr.iv.next, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i ], [ -1024, %entry ] + %0 = phi i8* [ %incdec.ptr.i.i.i, %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i ], [ %call.i.i.i14.i.i, %entry ] + %new.isnull.i.i.i.i = icmp eq i8* %0, null + br i1 %new.isnull.i.i.i.i, label %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i, label %new.notnull.i.i.i.i + +new.notnull.i.i.i.i: ; preds = %do.body.i.i.i + store i8 %a, i8* %0, align 1 + br label %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i + +_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i: ; preds = %new.notnull.i.i.i.i, %do.body.i.i.i + %1 = phi i8* [ null, %do.body.i.i.i ], [ %0, %new.notnull.i.i.i.i ] + %incdec.ptr.i.i.i = getelementptr inbounds i8* %1, i32 1 + %lsr.iv.next = add i32 %lsr.iv, 1 + %cmp.i16.i.i = icmp eq i32 %lsr.iv.next, 0 + br i1 %cmp.i16.i.i, label %invoke.cont, label %do.body.i.i.i + +invoke.cont: ; preds = %_ZNSt3__116allocator_traitsINS_9allocatorIcEEE9constructIccEEvRS2_PT_RKT0_.exit.i.i.i + invoke void @_Z4foo2Pci(i8* %call.i.i.i14.i.i, i32 1024) + to label %invoke.cont5 unwind label %lpad2 + +invoke.cont5: ; preds = %invoke.cont + %cmp.i.i.i15 = icmp eq i8* %call.i.i.i14.i.i, null + br i1 %cmp.i.i.i15, label %invoke.cont6, label %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19 + +_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19: ; preds = %invoke.cont5 + call void @_ZdlPv(i8* %call.i.i.i14.i.i) + br label %invoke.cont6 + +invoke.cont6: ; preds = %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i19, %invoke.cont5 + %call10 = call %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %s1) + ret void + +lpad.body: ; preds = %entry + %2 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + cleanup + %3 = extractvalue { i8*, i32 } %2, 0 + %4 = extractvalue { i8*, i32 } %2, 1 + br label %ehcleanup + +lpad2: ; preds = %invoke.cont + %5 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + cleanup + %6 = extractvalue { i8*, i32 } %5, 0 + %7 = extractvalue { i8*, i32 } %5, 1 + %cmp.i.i.i21 = icmp eq i8* %call.i.i.i14.i.i, null + br i1 %cmp.i.i.i21, label %ehcleanup, label %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 + +_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26: ; preds = %lpad2 + call void @_ZdlPv(i8* %call.i.i.i14.i.i) + br label %ehcleanup + +ehcleanup: ; preds = %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26, %lpad2, %lpad.body + %exn.slot.0 = phi i8* [ %3, %lpad.body ], [ %6, %lpad2 ], [ %6, %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 ] + %ehselector.slot.0 = phi i32 [ %4, %lpad.body ], [ %7, %lpad2 ], [ %7, %_ZNSt3__113__vector_baseIcNS_9allocatorIcEEE5clearEv.exit.i.i.i26 ] + %call12 = invoke %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* %s1) + to label %eh.resume unwind label %terminate.lpad + +eh.resume: ; preds = %ehcleanup + %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn.slot.0, 0 + %lpad.val13 = insertvalue { i8*, i32 } %lpad.val, i32 %ehselector.slot.0, 1 + resume { i8*, i32 } %lpad.val13 + +terminate.lpad: ; preds = %ehcleanup + %8 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*) + catch i8* null + %9 = extractvalue { i8*, i32 } %8, 0 + call void @__clang_call_terminate(i8* %9) + unreachable +} + +declare void @_Z4foo2Pci(i8*, i32) + +define linkonce_odr hidden void @__clang_call_terminate(i8*) { + %2 = tail call i8* @__cxa_begin_catch(i8* %0) + tail call void @_ZSt9terminatev() + unreachable +} + +declare i8* @__cxa_begin_catch(i8*) +declare void @_ZSt9terminatev() +declare %"class.std::__1::basic_string"* @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev(%"class.std::__1::basic_string"* returned) +declare void @_ZdlPv(i8*) #3 +declare noalias i8* @_Znwm(i32) +declare void @_ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEPKcm(%"class.std::__1::basic_string"*, i8*, i32) +declare void @_Unwind_SjLj_Register({ i8*, i32, [4 x i32], i8*, i8*, [5 x i8*] }*) +declare void @_Unwind_SjLj_Unregister({ i8*, i32, [4 x i32], i8*, i8*, [5 x i8*] }*) +declare i8* @llvm.frameaddress(i32) +declare i8* @llvm.stacksave() +declare void @llvm.stackrestore(i8*) +declare i32 @llvm.eh.sjlj.setjmp(i8*) +declare i8* @llvm.eh.sjlj.lsda() +declare void @llvm.eh.sjlj.callsite(i32) +declare void @llvm.eh.sjlj.functioncontext(i8*) diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index 4fa97ea..425fc12 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -11,7 +11,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly define void @aaa(%quuz* %this, i8* %block) { ; CHECK-LABEL: aaa: -; CHECK: bic {{.*}}, #15 +; CHECK: bfc {{.*}}, #0, #4 ; CHECK: vst1.64 {{.*}}sp:128 ; CHECK: vld1.64 {{.*}}sp:128 entry: diff --git a/test/CodeGen/ARM/stack-alignment.ll b/test/CodeGen/ARM/stack-alignment.ll new file mode 100644 index 0000000..153f92e --- /dev/null +++ b/test/CodeGen/ARM/stack-alignment.ll @@ -0,0 +1,164 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=armv4t | FileCheck %s -check-prefix=CHECK-v4A32 +; RUN: llc -verify-machineinstrs < %s -mtriple=armv7a | FileCheck %s -check-prefix=CHECK-v7A32 +; RUN: llc -verify-machineinstrs < %s -mtriple=thumbv7a | FileCheck %s -check-prefix=CHECK-THUMB2 +; FIXME: There are no tests for Thumb1 since dynamic stack alignment is not supported for +; Thumb1. + +define i32 @f_bic_can_be_used_align() nounwind { +entry: +; CHECK-LABEL: f_bic_can_be_used_align: +; CHECK-v7A32: bfc sp, #0, #8 +; CHECK-v4A32: bic sp, sp, #255 +; CHECK-THUMB2: mov r4, sp +; CHECK-THUMB2-NEXT: bfc r4, #0, #8 +; CHECK-THUMB2-NEXT: mov sp, r4 + %x = alloca i32, align 256 + store volatile i32 0, i32* %x, align 256 + ret i32 0 +} + +define i32 @f_too_large_for_bic_align() nounwind { +entry: +; CHECK-LABEL: f_too_large_for_bic_align: +; CHECK-v7A32: bfc sp, #0, #9 +; CHECK-v4A32: lsr sp, sp, #9 +; CHECK-v4A32: lsl sp, sp, #9 +; CHECK-THUMB2: mov r4, sp +; CHECK-THUMB2-NEXT: bfc r4, #0, #9 +; CHECK-THUMB2-NEXT: mov sp, r4 + %x = alloca i32, align 512 + store volatile i32 0, i32* %x, align 512 + ret i32 0 +} + +define i8* @f_alignedDPRCS2Spills(double* %d) #0 { +entry: +; CHECK-LABEL: f_too_large_for_bic_align: +; CHECK-v7A32: bfc sp, #0, #12 +; CHECK-v4A32: lsr sp, sp, #12 +; CHECK-v4A32: lsl sp, sp, #12 +; CHECK-THUMB2: bfc r4, #0, #12 +; CHECK-THUMB2-NEXT: mov sp, r4 + %a = alloca i8, align 4096 + %0 = load double* %d, align 4 + %arrayidx1 = getelementptr inbounds double* %d, i32 1 + %1 = load double* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds double* %d, i32 2 + %2 = load double* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds double* %d, i32 3 + %3 = load double* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds double* %d, i32 4 + %4 = load double* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds double* %d, i32 5 + %5 = load double* %arrayidx5, align 4 + %arrayidx6 = getelementptr inbounds double* %d, i32 6 + %6 = load double* %arrayidx6, align 4 + %arrayidx7 = getelementptr inbounds double* %d, i32 7 + %7 = load double* %arrayidx7, align 4 + %arrayidx8 = getelementptr inbounds double* %d, i32 8 + %8 = load double* %arrayidx8, align 4 + %arrayidx9 = getelementptr inbounds double* %d, i32 9 + %9 = load double* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds double* %d, i32 10 + %10 = load double* %arrayidx10, align 4 + %arrayidx11 = getelementptr inbounds double* %d, i32 11 + %11 = load double* %arrayidx11, align 4 + %arrayidx12 = getelementptr inbounds double* %d, i32 12 + %12 = load double* %arrayidx12, align 4 + %arrayidx13 = getelementptr inbounds double* %d, i32 13 + %13 = load double* %arrayidx13, align 4 + %arrayidx14 = getelementptr inbounds double* %d, i32 14 + %14 = load double* %arrayidx14, align 4 + %arrayidx15 = getelementptr inbounds double* %d, i32 15 + %15 = load double* %arrayidx15, align 4 + %arrayidx16 = getelementptr inbounds double* %d, i32 16 + %16 = load double* %arrayidx16, align 4 + %arrayidx17 = getelementptr inbounds double* %d, i32 17 + %17 = load double* %arrayidx17, align 4 + %arrayidx18 = getelementptr inbounds double* %d, i32 18 + %18 = load double* %arrayidx18, align 4 + %arrayidx19 = getelementptr inbounds double* %d, i32 19 + %19 = load double* %arrayidx19, align 4 + %arrayidx20 = getelementptr inbounds double* %d, i32 20 + %20 = load double* %arrayidx20, align 4 + %arrayidx21 = getelementptr inbounds double* %d, i32 21 + %21 = load double* %arrayidx21, align 4 + %arrayidx22 = getelementptr inbounds double* %d, i32 22 + %22 = load double* %arrayidx22, align 4 + %arrayidx23 = getelementptr inbounds double* %d, i32 23 + %23 = load double* %arrayidx23, align 4 + %arrayidx24 = getelementptr inbounds double* %d, i32 24 + %24 = load double* %arrayidx24, align 4 + %arrayidx25 = getelementptr inbounds double* %d, i32 25 + %25 = load double* %arrayidx25, align 4 + %arrayidx26 = getelementptr inbounds double* %d, i32 26 + %26 = load double* %arrayidx26, align 4 + %arrayidx27 = getelementptr inbounds double* %d, i32 27 + %27 = load double* %arrayidx27, align 4 + %arrayidx28 = getelementptr inbounds double* %d, i32 28 + %28 = load double* %arrayidx28, align 4 + %arrayidx29 = getelementptr inbounds double* %d, i32 29 + %29 = load double* %arrayidx29, align 4 + %div = fdiv double %29, %28 + %div30 = fdiv double %div, %27 + %div31 = fdiv double %div30, %26 + %div32 = fdiv double %div31, %25 + %div33 = fdiv double %div32, %24 + %div34 = fdiv double %div33, %23 + %div35 = fdiv double %div34, %22 + %div36 = fdiv double %div35, %21 + %div37 = fdiv double %div36, %20 + %div38 = fdiv double %div37, %19 + %div39 = fdiv double %div38, %18 + %div40 = fdiv double %div39, %17 + %div41 = fdiv double %div40, %16 + %div42 = fdiv double %div41, %15 + %div43 = fdiv double %div42, %14 + %div44 = fdiv double %div43, %13 + %div45 = fdiv double %div44, %12 + %div46 = fdiv double %div45, %11 + %div47 = fdiv double %div46, %10 + %div48 = fdiv double %div47, %9 + %div49 = fdiv double %div48, %8 + %div50 = fdiv double %div49, %7 + %div51 = fdiv double %div50, %6 + %div52 = fdiv double %div51, %5 + %div53 = fdiv double %div52, %4 + %div54 = fdiv double %div53, %3 + %div55 = fdiv double %div54, %2 + %div56 = fdiv double %div55, %1 + %div57 = fdiv double %div56, %0 + %div58 = fdiv double %0, %1 + %div59 = fdiv double %div58, %2 + %div60 = fdiv double %div59, %3 + %div61 = fdiv double %div60, %4 + %div62 = fdiv double %div61, %5 + %div63 = fdiv double %div62, %6 + %div64 = fdiv double %div63, %7 + %div65 = fdiv double %div64, %8 + %div66 = fdiv double %div65, %9 + %div67 = fdiv double %div66, %10 + %div68 = fdiv double %div67, %11 + %div69 = fdiv double %div68, %12 + %div70 = fdiv double %div69, %13 + %div71 = fdiv double %div70, %14 + %div72 = fdiv double %div71, %15 + %div73 = fdiv double %div72, %16 + %div74 = fdiv double %div73, %17 + %div75 = fdiv double %div74, %18 + %div76 = fdiv double %div75, %19 + %div77 = fdiv double %div76, %20 + %div78 = fdiv double %div77, %21 + %div79 = fdiv double %div78, %22 + %div80 = fdiv double %div79, %23 + %div81 = fdiv double %div80, %24 + %div82 = fdiv double %div81, %25 + %div83 = fdiv double %div82, %26 + %div84 = fdiv double %div83, %27 + %div85 = fdiv double %div84, %28 + %div86 = fdiv double %div85, %29 + %mul = fmul double %div57, %div86 + %conv = fptosi double %mul to i32 + %add.ptr = getelementptr inbounds i8* %a, i32 %conv + ret i8* %add.ptr +} diff --git a/test/CodeGen/ARM/stack_guard_remat.ll b/test/CodeGen/ARM/stack_guard_remat.ll index b11ea92..7c89b99 100644 --- a/test/CodeGen/ARM/stack_guard_remat.ll +++ b/test/CodeGen/ARM/stack_guard_remat.ll @@ -8,7 +8,7 @@ ;PIC: foo2 ;PIC: ldr [[R0:r[0-9]+]], [[LABEL0:LCPI[0-9_]+]] ;PIC: [[LABEL1:LPC0_1]]: -;PIC: ldr [[R1:r[0-9]+]], [pc, [[R0]]] +;PIC: add [[R1:r[0-9]+]], pc, [[R0]] ;PIC: ldr [[R2:r[0-9]+]], {{\[}}[[R1]]{{\]}} ;PIC: ldr {{r[0-9]+}}, {{\[}}[[R2]]{{\]}} diff --git a/test/CodeGen/ARM/stackpointer.ll b/test/CodeGen/ARM/stackpointer.ll index 420a916..320f0d9 100644 --- a/test/CodeGen/ARM/stackpointer.ll +++ b/test/CodeGen/ARM/stackpointer.ll @@ -22,4 +22,4 @@ declare void @llvm.write_register.i32(metadata, i32) nounwind ; register unsigned long current_stack_pointer asm("sp"); ; CHECK-NOT: .asciz "sp" -!0 = metadata !{metadata !"sp\00"} +!0 = !{!"sp\00"} diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll index 19727da..f7328dc 100644 --- a/test/CodeGen/ARM/sub-cmp-peephole.ll +++ b/test/CodeGen/ARM/sub-cmp-peephole.ll @@ -88,6 +88,19 @@ if.end11: ; preds = %num2long.exit ret i32 23 } +; When considering the producer of cmp's src as the subsuming instruction, +; only consider that when the comparison is to 0. +define i32 @cmp_src_nonzero(i32 %a, i32 %b, i32 %x, i32 %y) { +entry: +; CHECK-LABEL: cmp_src_nonzero: +; CHECK: sub +; CHECK: cmp + %sub = sub i32 %a, %b + %cmp = icmp eq i32 %sub, 17 + %ret = select i1 %cmp, i32 %x, i32 %y + ret i32 %ret +} + define float @float_sel(i32 %a, i32 %b, float %x, float %y) { entry: ; CHECK-LABEL: float_sel: @@ -144,3 +157,50 @@ entry: store i32 %sub, i32* @t ret double %ret } + +declare void @abort() +declare void @exit(i32) + +; If the comparison uses the V bit (signed overflow/underflow), we can't +; omit the comparison. +define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) { +entry: +; CHECK-LABEL: cmp_slt0 +; CHECK: sub +; CHECK: cmp +; CHECK: bge + %load = load i32* @t, align 4 + %sub = sub i32 %load, 17 + %cmp = icmp slt i32 %sub, 0 + br i1 %cmp, label %if.then, label %if.else + +if.then: + call void @abort() + unreachable + +if.else: + call void @exit(i32 0) + unreachable +} + +; Same for the C bit. (Note the ult X, 0 is trivially +; false, so the DAG combiner may or may not optimize it). +define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) { +entry: +; CHECK-LABEL: cmp_ult0 +; CHECK: sub +; CHECK: cmp +; CHECK: bhs + %load = load i32* @t, align 4 + %sub = sub i32 %load, 17 + %cmp = icmp ult i32 %sub, 0 + br i1 %cmp, label %if.then, label %if.else + +if.then: + call void @abort() + unreachable + +if.else: + call void @exit(i32 0) + unreachable +} diff --git a/test/CodeGen/ARM/tail-call-weak.ll b/test/CodeGen/ARM/tail-call-weak.ll new file mode 100644 index 0000000..466c33d --- /dev/null +++ b/test/CodeGen/ARM/tail-call-weak.ll @@ -0,0 +1,19 @@ +; RUN: llc -mtriple thumbv7-windows-coff -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-COFF +; RUN: llc -mtriple thumbv7-elf -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-ELF +; RUN: llc -mtriple thumbv7-macho -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MACHO + +declare i8* @f() +declare extern_weak i8* @g(i8*) + +; weak symbol resolution occurs statically in PE/COFF, ensure that we permit +; tail calls on weak externals when targeting a COFF environment. +define void @test() { + %call = tail call i8* @f() + %call1 = tail call i8* @g(i8* %call) + ret void +} + +; CHECK-COFF: b g +; CHECK-ELF: bl g +; CHECK-MACHO: blx _g + diff --git a/test/CodeGen/ARM/tail-call.ll b/test/CodeGen/ARM/tail-call.ll index c3e7965..ca19b05 100644 --- a/test/CodeGen/ARM/tail-call.ll +++ b/test/CodeGen/ARM/tail-call.ll @@ -1,5 +1,6 @@ -; RUN: llc -mtriple armv7 -O0 -o - < %s | FileCheck %s -check-prefix CHECK-TAIL -; RUN: llc -mtriple armv7 -O0 -disable-tail-calls -o - < %s \ +; RUN: llc -mtriple armv7 -target-abi apcs -O0 -o - < %s \ +; RUN: | FileCheck %s -check-prefix CHECK-TAIL +; RUN: llc -mtriple armv7 -target-abi apcs -O0 -disable-tail-calls -o - < %s \ ; RUN: | FileCheck %s -check-prefix CHECK-NO-TAIL declare i32 @callee(i32 %i) diff --git a/test/CodeGen/ARM/tail-merge-branch-weight.ll b/test/CodeGen/ARM/tail-merge-branch-weight.ll index 9b5d566..95b0a20 100644 --- a/test/CodeGen/ARM/tail-merge-branch-weight.ll +++ b/test/CodeGen/ARM/tail-merge-branch-weight.ll @@ -39,6 +39,6 @@ L3: ; preds = %L0, %L1, %L2 ret i32 %retval.0 } -!0 = metadata !{metadata !"branch_weights", i32 200, i32 800} -!1 = metadata !{metadata !"branch_weights", i32 600, i32 400} -!2 = metadata !{metadata !"branch_weights", i32 300, i32 700} +!0 = !{!"branch_weights", i32 200, i32 800} +!1 = !{!"branch_weights", i32 600, i32 400} +!2 = !{!"branch_weights", i32 300, i32 700} diff --git a/test/CodeGen/ARM/taildup-branch-weight.ll b/test/CodeGen/ARM/taildup-branch-weight.ll index 0a16071..64e0f4b 100644 --- a/test/CodeGen/ARM/taildup-branch-weight.ll +++ b/test/CodeGen/ARM/taildup-branch-weight.ll @@ -27,7 +27,7 @@ B4: ret void } -!0 = metadata !{metadata !"branch_weights", i32 4, i32 124} +!0 = !{!"branch_weights", i32 4, i32 124} ; CHECK: Machine code for function test1: ; CHECK: Successors according to CFG: BB#1(8) BB#2(248) @@ -51,4 +51,4 @@ B3: ret void } -!1 = metadata !{metadata !"branch_weights", i32 248, i32 8} +!1 = !{!"branch_weights", i32 248, i32 8} diff --git a/test/CodeGen/ARM/thumb1-varalloc.ll b/test/CodeGen/ARM/thumb1-varalloc.ll index 8d5888d..82c4ad5 100644 --- a/test/CodeGen/ARM/thumb1-varalloc.ll +++ b/test/CodeGen/ARM/thumb1-varalloc.ll @@ -43,26 +43,6 @@ bb3: declare noalias i8* @strdup(i8* nocapture) nounwind declare i32 @_called_func(i8*, i32*) nounwind -; Variable ending up at unaligned offset from sp (i.e. not a multiple of 4) -define void @test_local_var_addr() { -; CHECK-LABEL: test_local_var_addr: - - %addr1 = alloca i8 - %addr2 = alloca i8 - -; CHECK: mov r0, sp -; CHECK: adds r0, #{{[0-9]+}} -; CHECK: blx - call void @take_ptr(i8* %addr1) - -; CHECK: mov r0, sp -; CHECK: adds r0, #{{[0-9]+}} -; CHECK: blx - call void @take_ptr(i8* %addr2) - - ret void -} - ; Simple variable ending up *at* sp. define void @test_simple_var() { ; CHECK-LABEL: test_simple_var: @@ -126,14 +106,16 @@ define void @test_local_var_offset_1020() { ret void } -; Max range addressable with tADDrSPi + tADDi8 -define void @test_local_var_offset_1275() { -; CHECK-LABEL: test_local_var_offset_1275 +; Max range addressable with tADDrSPi + tADDi8 is 1275, however the automatic +; 4-byte aligning of objects on the stack combined with 8-byte stack alignment +; means that 1268 is the max offset we can use. +define void @test_local_var_offset_1268() { +; CHECK-LABEL: test_local_var_offset_1268 %addr1 = alloca i8, i32 1 - %addr2 = alloca i8, i32 1275 + %addr2 = alloca i8, i32 1268 ; CHECK: add r0, sp, #1020 -; CHECK: adds r0, #255 +; CHECK: adds r0, #248 ; CHECK-NEXT: blx call void @take_ptr(i8* %addr1) diff --git a/test/CodeGen/ARM/thumb1_return_sequence.ll b/test/CodeGen/ARM/thumb1_return_sequence.ll index 318e6e4..c831260 100644 --- a/test/CodeGen/ARM/thumb1_return_sequence.ll +++ b/test/CodeGen/ARM/thumb1_return_sequence.ll @@ -3,7 +3,7 @@ ; CHECK-V4T-LABEL: clobberframe ; CHECK-V5T-LABEL: clobberframe -define <4 x i32> @clobberframe() #0 { +define <4 x i32> @clobberframe(<6 x i32>* %p) #0 { entry: ; Prologue ; -------- @@ -11,9 +11,10 @@ entry: ; CHECK-V4T: sub sp, ; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr} - %b = alloca <4 x i32>, align 16 + %b = alloca <6 x i32>, align 16 %a = alloca <4 x i32>, align 16 - store <4 x i32> , <4 x i32>* %b, align 16 + %stuff = load <6 x i32>* %p, align 16 + store <6 x i32> %stuff, <6 x i32>* %b, align 16 store <4 x i32> , <4 x i32>* %a, align 16 %0 = load <4 x i32>* %a, align 16 ret <4 x i32> %0 @@ -70,40 +71,25 @@ entry: ; CHECK-V4T-LABEL: simpleframe ; CHECK-V5T-LABEL: simpleframe -define i32 @simpleframe() #0 { +define i32 @simpleframe(<6 x i32>* %p) #0 { entry: ; Prologue ; -------- ; CHECK-V4T: push {[[SAVED:(r[4567](, )?)+]], lr} ; CHECK-V5T: push {[[SAVED:(r[4567](, )?)+]], lr} - %a = alloca i32, align 4 - %b = alloca i32, align 4 - %c = alloca i32, align 4 - %d = alloca i32, align 4 - store i32 1, i32* %a, align 4 - store i32 2, i32* %b, align 4 - store i32 3, i32* %c, align 4 - store i32 4, i32* %d, align 4 - %0 = load i32* %a, align 4 - %inc = add nsw i32 %0, 1 - store i32 %inc, i32* %a, align 4 - %1 = load i32* %b, align 4 - %inc1 = add nsw i32 %1, 1 - store i32 %inc1, i32* %b, align 4 - %2 = load i32* %c, align 4 - %inc2 = add nsw i32 %2, 1 - store i32 %inc2, i32* %c, align 4 - %3 = load i32* %d, align 4 - %inc3 = add nsw i32 %3, 1 - store i32 %inc3, i32* %d, align 4 - %4 = load i32* %a, align 4 - %5 = load i32* %b, align 4 - %add = add nsw i32 %4, %5 - %6 = load i32* %c, align 4 - %add4 = add nsw i32 %add, %6 - %7 = load i32* %d, align 4 - %add5 = add nsw i32 %add4, %7 + %0 = load <6 x i32>* %p, align 16 + %1 = extractelement <6 x i32> %0, i32 0 + %2 = extractelement <6 x i32> %0, i32 1 + %3 = extractelement <6 x i32> %0, i32 2 + %4 = extractelement <6 x i32> %0, i32 3 + %5 = extractelement <6 x i32> %0, i32 4 + %6 = extractelement <6 x i32> %0, i32 5 + %add1 = add nsw i32 %1, %2 + %add2 = add nsw i32 %add1, %3 + %add3 = add nsw i32 %add2, %4 + %add4 = add nsw i32 %add3, %5 + %add5 = add nsw i32 %add4, %6 ret i32 %add5 ; Epilogue diff --git a/test/CodeGen/ARM/thumb_indirect_calls.ll b/test/CodeGen/ARM/thumb_indirect_calls.ll new file mode 100644 index 0000000..16a55a8 --- /dev/null +++ b/test/CodeGen/ARM/thumb_indirect_calls.ll @@ -0,0 +1,40 @@ +; RUN: llc -mtriple=thumbv4t-eabi %s -o - | FileCheck ---check-prefix=CHECK -check-prefix=CHECK-V4T %s +; RUN: llc -mtriple=thumbv5t-eabi %s -o - | FileCheck ---check-prefix=CHECK -check-prefix=CHECK-V5T %s + +@f = common global void (i32)* null, align 4 + +; CHECK-LABEL foo: +define void @foo(i32 %x) { +entry: + %0 = load void (i32)** @f, align 4 + tail call void %0(i32 %x) + ret void + +; CHECK: ldr [[TMP:r[0-3]]], [[F:\.[A-Z0-9_]+]] +; CHECK: ldr [[CALLEE:r[0-3]]], {{\[}}[[TMP]]{{\]}} + +; CHECK-V4T-NOT: blx +; CHECK-V4T: bl [[INDIRECT_PAD:\.Ltmp[0-9]+]] +; CHECK-V4T: [[F]]: +; CHECK-V4T: [[INDIRECT_PAD]]: +; CHECK-V4T-NEXT: bx [[CALLEE]] +; CHECK-V5T: blx [[CALLEE]] +} + +; CHECK-LABEL bar: +define void @bar(void (i32)* nocapture %g, i32 %x, void (i32)* nocapture %h) { +entry: + tail call void %g(i32 %x) + tail call void %h(i32 %x) + ret void + +; CHECK-V4T: bl [[INDIRECT_PAD1:\.Ltmp[0-9]+]] +; CHECK-V4T: bl [[INDIRECT_PAD2:\.Ltmp[0-9]+]] +; CHECK-V4T: [[INDIRECT_PAD1]]: +; CHECK-V4T-NEXT: bx +; CHECK-V4T: [[INDIRECT_PAD2]]: +; CHECK-V4T-NEXT: bx +; CHECK-V5T: blx +; CHECK-V5T: blx +} + diff --git a/test/CodeGen/ARM/tls1.ll b/test/CodeGen/ARM/tls1.ll index a1ca0b7..b03f76b 100644 --- a/test/CodeGen/ARM/tls1.ll +++ b/test/CodeGen/ARM/tls1.ll @@ -1,11 +1,13 @@ -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \ -; RUN: grep "i(TPOFF)" -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | \ -; RUN: grep "__aeabi_read_tp" -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \ -; RUN: -relocation-model=pic | grep "__tls_get_addr" +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | FileCheck %s +; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi -relocation-model=pic | \ +; RUN: FileCheck %s --check-prefix=PIC +; CHECK: i(TPOFF) +; CHECK: __aeabi_read_tp + +; PIC: __tls_get_addr + @i = thread_local global i32 15 ; [#uses=2] define i32 @f() { diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll index 89f355c..6f8b3dd 100644 --- a/test/CodeGen/ARM/vdup.ll +++ b/test/CodeGen/ARM/vdup.ll @@ -347,17 +347,17 @@ define <2 x float> @check_spr_splat2(<2 x float> %p, i16 %q) { define <4 x float> @check_spr_splat4(<4 x float> %p, i16 %q) { ;CHECK-LABEL: check_spr_splat4: -;CHECK: vdup.32 q +;CHECK: vld1.16 %conv = sitofp i16 %q to float %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer %sub = fsub <4 x float> %splat.splat, %p ret <4 x float> %sub } - +; Same codegen as above test; scalar is splatted using vld1, so shuffle index is irrelevant. define <4 x float> @check_spr_splat4_lane1(<4 x float> %p, i16 %q) { ;CHECK-LABEL: check_spr_splat4_lane1: -;CHECK: vdup.32 q{{.*}}, d{{.*}}[1] +;CHECK: vld1.16 %conv = sitofp i16 %q to float %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll index 759da22..566e955 100644 --- a/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -27,6 +27,14 @@ entry: ret void } +; PR22678 +; Check CONCAT_VECTORS DAG combiner pass doesn't introduce illegal types. +define void @test_pr22678() { + %1 = fptoui <16 x float> undef to <16 x i8> + store <16 x i8> %1, <16 x i8>* undef + ret void +} + ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is ; converted back to be used as a vector type. ; CHECK-LABEL: test_vmovrrd_combine: diff --git a/test/CodeGen/ARM/vector-load.ll b/test/CodeGen/ARM/vector-load.ll new file mode 100644 index 0000000..c177a55 --- /dev/null +++ b/test/CodeGen/ARM/vector-load.ll @@ -0,0 +1,253 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-ios8.0.0" + +define <8 x i8> @load_v8i8(<8 x i8>** %ptr) { +;CHECK-LABEL: load_v8i8: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <8 x i8>** %ptr + %lA = load <8 x i8>* %A, align 1 + ret <8 x i8> %lA +} + +define <8 x i8> @load_v8i8_update(<8 x i8>** %ptr) { +;CHECK-LABEL: load_v8i8_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <8 x i8>** %ptr + %lA = load <8 x i8>* %A, align 1 + %inc = getelementptr <8 x i8>* %A, i38 1 + store <8 x i8>* %inc, <8 x i8>** %ptr + ret <8 x i8> %lA +} + +define <4 x i16> @load_v4i16(<4 x i16>** %ptr) { +;CHECK-LABEL: load_v4i16: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x i16>** %ptr + %lA = load <4 x i16>* %A, align 1 + ret <4 x i16> %lA +} + +define <4 x i16> @load_v4i16_update(<4 x i16>** %ptr) { +;CHECK-LABEL: load_v4i16_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x i16>** %ptr + %lA = load <4 x i16>* %A, align 1 + %inc = getelementptr <4 x i16>* %A, i34 1 + store <4 x i16>* %inc, <4 x i16>** %ptr + ret <4 x i16> %lA +} + +define <2 x i32> @load_v2i32(<2 x i32>** %ptr) { +;CHECK-LABEL: load_v2i32: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <2 x i32>** %ptr + %lA = load <2 x i32>* %A, align 1 + ret <2 x i32> %lA +} + +define <2 x i32> @load_v2i32_update(<2 x i32>** %ptr) { +;CHECK-LABEL: load_v2i32_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i32>** %ptr + %lA = load <2 x i32>* %A, align 1 + %inc = getelementptr <2 x i32>* %A, i32 1 + store <2 x i32>* %inc, <2 x i32>** %ptr + ret <2 x i32> %lA +} + +define <2 x float> @load_v2f32(<2 x float>** %ptr) { +;CHECK-LABEL: load_v2f32: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <2 x float>** %ptr + %lA = load <2 x float>* %A, align 1 + ret <2 x float> %lA +} + +define <2 x float> @load_v2f32_update(<2 x float>** %ptr) { +;CHECK-LABEL: load_v2f32_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x float>** %ptr + %lA = load <2 x float>* %A, align 1 + %inc = getelementptr <2 x float>* %A, i32 1 + store <2 x float>* %inc, <2 x float>** %ptr + ret <2 x float> %lA +} + +define <1 x i64> @load_v1i64(<1 x i64>** %ptr) { +;CHECK-LABEL: load_v1i64: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <1 x i64>** %ptr + %lA = load <1 x i64>* %A, align 1 + ret <1 x i64> %lA +} + +define <1 x i64> @load_v1i64_update(<1 x i64>** %ptr) { +;CHECK-LABEL: load_v1i64_update: +;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <1 x i64>** %ptr + %lA = load <1 x i64>* %A, align 1 + %inc = getelementptr <1 x i64>* %A, i31 1 + store <1 x i64>* %inc, <1 x i64>** %ptr + ret <1 x i64> %lA +} + +define <16 x i8> @load_v16i8(<16 x i8>** %ptr) { +;CHECK-LABEL: load_v16i8: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <16 x i8>** %ptr + %lA = load <16 x i8>* %A, align 1 + ret <16 x i8> %lA +} + +define <16 x i8> @load_v16i8_update(<16 x i8>** %ptr) { +;CHECK-LABEL: load_v16i8_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <16 x i8>** %ptr + %lA = load <16 x i8>* %A, align 1 + %inc = getelementptr <16 x i8>* %A, i316 1 + store <16 x i8>* %inc, <16 x i8>** %ptr + ret <16 x i8> %lA +} + +define <8 x i16> @load_v8i16(<8 x i16>** %ptr) { +;CHECK-LABEL: load_v8i16: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <8 x i16>** %ptr + %lA = load <8 x i16>* %A, align 1 + ret <8 x i16> %lA +} + +define <8 x i16> @load_v8i16_update(<8 x i16>** %ptr) { +;CHECK-LABEL: load_v8i16_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <8 x i16>** %ptr + %lA = load <8 x i16>* %A, align 1 + %inc = getelementptr <8 x i16>* %A, i38 1 + store <8 x i16>* %inc, <8 x i16>** %ptr + ret <8 x i16> %lA +} + +define <4 x i32> @load_v4i32(<4 x i32>** %ptr) { +;CHECK-LABEL: load_v4i32: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x i32>** %ptr + %lA = load <4 x i32>* %A, align 1 + ret <4 x i32> %lA +} + +define <4 x i32> @load_v4i32_update(<4 x i32>** %ptr) { +;CHECK-LABEL: load_v4i32_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x i32>** %ptr + %lA = load <4 x i32>* %A, align 1 + %inc = getelementptr <4 x i32>* %A, i34 1 + store <4 x i32>* %inc, <4 x i32>** %ptr + ret <4 x i32> %lA +} + +define <4 x float> @load_v4f32(<4 x float>** %ptr) { +;CHECK-LABEL: load_v4f32: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x float>** %ptr + %lA = load <4 x float>* %A, align 1 + ret <4 x float> %lA +} + +define <4 x float> @load_v4f32_update(<4 x float>** %ptr) { +;CHECK-LABEL: load_v4f32_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x float>** %ptr + %lA = load <4 x float>* %A, align 1 + %inc = getelementptr <4 x float>* %A, i34 1 + store <4 x float>* %inc, <4 x float>** %ptr + ret <4 x float> %lA +} + +define <2 x i64> @load_v2i64(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <2 x i64>** %ptr + %lA = load <2 x i64>* %A, align 1 + ret <2 x i64> %lA +} + +define <2 x i64> @load_v2i64_update(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update: +;CHECK: vld1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>** %ptr + %lA = load <2 x i64>* %A, align 1 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +; Make sure we change the type to match alignment if necessary. +define <2 x i64> @load_v2i64_update_aligned2(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update_aligned2: +;CHECK: vld1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>** %ptr + %lA = load <2 x i64>* %A, align 2 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +define <2 x i64> @load_v2i64_update_aligned4(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update_aligned4: +;CHECK: vld1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>** %ptr + %lA = load <2 x i64>* %A, align 4 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +define <2 x i64> @load_v2i64_update_aligned8(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update_aligned8: +;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>** %ptr + %lA = load <2 x i64>* %A, align 8 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +define <2 x i64> @load_v2i64_update_aligned16(<2 x i64>** %ptr) { +;CHECK-LABEL: load_v2i64_update_aligned16: +;CHECK: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]! + %A = load <2 x i64>** %ptr + %lA = load <2 x i64>* %A, align 16 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret <2 x i64> %lA +} + +; Make sure we don't break smaller-than-dreg extloads. +define <4 x i32> @zextload_v8i8tov8i32(<4 x i8>** %ptr) { +;CHECK-LABEL: zextload_v8i8tov8i32: +;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [{{r[0-9]+}}:32] +;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}} +;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}} + %A = load <4 x i8>** %ptr + %lA = load <4 x i8>* %A, align 4 + %zlA = zext <4 x i8> %lA to <4 x i32> + ret <4 x i32> %zlA +} + +define <4 x i32> @zextload_v8i8tov8i32_fake_update(<4 x i8>** %ptr) { +;CHECK-LABEL: zextload_v8i8tov8i32_fake_update: +;CHECK: ldr.w r[[PTRREG:[0-9]+]], [r0] +;CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r[[PTRREG]]:32] +;CHECK: add.w r[[INCREG:[0-9]+]], r[[PTRREG]], #16 +;CHECK: str.w r[[INCREG]], [r0] +;CHECK: vmovl.u8 {{q[0-9]+}}, {{d[0-9]+}} +;CHECK: vmovl.u16 {{q[0-9]+}}, {{d[0-9]+}} + %A = load <4 x i8>** %ptr + %lA = load <4 x i8>* %A, align 4 + %inc = getelementptr <4 x i8>* %A, i38 4 + store <4 x i8>* %inc, <4 x i8>** %ptr + %zlA = zext <4 x i8> %lA to <4 x i32> + ret <4 x i32> %zlA +} diff --git a/test/CodeGen/ARM/vector-store.ll b/test/CodeGen/ARM/vector-store.ll new file mode 100644 index 0000000..55cb8f2 --- /dev/null +++ b/test/CodeGen/ARM/vector-store.ll @@ -0,0 +1,258 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7s-apple-ios8.0.0" + +define void @store_v8i8(<8 x i8>** %ptr, <8 x i8> %val) { +;CHECK-LABEL: store_v8i8: +;CHECK: str r1, [r0] + %A = load <8 x i8>** %ptr + store <8 x i8> %val, <8 x i8>* %A, align 1 + ret void +} + +define void @store_v8i8_update(<8 x i8>** %ptr, <8 x i8> %val) { +;CHECK-LABEL: store_v8i8_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <8 x i8>** %ptr + store <8 x i8> %val, <8 x i8>* %A, align 1 + %inc = getelementptr <8 x i8>* %A, i38 1 + store <8 x i8>* %inc, <8 x i8>** %ptr + ret void +} + +define void @store_v4i16(<4 x i16>** %ptr, <4 x i16> %val) { +;CHECK-LABEL: store_v4i16: +;CHECK: str r1, [r0] + %A = load <4 x i16>** %ptr + store <4 x i16> %val, <4 x i16>* %A, align 1 + ret void +} + +define void @store_v4i16_update(<4 x i16>** %ptr, <4 x i16> %val) { +;CHECK-LABEL: store_v4i16_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x i16>** %ptr + store <4 x i16> %val, <4 x i16>* %A, align 1 + %inc = getelementptr <4 x i16>* %A, i34 1 + store <4 x i16>* %inc, <4 x i16>** %ptr + ret void +} + +define void @store_v2i32(<2 x i32>** %ptr, <2 x i32> %val) { +;CHECK-LABEL: store_v2i32: +;CHECK: str r1, [r0] + %A = load <2 x i32>** %ptr + store <2 x i32> %val, <2 x i32>* %A, align 1 + ret void +} + +define void @store_v2i32_update(<2 x i32>** %ptr, <2 x i32> %val) { +;CHECK-LABEL: store_v2i32_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i32>** %ptr + store <2 x i32> %val, <2 x i32>* %A, align 1 + %inc = getelementptr <2 x i32>* %A, i32 1 + store <2 x i32>* %inc, <2 x i32>** %ptr + ret void +} + +define void @store_v2f32(<2 x float>** %ptr, <2 x float> %val) { +;CHECK-LABEL: store_v2f32: +;CHECK: str r1, [r0] + %A = load <2 x float>** %ptr + store <2 x float> %val, <2 x float>* %A, align 1 + ret void +} + +define void @store_v2f32_update(<2 x float>** %ptr, <2 x float> %val) { +;CHECK-LABEL: store_v2f32_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x float>** %ptr + store <2 x float> %val, <2 x float>* %A, align 1 + %inc = getelementptr <2 x float>* %A, i32 1 + store <2 x float>* %inc, <2 x float>** %ptr + ret void +} + +define void @store_v1i64(<1 x i64>** %ptr, <1 x i64> %val) { +;CHECK-LABEL: store_v1i64: +;CHECK: str r1, [r0] + %A = load <1 x i64>** %ptr + store <1 x i64> %val, <1 x i64>* %A, align 1 + ret void +} + +define void @store_v1i64_update(<1 x i64>** %ptr, <1 x i64> %val) { +;CHECK-LABEL: store_v1i64_update: +;CHECK: vst1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <1 x i64>** %ptr + store <1 x i64> %val, <1 x i64>* %A, align 1 + %inc = getelementptr <1 x i64>* %A, i31 1 + store <1 x i64>* %inc, <1 x i64>** %ptr + ret void +} + +define void @store_v16i8(<16 x i8>** %ptr, <16 x i8> %val) { +;CHECK-LABEL: store_v16i8: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <16 x i8>** %ptr + store <16 x i8> %val, <16 x i8>* %A, align 1 + ret void +} + +define void @store_v16i8_update(<16 x i8>** %ptr, <16 x i8> %val) { +;CHECK-LABEL: store_v16i8_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <16 x i8>** %ptr + store <16 x i8> %val, <16 x i8>* %A, align 1 + %inc = getelementptr <16 x i8>* %A, i316 1 + store <16 x i8>* %inc, <16 x i8>** %ptr + ret void +} + +define void @store_v8i16(<8 x i16>** %ptr, <8 x i16> %val) { +;CHECK-LABEL: store_v8i16: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <8 x i16>** %ptr + store <8 x i16> %val, <8 x i16>* %A, align 1 + ret void +} + +define void @store_v8i16_update(<8 x i16>** %ptr, <8 x i16> %val) { +;CHECK-LABEL: store_v8i16_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <8 x i16>** %ptr + store <8 x i16> %val, <8 x i16>* %A, align 1 + %inc = getelementptr <8 x i16>* %A, i38 1 + store <8 x i16>* %inc, <8 x i16>** %ptr + ret void +} + +define void @store_v4i32(<4 x i32>** %ptr, <4 x i32> %val) { +;CHECK-LABEL: store_v4i32: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x i32>** %ptr + store <4 x i32> %val, <4 x i32>* %A, align 1 + ret void +} + +define void @store_v4i32_update(<4 x i32>** %ptr, <4 x i32> %val) { +;CHECK-LABEL: store_v4i32_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x i32>** %ptr + store <4 x i32> %val, <4 x i32>* %A, align 1 + %inc = getelementptr <4 x i32>* %A, i34 1 + store <4 x i32>* %inc, <4 x i32>** %ptr + ret void +} + +define void @store_v4f32(<4 x float>** %ptr, <4 x float> %val) { +;CHECK-LABEL: store_v4f32: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <4 x float>** %ptr + store <4 x float> %val, <4 x float>* %A, align 1 + ret void +} + +define void @store_v4f32_update(<4 x float>** %ptr, <4 x float> %val) { +;CHECK-LABEL: store_v4f32_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <4 x float>** %ptr + store <4 x float> %val, <4 x float>* %A, align 1 + %inc = getelementptr <4 x float>* %A, i34 1 + store <4 x float>* %inc, <4 x float>** %ptr + ret void +} + +define void @store_v2i64(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}] + %A = load <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 1 + ret void +} + +define void @store_v2i64_update(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update: +;CHECK: vst1.8 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 1 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @store_v2i64_update_aligned2(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update_aligned2: +;CHECK: vst1.16 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 2 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @store_v2i64_update_aligned4(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update_aligned4: +;CHECK: vst1.32 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 4 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @store_v2i64_update_aligned8(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update_aligned8: +;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}]! + %A = load <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 8 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @store_v2i64_update_aligned16(<2 x i64>** %ptr, <2 x i64> %val) { +;CHECK-LABEL: store_v2i64_update_aligned16: +;CHECK: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [{{r[0-9]+}}:128]! + %A = load <2 x i64>** %ptr + store <2 x i64> %val, <2 x i64>* %A, align 16 + %inc = getelementptr <2 x i64>* %A, i32 1 + store <2 x i64>* %inc, <2 x i64>** %ptr + ret void +} + +define void @truncstore_v4i32tov4i8(<4 x i8>** %ptr, <4 x i32> %val) { +;CHECK-LABEL: truncstore_v4i32tov4i8: +;CHECK: ldr.w r9, [sp] +;CHECK: vmov {{d[0-9]+}}, r3, r9 +;CHECK: vmov {{d[0-9]+}}, r1, r2 +;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}} +;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}} +;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] +;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32] + %A = load <4 x i8>** %ptr + %trunc = trunc <4 x i32> %val to <4 x i8> + store <4 x i8> %trunc, <4 x i8>* %A, align 4 + ret void +} + +define void @truncstore_v4i32tov4i8_fake_update(<4 x i8>** %ptr, <4 x i32> %val) { +;CHECK-LABEL: truncstore_v4i32tov4i8_fake_update: +;CHECK: ldr.w r9, [sp] +;CHECK: vmov {{d[0-9]+}}, r3, r9 +;CHECK: vmov {{d[0-9]+}}, r1, r2 +;CHECK: movs [[IMM16:r[0-9]+]], #16 +;CHECK: vmovn.i32 [[VECLO:d[0-9]+]], {{q[0-9]+}} +;CHECK: vuzp.8 [[VECLO]], {{d[0-9]+}} +;CHECK: ldr r[[PTRREG:[0-9]+]], [r0] +;CHECK: vst1.32 {[[VECLO]][0]}, [r[[PTRREG]]:32], [[IMM16]] +;CHECK: str r[[PTRREG]], [r0] + %A = load <4 x i8>** %ptr + %trunc = trunc <4 x i32> %val to <4 x i8> + store <4 x i8> %trunc, <4 x i8>* %A, align 4 + %inc = getelementptr <4 x i8>* %A, i38 4 + store <4 x i8>* %inc, <4 x i8>** %ptr + ret void +} diff --git a/test/CodeGen/ARM/vfp-regs-dwarf.ll b/test/CodeGen/ARM/vfp-regs-dwarf.ll index f83adf9..b67f770 100644 --- a/test/CodeGen/ARM/vfp-regs-dwarf.ll +++ b/test/CodeGen/ARM/vfp-regs-dwarf.ll @@ -31,14 +31,14 @@ define void @stack_offsets() { !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!8, !9} -!0 = metadata !{metadata !"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", metadata !1, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2} ; [ DW_TAG_compile_unit ] [/Users/tim/llvm/build/tmp.c] [DW_LANG_C99] -!1 = metadata !{metadata !"tmp.c", metadata !"/Users/tim/llvm/build"} -!2 = metadata !{} -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !"0x2e\00bar\00bar\00\001\000\001\000\006\000\000\001", metadata !1, metadata !5, metadata !6, null, void ()* @stack_offsets, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 1] [def] [bar] -!5 = metadata !{metadata !"0x29", metadata !1} ; [ DW_TAG_file_type ] [/Users/tim/llvm/build/tmp.c] -!6 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!7 = metadata !{null} -!8 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} -!9 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x11\0012\00clang version 3.5.0 \000\00\000\00\001", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/Users/tim/llvm/build/tmp.c] [DW_LANG_C99] +!1 = !{!"tmp.c", !"/Users/tim/llvm/build"} +!2 = !{} +!3 = !{!4} +!4 = !{!"0x2e\00bar\00bar\00\001\000\001\000\006\000\000\001", !1, !5, !6, null, void ()* @stack_offsets, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [bar] +!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/Users/tim/llvm/build/tmp.c] +!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = !{null} +!8 = !{i32 2, !"Dwarf Version", i32 4} +!9 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index caeeada..db640f5 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -119,6 +119,14 @@ define <2 x i64> @vld1Qi64(i64* %A) nounwind { ret <2 x i64> %tmp1 } +define <2 x double> @vld1Qf64(double* %A) nounwind { +;CHECK-LABEL: vld1Qf64: +;CHECK: vld1.64 + %tmp0 = bitcast double* %A to i8* + %tmp1 = call <2 x double> @llvm.arm.neon.vld1.v2f64(i8* %tmp0, i32 1) + ret <2 x double> %tmp1 +} + declare <8 x i8> @llvm.arm.neon.vld1.v8i8(i8*, i32) nounwind readonly declare <4 x i16> @llvm.arm.neon.vld1.v4i16(i8*, i32) nounwind readonly declare <2 x i32> @llvm.arm.neon.vld1.v2i32(i8*, i32) nounwind readonly @@ -130,6 +138,7 @@ declare <8 x i16> @llvm.arm.neon.vld1.v8i16(i8*, i32) nounwind readonly declare <4 x i32> @llvm.arm.neon.vld1.v4i32(i8*, i32) nounwind readonly declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly +declare <2 x double> @llvm.arm.neon.vld1.v2f64(i8*, i32) nounwind readonly ; Radar 8355607 ; Do not crash if the vld1 result is not used. diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll index 14f3ff0..a6bcf7d 100644 --- a/test/CodeGen/ARM/vst1.ll +++ b/test/CodeGen/ARM/vst1.ll @@ -117,6 +117,15 @@ define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind { ret void } +define void @vst1Qf64(double* %A, <2 x double>* %B) nounwind { +;CHECK-LABEL: vst1Qf64: +;CHECK: vst1.64 + %tmp0 = bitcast double* %A to i8* + %tmp1 = load <2 x double>* %B + call void @llvm.arm.neon.vst1.v2f64(i8* %tmp0, <2 x double> %tmp1, i32 1) + ret void +} + declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind declare void @llvm.arm.neon.vst1.v4i16(i8*, <4 x i16>, i32) nounwind declare void @llvm.arm.neon.vst1.v2i32(i8*, <2 x i32>, i32) nounwind @@ -128,3 +137,4 @@ declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind declare void @llvm.arm.neon.vst1.v4i32(i8*, <4 x i32>, i32) nounwind declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind declare void @llvm.arm.neon.vst1.v2i64(i8*, <2 x i64>, i32) nounwind +declare void @llvm.arm.neon.vst1.v2f64(i8*, <2 x double>, i32) nounwind diff --git a/test/CodeGen/BPF/alu8.ll b/test/CodeGen/BPF/alu8.ll new file mode 100644 index 0000000..0233225 --- /dev/null +++ b/test/CodeGen/BPF/alu8.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=bpf -show-mc-encoding < %s | FileCheck %s +; test little endian only for now + +define i8 @mov(i8 %a, i8 %b) nounwind { +; CHECK-LABEL: mov: +; CHECK: mov r0, r2 # encoding: [0xbf,0x20,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: ret # encoding: [0x95,0x00,0x00,0x00,0x00,0x00,0x00,0x00] + ret i8 %b +} + +define i8 @add(i8 %a, i8 %b) nounwind { +; CHECK-LABEL: add: +; CHECK: add r1, r2 # encoding: [0x0f,0x21,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: mov r0, r1 # encoding: [0xbf,0x10,0x00,0x00,0x00,0x00,0x00,0x00] + %1 = add i8 %a, %b + ret i8 %1 +} + +define i8 @and(i8 %a, i8 %b) nounwind { +; CHECK-LABEL: and: +; CHECK: and r1, r2 # encoding: [0x5f,0x21,0x00,0x00,0x00,0x00,0x00,0x00] + %1 = and i8 %a, %b + ret i8 %1 +} + +define i8 @bis(i8 %a, i8 %b) nounwind { +; CHECK-LABEL: bis: +; CHECK: or r1, r2 # encoding: [0x4f,0x21,0x00,0x00,0x00,0x00,0x00,0x00] + %1 = or i8 %a, %b + ret i8 %1 +} + +define i8 @xorand(i8 %a, i8 %b) nounwind { +; CHECK-LABEL: xorand: +; CHECK: xori r2, -1 # encoding: [0xa7,0x02,0x00,0x00,0xff,0xff,0xff,0xff] + %1 = xor i8 %b, -1 + %2 = and i8 %a, %1 + ret i8 %2 +} + +define i8 @xor(i8 %a, i8 %b) nounwind { +; CHECK-LABEL: xor: +; CHECK: xor r1, r2 # encoding: [0xaf,0x21,0x00,0x00,0x00,0x00,0x00,0x00] + %1 = xor i8 %a, %b + ret i8 %1 +} diff --git a/test/CodeGen/BPF/atomics.ll b/test/CodeGen/BPF/atomics.ll new file mode 100644 index 0000000..2f9730d --- /dev/null +++ b/test/CodeGen/BPF/atomics.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=bpf -verify-machineinstrs -show-mc-encoding | FileCheck %s +; test little endian only for now + +; CHECK-LABEL: test_load_add_32 +; CHECK: xadd32 +; CHECK: encoding: [0xc3 +define void @test_load_add_32(i32* %p, i32 zeroext %v) { +entry: + atomicrmw add i32* %p, i32 %v seq_cst + ret void +} + +; CHECK-LABEL: test_load_add_64 +; CHECK: xadd64 +; CHECK: encoding: [0xdb +define void @test_load_add_64(i64* %p, i64 zeroext %v) { +entry: + atomicrmw add i64* %p, i64 %v seq_cst + ret void +} diff --git a/test/CodeGen/BPF/basictest.ll b/test/CodeGen/BPF/basictest.ll new file mode 100644 index 0000000..0cbfff8 --- /dev/null +++ b/test/CodeGen/BPF/basictest.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=bpf | FileCheck %s + +define i32 @test0(i32 %X) { + %tmp.1 = add i32 %X, 1 + ret i32 %tmp.1 +; CHECK-LABEL: test0: +; CHECK: addi r1, 1 +} + +; CHECK-LABEL: store_imm: +; CHECK: stw 0(r1), r0 +; CHECK: stw 4(r2), r0 +define i32 @store_imm(i32* %a, i32* %b) { +entry: + store i32 0, i32* %a, align 4 + %0 = getelementptr inbounds i32* %b, i32 1 + store i32 0, i32* %0, align 4 + ret i32 0 +} + +@G = external global i8 +define zeroext i8 @loadG() { + %tmp = load i8* @G + ret i8 %tmp +; CHECK-LABEL: loadG: +; CHECK: ld_64 r1 +; CHECK: ldb r0, 0(r1) +} diff --git a/test/CodeGen/BPF/byval.ll b/test/CodeGen/BPF/byval.ll new file mode 100644 index 0000000..065604b --- /dev/null +++ b/test/CodeGen/BPF/byval.ll @@ -0,0 +1,27 @@ +; RUN: not llc -march=bpf < %s 2> %t1 +; RUN: FileCheck %s < %t1 +; CHECK: by value not supported + +%struct.S = type { [10 x i32] } + +; Function Attrs: nounwind uwtable +define void @bar(i32 %a) #0 { +entry: + %.compoundliteral = alloca %struct.S, align 8 + %arrayinit.begin = getelementptr inbounds %struct.S* %.compoundliteral, i64 0, i32 0, i64 0 + store i32 1, i32* %arrayinit.begin, align 8 + %arrayinit.element = getelementptr inbounds %struct.S* %.compoundliteral, i64 0, i32 0, i64 1 + store i32 2, i32* %arrayinit.element, align 4 + %arrayinit.element2 = getelementptr inbounds %struct.S* %.compoundliteral, i64 0, i32 0, i64 2 + store i32 3, i32* %arrayinit.element2, align 8 + %arrayinit.start = getelementptr inbounds %struct.S* %.compoundliteral, i64 0, i32 0, i64 3 + %scevgep4 = bitcast i32* %arrayinit.start to i8* + call void @llvm.memset.p0i8.i64(i8* %scevgep4, i8 0, i64 28, i32 4, i1 false) + call void @foo(i32 %a, %struct.S* byval align 8 %.compoundliteral) #3 + ret void +} + +declare void @foo(i32, %struct.S* byval align 8) #1 + +; Function Attrs: nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #3 diff --git a/test/CodeGen/BPF/cc_args.ll b/test/CodeGen/BPF/cc_args.ll new file mode 100644 index 0000000..5085fe5 --- /dev/null +++ b/test/CodeGen/BPF/cc_args.ll @@ -0,0 +1,96 @@ +; RUN: llc < %s -march=bpf -show-mc-encoding | FileCheck %s +; test little endian only for now + +define void @test() #0 { +entry: +; CHECK: test: + +; CHECK: mov r1, 123 # encoding: [0xb7,0x01,0x00,0x00,0x7b,0x00,0x00,0x00] +; CHECK: call f_i16 + call void @f_i16(i16 123) + +; CHECK: mov r1, 12345678 # encoding: [0xb7,0x01,0x00,0x00,0x4e,0x61,0xbc,0x00] +; CHECK: call f_i32 + call void @f_i32(i32 12345678) + +; CHECK: ld_64 r1, 72623859790382856 # encoding: [0x18,0x01,0x00,0x00,0x08,0x07,0x06,0x05,0x00,0x00,0x00,0x00,0x04,0x03,0x02,0x01] +; CHECK: call f_i64 + call void @f_i64(i64 72623859790382856) + +; CHECK: mov r1, 1234 +; CHECK: mov r2, 5678 +; CHECK: call f_i32_i32 + call void @f_i32_i32(i32 1234, i32 5678) + +; CHECK: mov r1, 2 +; CHECK: mov r2, 3 +; CHECK: mov r3, 4 +; CHECK: call f_i16_i32_i16 + call void @f_i16_i32_i16(i16 2, i32 3, i16 4) + +; CHECK: mov r1, 5 +; CHECK: ld_64 r2, 7262385979038285 +; CHECK: mov r3, 6 +; CHECK: call f_i16_i64_i16 + call void @f_i16_i64_i16(i16 5, i64 7262385979038285, i16 6) + + ret void +} + +@g_i16 = common global i16 0, align 2 +@g_i32 = common global i32 0, align 2 +@g_i64 = common global i64 0, align 4 + +define void @f_i16(i16 %a) #0 { +; CHECK: f_i16: +; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00] + store volatile i16 %a, i16* @g_i16, align 2 + ret void +} + +define void @f_i32(i32 %a) #0 { +; CHECK: f_i32: +; CHECK: sth 0(r2), r1 # encoding: [0x6b,0x12,0x00,0x00,0x00,0x00,0x00,0x00] +; CHECK: sth 2(r2), r1 # encoding: [0x6b,0x12,0x02,0x00,0x00,0x00,0x00,0x00] + store volatile i32 %a, i32* @g_i32, align 2 + ret void +} + +define void @f_i64(i64 %a) #0 { +; CHECK: f_i64: +; CHECK: stw 0(r2), r1 +; CHECK: stw 4(r2), r1 # encoding: [0x63,0x12,0x04,0x00,0x00,0x00,0x00,0x00] + store volatile i64 %a, i64* @g_i64, align 2 + ret void +} + +define void @f_i32_i32(i32 %a, i32 %b) #0 { +; CHECK: f_i32_i32: +; CHECK: stw 0(r3), r1 + store volatile i32 %a, i32* @g_i32, align 4 +; CHECK: stw 0(r3), r2 + store volatile i32 %b, i32* @g_i32, align 4 + ret void +} + +define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 { +; CHECK: f_i16_i32_i16: +; CHECK: sth 0(r4), r1 + store volatile i16 %a, i16* @g_i16, align 2 +; CHECK: stw 0(r1), r2 + store volatile i32 %b, i32* @g_i32, align 4 +; CHECK: sth 0(r4), r3 + store volatile i16 %c, i16* @g_i16, align 2 + ret void +} + +define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 { +; CHECK: f_i16_i64_i16: +; CHECK: sth 0(r4), r1 + store volatile i16 %a, i16* @g_i16, align 2 +; CHECK: std 0(r1), r2 # encoding: [0x7b,0x21,0x00,0x00,0x00,0x00,0x00,0x00] + store volatile i64 %b, i64* @g_i64, align 8 +; CHECK: sth 0(r4), r3 + store volatile i16 %c, i16* @g_i16, align 2 + ret void +} diff --git a/test/CodeGen/BPF/cc_ret.ll b/test/CodeGen/BPF/cc_ret.ll new file mode 100644 index 0000000..e32b17b --- /dev/null +++ b/test/CodeGen/BPF/cc_ret.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=bpf | FileCheck %s + +define void @test() #0 { +entry: +; CHECK: test: + +; CHECK: call f_i16 +; CHECK: sth 0(r1), r0 + %0 = call i16 @f_i16() + store volatile i16 %0, i16* @g_i16 + +; CHECK: call f_i32 +; CHECK: stw 0(r1), r0 + %1 = call i32 @f_i32() + store volatile i32 %1, i32* @g_i32 + +; CHECK: call f_i64 +; CHECK: std 0(r1), r0 + %2 = call i64 @f_i64() + store volatile i64 %2, i64* @g_i64 + + ret void +} + +@g_i16 = common global i16 0, align 2 +@g_i32 = common global i32 0, align 2 +@g_i64 = common global i64 0, align 2 + +define i16 @f_i16() #0 { +; CHECK: f_i16: +; CHECK: mov r0, 1 +; CHECK: ret + ret i16 1 +} + +define i32 @f_i32() #0 { +; CHECK: f_i32: +; CHECK: mov r0, 16909060 +; CHECK: ret + ret i32 16909060 +} + +define i64 @f_i64() #0 { +; CHECK: f_i64: +; CHECK: ld_64 r0, 72623859790382856 +; CHECK: ret + ret i64 72623859790382856 +} diff --git a/test/CodeGen/BPF/cmp.ll b/test/CodeGen/BPF/cmp.ll new file mode 100644 index 0000000..b353f90 --- /dev/null +++ b/test/CodeGen/BPF/cmp.ll @@ -0,0 +1,119 @@ +; RUN: llc < %s -march=bpf | FileCheck %s + +; Function Attrs: nounwind readnone uwtable +define signext i8 @foo_cmp1(i8 signext %a, i8 signext %b) #0 { + %1 = icmp sgt i8 %a, %b + br i1 %1, label %2, label %4 + +;