From 6a7770b7ae43d784dec6f4d3c73ffed6166f3882 Mon Sep 17 00:00:00 2001 From: Andrew Trick Date: Tue, 15 Oct 2013 23:33:07 +0000 Subject: Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192750 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/DebugInfo/X86/dbg-value-dag-combine.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'test/DebugInfo') diff --git a/test/DebugInfo/X86/dbg-value-dag-combine.ll b/test/DebugInfo/X86/dbg-value-dag-combine.ll index 17cbf9f..c07dcf8 100644 --- a/test/DebugInfo/X86/dbg-value-dag-combine.ll +++ b/test/DebugInfo/X86/dbg-value-dag-combine.ll @@ -16,7 +16,7 @@ entry: call void @llvm.dbg.value(metadata !12, i64 0, metadata !13), !dbg !14 %tmp2 = load i32 addrspace(1)* %ip, align 4, !dbg !15 %tmp3 = add i32 0, %tmp2, !dbg !15 -; CHECK: ##DEBUG_VALUE: idx <- EAX{{$}} +; CHECK: ##DEBUG_VALUE: idx <- E{{..$}} call void @llvm.dbg.value(metadata !{i32 %tmp3}, i64 0, metadata !13), !dbg !15 %arrayidx = getelementptr i32 addrspace(1)* %ip, i32 %1, !dbg !16 -- cgit v1.1