From 42fac8ee3bc02e18a5887800e812af762b45b9eb Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Mon, 11 Oct 2010 23:16:21 +0000 Subject: MC machine encoding for simple aritmetic instructions that use a shifted register operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/ARM/simple-encoding.ll | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'test/MC/ARM/simple-encoding.ll') diff --git a/test/MC/ARM/simple-encoding.ll b/test/MC/ARM/simple-encoding.ll index 2da4e74..4c23c7e7 100644 --- a/test/MC/ARM/simple-encoding.ll +++ b/test/MC/ARM/simple-encoding.ll @@ -8,8 +8,8 @@ define i32 @foo(i32 %a, i32 %b) nounwind ssp { entry: ; CHECK: foo -; CHECK: 0xf0,0x00,0xf0,0x07 -; CHECK: 0x1e,0xff,0x2f,0xe1 +; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07] +; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] tail call void @llvm.trap() ret i32 undef @@ -18,9 +18,21 @@ entry: define i32 @f2(i32 %a, i32 %b) nounwind readnone ssp { entry: ; CHECK: f2 -; CHECK: 0x00,0x00,0x81,0xe0 -; CHECK: 0x1e,0xff,0x2f,0xe1 +; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0] +; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] %add = add nsw i32 %b, %a ret i32 %add } + + +define i32 @f3(i32 %a, i32 %b) nounwind readnone ssp { +entry: +; CHECK: f3 +; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0] +; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1] + %mul = shl i32 %b, 3 + %add = add nsw i32 %mul, %a + ret i32 %add +} + declare void @llvm.trap() nounwind -- cgit v1.1