From a45e3747e612c00ca4933087d883db77f4547571 Mon Sep 17 00:00:00 2001
From: Jim Grosbach <grosbach@apple.com>
Date: Fri, 30 Mar 2012 18:53:01 +0000
Subject: ARM encoding for VSWP got the second operand incorrect.

Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/MC/ARM/neon-vswp.s | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 test/MC/ARM/neon-vswp.s

(limited to 'test/MC/ARM')

diff --git a/test/MC/ARM/neon-vswp.s b/test/MC/ARM/neon-vswp.s
new file mode 100644
index 0000000..2138eed
--- /dev/null
+++ b/test/MC/ARM/neon-vswp.s
@@ -0,0 +1,7 @@
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
+
+vswp d1, d2
+vswp q1, q2
+
+@ CHECK: vswp	d1, d2                  @ encoding: [0x02,0x10,0xb2,0xf3]
+@ CHECK: vswp	q1, q2                  @ encoding: [0x44,0x20,0xb2,0xf3]
-- 
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