From 01b0e94bb731310e72f66977e4b57cd3f3280ba4 Mon Sep 17 00:00:00 2001 From: Tim Northover Date: Tue, 22 Oct 2013 19:00:39 +0000 Subject: ARM: provide diagnostics on more writeback LDM/STM instructions The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193185 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/Disassembler/ARM/invalid-thumbv7.txt | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'test/MC/Disassembler') diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/test/MC/Disassembler/ARM/invalid-thumbv7.txt index 1697084..2c84b8a 100644 --- a/test/MC/Disassembler/ARM/invalid-thumbv7.txt +++ b/test/MC/Disassembler/ARM/invalid-thumbv7.txt @@ -389,3 +389,19 @@ [0x80 0xf9 0x30 0x0b] # CHECK: invalid instruction encoding # CHECK-NEXT: [0x80 0xf9 0x30 0x0b] + + +#------------------------------------------------------------------------------ +# Unpredictable STMs +#------------------------------------------------------------------------------ + +# 32-bit Thumb STM instructions cannot have a writeback register which appears +# in the list. + +[0xa1,0xe8,0x07,0x04] +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: [0xa1,0xe8,0x07,0x04] + +[0x21,0xe9,0x07,0x04] +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: [0x21,0xe9,0x07,0x04] -- cgit v1.1