From 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 Mon Sep 17 00:00:00 2001 From: Pirama Arumuga Nainar Date: Wed, 6 May 2015 11:46:36 -0700 Subject: Update aosp/master LLVM for rebase to r235153 Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987) --- test/TableGen/AsmPredicateCondsEmission.td | 31 ++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 test/TableGen/AsmPredicateCondsEmission.td (limited to 'test/TableGen') diff --git a/test/TableGen/AsmPredicateCondsEmission.td b/test/TableGen/AsmPredicateCondsEmission.td new file mode 100644 index 0000000..ba5898f --- /dev/null +++ b/test/TableGen/AsmPredicateCondsEmission.td @@ -0,0 +1,31 @@ +// RUN: llvm-tblgen -gen-disassembler -I %p/../../include %s | FileCheck %s + +// Check that we don't generate invalid code of the form "( && Cond2)" when +// emitting AssemblerPredicate conditions. In the example below, the invalid +// code would be: "return ( && (Bits & arch::AssemblerCondition2));". + +include "llvm/Target/Target.td" + +def archInstrInfo : InstrInfo { } + +def arch : Target { + let InstructionSet = archInstrInfo; +} + +def Pred1 : Predicate<"Condition1">; +def Pred2 : Predicate<"Condition2">, + AssemblerPredicate<"AssemblerCondition2">; + +def foo : Instruction { + let Size = 2; + let OutOperandList = (outs); + let InOperandList = (ins); + field bits<16> Inst; + let Inst = 0xAAAA; + let AsmString = "foo"; + field bits<16> SoftFail = 0; + // This is the important bit: + let Predicates = [Pred1, Pred2]; +} + +// CHECK: return ((Bits & arch::AssemblerCondition2)); -- cgit v1.1