From fd22019ec36e8335254430e61a1e5a3f8a681f6a Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Sat, 17 Nov 2012 00:05:06 +0000 Subject: Teach SROA rewriteVectorizedStoreInst to handle cases when the loaded value is narrower than the stored value. rdar://12713675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168227 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/Transforms/SROA/vector-extract.ll | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 test/Transforms/SROA/vector-extract.ll (limited to 'test/Transforms') diff --git a/test/Transforms/SROA/vector-extract.ll b/test/Transforms/SROA/vector-extract.ll new file mode 100644 index 0000000..2ca6168 --- /dev/null +++ b/test/Transforms/SROA/vector-extract.ll @@ -0,0 +1,25 @@ +; RUN: opt < %s -sroa -S | FileCheck %s +; rdar://12713675 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +define <2 x i16> @test1(i64 %x) nounwind ssp { +; CHECK: @test1 +entry: + %tmp = alloca i64, align 8 + br i1 undef, label %bb1, label %bb2 +; CHECK-NOT: alloca + +bb1: + store i64 %x, i64* %tmp, align 8 +; CHECK-NOT: store + %0 = bitcast i64* %tmp to <2 x i16>* + %1 = load <2 x i16>* %0, align 8 +; CHECK-NOT: load +; CHECK: trunc i64 %x to i32 +; CHECK: bitcast i32 + ret <2 x i16> %1 + +bb2: + ret <2 x i16> < i16 0, i16 0 > +} -- cgit v1.1