From 2015236dfcd40f0b93e7d9f6dc4c380dc88bf3c0 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Mon, 16 Jul 2012 14:17:19 +0000 Subject: test/CodeGen/R600: Add some basic tests v6 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160273 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/R600/fadd.ll | 15 +++++++++++++++ test/CodeGen/R600/fadd.ll.check | Bin 0 -> 48 bytes test/CodeGen/R600/fmul.ll | 15 +++++++++++++++ test/CodeGen/R600/fmul.ll.check | Bin 0 -> 48 bytes test/CodeGen/R600/fsub.ll | 15 +++++++++++++++ test/CodeGen/R600/fsub.ll.check | Bin 0 -> 96 bytes test/CodeGen/R600/lit.local.cfg | 13 +++++++++++++ test/CodeGen/R600/llvm.AMDGPU.cos.ll | 15 +++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.cos.ll.check | Bin 0 -> 144 bytes test/CodeGen/R600/llvm.AMDGPU.floor.ll | 15 +++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.floor.ll.check | Bin 0 -> 48 bytes test/CodeGen/R600/llvm.AMDGPU.mul.ll | 16 ++++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.mul.ll.check | Bin 0 -> 48 bytes test/CodeGen/R600/llvm.AMDGPU.pow.ll | 16 ++++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.pow.ll.check | Bin 0 -> 144 bytes test/CodeGen/R600/llvm.AMDGPU.rcp.ll | 15 +++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check | Bin 0 -> 48 bytes test/CodeGen/R600/llvm.AMDGPU.sin.ll | 15 +++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.sin.ll.check | Bin 0 -> 144 bytes test/CodeGen/R600/llvm.AMDGPU.trunc.ll | 15 +++++++++++++++ test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check | Bin 0 -> 48 bytes test/CodeGen/R600/llvm.AMDIL.fabs..ll | 15 +++++++++++++++ test/CodeGen/R600/llvm.AMDIL.fabs..ll.check | Bin 0 -> 48 bytes test/CodeGen/R600/llvm.AMDIL.max..ll | 16 ++++++++++++++++ test/CodeGen/R600/llvm.AMDIL.max..ll.check | Bin 0 -> 48 bytes test/CodeGen/R600/llvm.AMDIL.min..ll | 16 ++++++++++++++++ test/CodeGen/R600/llvm.AMDIL.min..ll.check | Bin 0 -> 48 bytes 27 files changed, 212 insertions(+) create mode 100644 test/CodeGen/R600/fadd.ll create mode 100644 test/CodeGen/R600/fadd.ll.check create mode 100644 test/CodeGen/R600/fmul.ll create mode 100644 test/CodeGen/R600/fmul.ll.check create mode 100644 test/CodeGen/R600/fsub.ll create mode 100644 test/CodeGen/R600/fsub.ll.check create mode 100644 test/CodeGen/R600/lit.local.cfg create mode 100644 test/CodeGen/R600/llvm.AMDGPU.cos.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.cos.ll.check create mode 100644 test/CodeGen/R600/llvm.AMDGPU.floor.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.floor.ll.check create mode 100644 test/CodeGen/R600/llvm.AMDGPU.mul.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.mul.ll.check create mode 100644 test/CodeGen/R600/llvm.AMDGPU.pow.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.pow.ll.check create mode 100644 test/CodeGen/R600/llvm.AMDGPU.rcp.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check create mode 100644 test/CodeGen/R600/llvm.AMDGPU.sin.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.sin.ll.check create mode 100644 test/CodeGen/R600/llvm.AMDGPU.trunc.ll create mode 100644 test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check create mode 100644 test/CodeGen/R600/llvm.AMDIL.fabs..ll create mode 100644 test/CodeGen/R600/llvm.AMDIL.fabs..ll.check create mode 100644 test/CodeGen/R600/llvm.AMDIL.max..ll create mode 100644 test/CodeGen/R600/llvm.AMDIL.max..ll.check create mode 100644 test/CodeGen/R600/llvm.AMDIL.min..ll create mode 100644 test/CodeGen/R600/llvm.AMDIL.min..ll.check (limited to 'test') diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll new file mode 100644 index 0000000..874fcc6 --- /dev/null +++ b/test/CodeGen/R600/fadd.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = fadd float %r0, %r1 + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + diff --git a/test/CodeGen/R600/fadd.ll.check b/test/CodeGen/R600/fadd.ll.check new file mode 100644 index 0000000..886082f Binary files /dev/null and b/test/CodeGen/R600/fadd.ll.check differ diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll new file mode 100644 index 0000000..28bc4d8 --- /dev/null +++ b/test/CodeGen/R600/fmul.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = fmul float %r0, %r1 + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + diff --git a/test/CodeGen/R600/fmul.ll.check b/test/CodeGen/R600/fmul.ll.check new file mode 100644 index 0000000..9ba36cc Binary files /dev/null and b/test/CodeGen/R600/fmul.ll.check differ diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll new file mode 100644 index 0000000..8e43128 --- /dev/null +++ b/test/CodeGen/R600/fsub.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = fsub float %r0, %r1 + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + diff --git a/test/CodeGen/R600/fsub.ll.check b/test/CodeGen/R600/fsub.ll.check new file mode 100644 index 0000000..7999354 Binary files /dev/null and b/test/CodeGen/R600/fsub.ll.check differ diff --git a/test/CodeGen/R600/lit.local.cfg b/test/CodeGen/R600/lit.local.cfg new file mode 100644 index 0000000..79fc2ba --- /dev/null +++ b/test/CodeGen/R600/lit.local.cfg @@ -0,0 +1,13 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +def getRoot(config): + if not config.parent: + return config + return getRoot(config.parent) + +root = getRoot(config) + +targets = set(root.targets_to_build.split()) +if not 'AMDGPU' in targets: + config.unsupported = True + diff --git a/test/CodeGen/R600/llvm.AMDGPU.cos.ll b/test/CodeGen/R600/llvm.AMDGPU.cos.ll new file mode 100644 index 0000000..8db9563 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.cos.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.cos( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.cos(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check b/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check new file mode 100644 index 0000000..ef1389b Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDGPU.cos.ll.check differ diff --git a/test/CodeGen/R600/llvm.AMDGPU.floor.ll b/test/CodeGen/R600/llvm.AMDGPU.floor.ll new file mode 100644 index 0000000..729a783 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.floor.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.floor( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.floor(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check b/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check new file mode 100644 index 0000000..324c10d Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDGPU.floor.ll.check differ diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll b/test/CodeGen/R600/llvm.AMDGPU.mul.ll new file mode 100644 index 0000000..3c995c9 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.mul.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = call float @llvm.AMDGPU.mul( float %r0, float %r1) + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.mul(float ,float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check b/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check new file mode 100644 index 0000000..0a79cba Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDGPU.mul.ll.check differ diff --git a/test/CodeGen/R600/llvm.AMDGPU.pow.ll b/test/CodeGen/R600/llvm.AMDGPU.pow.ll new file mode 100644 index 0000000..b692081 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.pow.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = call float @llvm.AMDGPU.pow( float %r0, float %r1) + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.pow(float ,float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check b/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check new file mode 100644 index 0000000..94af645 Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDGPU.pow.ll.check differ diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll new file mode 100644 index 0000000..3efae49 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.rcp( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.rcp(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check new file mode 100644 index 0000000..75fe90c Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDGPU.rcp.ll.check differ diff --git a/test/CodeGen/R600/llvm.AMDGPU.sin.ll b/test/CodeGen/R600/llvm.AMDGPU.sin.ll new file mode 100644 index 0000000..6a427b5 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.sin.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.sin( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.sin(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check b/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check new file mode 100644 index 0000000..5353554 Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDGPU.sin.ll.check differ diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll new file mode 100644 index 0000000..fcabcac --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDGPU.trunc( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDGPU.trunc(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check new file mode 100644 index 0000000..f9c93b3 Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll.check differ diff --git a/test/CodeGen/R600/llvm.AMDIL.fabs..ll b/test/CodeGen/R600/llvm.AMDIL.fabs..ll new file mode 100644 index 0000000..1143036 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDIL.fabs..ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.AMDIL.fabs.( float %r0) + call void @llvm.AMDGPU.store.output(float %r1, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDIL.fabs.(float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check b/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check new file mode 100644 index 0000000..ff3124c Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDIL.fabs..ll.check differ diff --git a/test/CodeGen/R600/llvm.AMDIL.max..ll b/test/CodeGen/R600/llvm.AMDIL.max..ll new file mode 100644 index 0000000..3373712 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDIL.max..ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = call float @llvm.AMDIL.max.( float %r0, float %r1) + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDIL.max.(float ,float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDIL.max..ll.check b/test/CodeGen/R600/llvm.AMDIL.max..ll.check new file mode 100644 index 0000000..9ae4070 Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDIL.max..ll.check differ diff --git a/test/CodeGen/R600/llvm.AMDIL.min..ll b/test/CodeGen/R600/llvm.AMDIL.min..ll new file mode 100644 index 0000000..76a8718 --- /dev/null +++ b/test/CodeGen/R600/llvm.AMDIL.min..ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | diff %s.check - + + +define void @test() { + %r0 = call float @llvm.R600.load.input(i32 0) + %r1 = call float @llvm.R600.load.input(i32 1) + %r2 = call float @llvm.AMDIL.min.( float %r0, float %r1) + call void @llvm.AMDGPU.store.output(float %r2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) + +declare float @llvm.AMDIL.min.(float ,float ) readnone diff --git a/test/CodeGen/R600/llvm.AMDIL.min..ll.check b/test/CodeGen/R600/llvm.AMDIL.min..ll.check new file mode 100644 index 0000000..3d343bd Binary files /dev/null and b/test/CodeGen/R600/llvm.AMDIL.min..ll.check differ -- cgit v1.1