From 2a2a323488a31fbdb3524f7f288b8e5c3fc3b7c3 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Tue, 3 Dec 2013 11:05:09 +0000 Subject: Merging r196267: ------------------------------------------------------------------------ r196267 | rsandifo | 2013-12-03 11:01:54 +0000 (Tue, 03 Dec 2013) | 12 lines [SystemZ] Fix choice of known-zero mask in insertion optimization The backend converts 64-bit ORs into subreg moves if the upper 32 bits of one operand and the low 32 bits of the other are known to be zero. It then tries to peel away redundant ANDs from the upper 32 bits. Since AND masks are canonicalized to exclude known-zero bits, the test ORs the mask and the known-zero bits together before checking for redundancy. The problem was that it was using the wrong node when checking for known-zero bits, so could drop ANDs that were still needed. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196268 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/SystemZ/insert-06.ll | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'test') diff --git a/test/CodeGen/SystemZ/insert-06.ll b/test/CodeGen/SystemZ/insert-06.ll index 8366b2c..edcd0c5 100644 --- a/test/CodeGen/SystemZ/insert-06.ll +++ b/test/CodeGen/SystemZ/insert-06.ll @@ -165,3 +165,16 @@ define i64 @f13(i64 %a, i32 %b) { %or = or i64 %shift, %low ret i64 %or } + +; We previously wrongly removed the upper AND as dead. +define i64 @f14(i64 %a, i64 %b) { +; CHECK-LABEL: f14: +; CHECK: risbg {{%r[0-5]}}, %r2, 6, 134, 0 +; CHECK: br %r14 + %and1 = and i64 %a, 144115188075855872 + %and2 = and i64 %b, 15 + %or = or i64 %and1, %and2 + %res = icmp eq i64 %or, 0 + %ext = sext i1 %res to i64 + ret i64 %ext +} -- cgit v1.1