From 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 Mon Sep 17 00:00:00 2001 From: Pirama Arumuga Nainar Date: Wed, 6 May 2015 11:46:36 -0700 Subject: Update aosp/master LLVM for rebase to r235153 Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987) --- .../BasicAA/2006-03-03-BadArraySubscript.ll | 2 +- test/Analysis/BasicAA/2008-04-15-Byval.ll | 2 +- test/Analysis/BasicAA/byval.ll | 2 +- test/Analysis/BlockFrequencyInfo/bad_input.ll | 3 +- .../BlockFrequencyInfo/loops_with_profile_info.ll | 204 ++++ test/Analysis/BranchProbabilityInfo/basic.ll | 28 + test/Analysis/CallGraph/2008-09-09-DirectCall.ll | 2 +- test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll | 198 ++++ .../DivergenceAnalysis/NVPTX/lit.local.cfg | 2 + test/Analysis/GlobalsModRef/volatile-instrs.ll | 2 +- test/Analysis/LazyCallGraph/basic.ll | 2 +- .../backward-dep-different-types.ll | 1 - test/Analysis/LoopAccessAnalysis/safe-no-checks.ll | 43 + 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+++ b/test/Analysis/BasicAA/2006-03-03-BadArraySubscript.ll @@ -26,7 +26,7 @@ no_exit: ; preds = %no_exit, %entry loopexit: ; preds = %no_exit, %entry %Y.0.1 = phi i32 [ 0, %entry ], [ %tmp.13, %no_exit ] ; [#uses=1] %tmp.4 = getelementptr [3 x [3 x i32]], [3 x [3 x i32]]* %X, i32 0, i32 0 ; <[3 x i32]*> [#uses=1] - %tmp.15 = call i32 (...)* @foo( [3 x i32]* %tmp.4, i32 %Y.0.1 ) ; [#uses=0] + %tmp.15 = call i32 (...) @foo( [3 x i32]* %tmp.4, i32 %Y.0.1 ) ; [#uses=0] ret void } diff --git a/test/Analysis/BasicAA/2008-04-15-Byval.ll b/test/Analysis/BasicAA/2008-04-15-Byval.ll index 9df12bd..9d4fd14 100644 --- a/test/Analysis/BasicAA/2008-04-15-Byval.ll +++ b/test/Analysis/BasicAA/2008-04-15-Byval.ll @@ -10,7 +10,7 @@ entry: %tmp = getelementptr %struct.x, %struct.x* %X, i32 0, i32 0 ; <[4 x i32]*> [#uses=1] %tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp, i32 0, i32 3 ; [#uses=1] store i32 2, i32* %tmp1, align 4 - %tmp2 = call i32 (...)* @bar( %struct.x* byval align 4 %X ) nounwind ; [#uses=0] + %tmp2 = call i32 (...) @bar( %struct.x* byval align 4 %X ) nounwind ; [#uses=0] br label %return return: ; preds = %entry ret void diff --git a/test/Analysis/BasicAA/byval.ll b/test/Analysis/BasicAA/byval.ll index edbe7b3..4f90c3f 100644 --- a/test/Analysis/BasicAA/byval.ll +++ b/test/Analysis/BasicAA/byval.ll @@ -6,7 +6,7 @@ target triple = "i686-apple-darwin8" define i32 @foo(%struct.x* byval %a) nounwind { ; CHECK: ret i32 1 - %tmp1 = tail call i32 (...)* @bar( %struct.x* %a ) nounwind ; [#uses=0] + %tmp1 = tail call i32 (...) @bar( %struct.x* %a ) nounwind ; [#uses=0] %tmp2 = getelementptr %struct.x, %struct.x* %a, i32 0, i32 0 ; [#uses=2] store i32 1, i32* %tmp2, align 4 store i32 2, i32* @g, align 4 diff --git a/test/Analysis/BlockFrequencyInfo/bad_input.ll b/test/Analysis/BlockFrequencyInfo/bad_input.ll index da62dca..e5b1f50 100644 --- a/test/Analysis/BlockFrequencyInfo/bad_input.ll +++ b/test/Analysis/BlockFrequencyInfo/bad_input.ll @@ -32,7 +32,8 @@ define void @infinite_loop(i1 %x) { entry: br i1 %x, label %for.body, label %for.end, !prof !1 -; Check that the loop scale maxes out at 4096, giving 2048 here. +; Check that the infinite loop is arbitrarily scaled to max out at 4096, +; giving 2048 here. ; CHECK-NEXT: for.body: float = 2048.0, for.body: %i = phi i32 [ 0, %entry ], [ %inc, %for.body ] diff --git a/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll b/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll new file mode 100644 index 0000000..534c4ad --- /dev/null +++ b/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll @@ -0,0 +1,204 @@ +; RUN: opt < %s -analyze -block-freq | FileCheck %s + +; This code contains three loops. One is triple-nested, the +; second is double nested and the third is a single loop. At +; runtime, all three loops execute 1,000,000 times each. We use to +; give different frequencies to each of the loops because loop +; scales were limited to no more than 4,096. +; +; This was penalizing the hotness of the second and third loops +; because BFI was reducing the loop scale for for.cond16 and +; for.cond26 to a max of 4,096. +; +; Without this restriction, all loops are now correctly given the same +; frequency values. +; +; Original C code: +; +; +; int g; +; __attribute__((noinline)) void bar() { +; g++; +; } +; +; extern int printf(const char*, ...); +; +; int main() +; { +; int i, j, k; +; +; g = 0; +; for (i = 0; i < 100; i++) +; for (j = 0; j < 100; j++) +; for (k = 0; k < 100; k++) +; bar(); +; +; printf ("g = %d\n", g); +; g = 0; +; +; for (i = 0; i < 100; i++) +; for (j = 0; j < 10000; j++) +; bar(); +; +; printf ("g = %d\n", g); +; g = 0; +; +; +; for (i = 0; i < 1000000; i++) +; bar(); +; +; printf ("g = %d\n", g); +; g = 0; +; } + +@g = common global i32 0, align 4 +@.str = private unnamed_addr constant [8 x i8] c"g = %d\0A\00", align 1 + +declare void @bar() +declare i32 @printf(i8*, ...) + +; CHECK: Printing analysis {{.*}} for function 'main': +; CHECK-NEXT: block-frequency-info: main +define i32 @main() { +entry: + %retval = alloca i32, align 4 + %i = alloca i32, align 4 + %j = alloca i32, align 4 + %k = alloca i32, align 4 + store i32 0, i32* %retval + store i32 0, i32* @g, align 4 + store i32 0, i32* %i, align 4 + br label %for.cond + +for.cond: ; preds = %for.inc10, %entry + %0 = load i32, i32* %i, align 4 + %cmp = icmp slt i32 %0, 100 + br i1 %cmp, label %for.body, label %for.end12, !prof !1 + +for.body: ; preds = %for.cond + store i32 0, i32* %j, align 4 + br label %for.cond1 + +for.cond1: ; preds = %for.inc7, %for.body + %1 = load i32, i32* %j, align 4 + %cmp2 = icmp slt i32 %1, 100 + br i1 %cmp2, label %for.body3, label %for.end9, !prof !2 + +for.body3: ; preds = %for.cond1 + store i32 0, i32* %k, align 4 + br label %for.cond4 + +for.cond4: ; preds = %for.inc, %for.body3 + %2 = load i32, i32* %k, align 4 + %cmp5 = icmp slt i32 %2, 100 + br i1 %cmp5, label %for.body6, label %for.end, !prof !3 + +; CHECK: - for.body6: float = 500000.5, int = 4000003 +for.body6: ; preds = %for.cond4 + call void @bar() + br label %for.inc + +for.inc: ; preds = %for.body6 + %3 = load i32, i32* %k, align 4 + %inc = add nsw i32 %3, 1 + store i32 %inc, i32* %k, align 4 + br label %for.cond4 + +for.end: ; preds = %for.cond4 + br label %for.inc7 + +for.inc7: ; preds = %for.end + %4 = load i32, i32* %j, align 4 + %inc8 = add nsw i32 %4, 1 + store i32 %inc8, i32* %j, align 4 + br label %for.cond1 + +for.end9: ; preds = %for.cond1 + br label %for.inc10 + +for.inc10: ; preds = %for.end9 + %5 = load i32, i32* %i, align 4 + %inc11 = add nsw i32 %5, 1 + store i32 %inc11, i32* %i, align 4 + br label %for.cond + +for.end12: ; preds = %for.cond + %6 = load i32, i32* @g, align 4 + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %6) + store i32 0, i32* @g, align 4 + store i32 0, i32* %i, align 4 + br label %for.cond13 + +for.cond13: ; preds = %for.inc22, %for.end12 + %7 = load i32, i32* %i, align 4 + %cmp14 = icmp slt i32 %7, 100 + br i1 %cmp14, label %for.body15, label %for.end24, !prof !1 + +for.body15: ; preds = %for.cond13 + store i32 0, i32* %j, align 4 + br label %for.cond16 + +for.cond16: ; preds = %for.inc19, %for.body15 + %8 = load i32, i32* %j, align 4 + %cmp17 = icmp slt i32 %8, 10000 + br i1 %cmp17, label %for.body18, label %for.end21, !prof !4 + +; CHECK: - for.body18: float = 500000.5, int = 4000003 +for.body18: ; preds = %for.cond16 + call void @bar() + br label %for.inc19 + +for.inc19: ; preds = %for.body18 + %9 = load i32, i32* %j, align 4 + %inc20 = add nsw i32 %9, 1 + store i32 %inc20, i32* %j, align 4 + br label %for.cond16 + +for.end21: ; preds = %for.cond16 + br label %for.inc22 + +for.inc22: ; preds = %for.end21 + %10 = load i32, i32* %i, align 4 + %inc23 = add nsw i32 %10, 1 + store i32 %inc23, i32* %i, align 4 + br label %for.cond13 + +for.end24: ; preds = %for.cond13 + %11 = load i32, i32* @g, align 4 + %call25 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %11) + store i32 0, i32* @g, align 4 + store i32 0, i32* %i, align 4 + br label %for.cond26 + +for.cond26: ; preds = %for.inc29, %for.end24 + %12 = load i32, i32* %i, align 4 + %cmp27 = icmp slt i32 %12, 1000000 + br i1 %cmp27, label %for.body28, label %for.end31, !prof !5 + +; CHECK: - for.body28: float = 500000.5, int = 4000003 +for.body28: ; preds = %for.cond26 + call void @bar() + br label %for.inc29 + +for.inc29: ; preds = %for.body28 + %13 = load i32, i32* %i, align 4 + %inc30 = add nsw i32 %13, 1 + store i32 %inc30, i32* %i, align 4 + br label %for.cond26 + +for.end31: ; preds = %for.cond26 + %14 = load i32, i32* @g, align 4 + %call32 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str, i32 0, i32 0), i32 %14) + store i32 0, i32* @g, align 4 + %15 = load i32, i32* %retval + ret i32 %15 +} + +!llvm.ident = !{!0} + +!0 = !{!"clang version 3.7.0 (trunk 232635) (llvm/trunk 232636)"} +!1 = !{!"branch_weights", i32 101, i32 2} +!2 = !{!"branch_weights", i32 10001, i32 101} +!3 = !{!"branch_weights", i32 1000001, i32 10001} +!4 = !{!"branch_weights", i32 1000001, i32 101} +!5 = !{!"branch_weights", i32 1000001, i32 2} diff --git a/test/Analysis/BranchProbabilityInfo/basic.ll b/test/Analysis/BranchProbabilityInfo/basic.ll index 0f66911..2c9c156 100644 --- a/test/Analysis/BranchProbabilityInfo/basic.ll +++ b/test/Analysis/BranchProbabilityInfo/basic.ll @@ -212,3 +212,31 @@ exit: ret i32 %result } +define i32 @zero3(i32 %i, i32 %a, i32 %b) { +; CHECK: Printing analysis {{.*}} for function 'zero3' +entry: +; AND'ing with a single bit bitmask essentially leads to a bool comparison, +; meaning we don't have probability information. + %and = and i32 %i, 2 + %tobool = icmp eq i32 %and, 0 + br i1 %tobool, label %then, label %else +; CHECK: edge entry -> then probability is 16 / 32 +; CHECK: edge entry -> else probability is 16 / 32 + +then: +; AND'ing with other bitmask might be something else, so we still assume the +; usual probabilities. + %and2 = and i32 %i, 5 + %tobool2 = icmp eq i32 %and2, 0 + br i1 %tobool2, label %else, label %exit +; CHECK: edge then -> else probability is 12 / 32 +; CHECK: edge then -> exit probability is 20 / 32 + +else: + br label %exit + +exit: + %result = phi i32 [ %a, %then ], [ %b, %else ] + ret i32 %result +} + diff --git a/test/Analysis/CallGraph/2008-09-09-DirectCall.ll b/test/Analysis/CallGraph/2008-09-09-DirectCall.ll index 595cc42..56eac49 100644 --- a/test/Analysis/CallGraph/2008-09-09-DirectCall.ll +++ b/test/Analysis/CallGraph/2008-09-09-DirectCall.ll @@ -12,6 +12,6 @@ entry: define void @caller() { entry: - call void (...)* @callee( void (...)* @callee ) + call void (...) @callee( void (...)* @callee ) unreachable } diff --git a/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll b/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll new file mode 100644 index 0000000..9dd3d55 --- /dev/null +++ b/test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll @@ -0,0 +1,198 @@ +; RUN: opt %s -analyze -divergence | FileCheck %s + +target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" +target triple = "nvptx64-nvidia-cuda" + +; return (n < 0 ? a + threadIdx.x : b + threadIdx.x) +define i32 @no_diverge(i32 %n, i32 %a, i32 %b) { +; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'no_diverge' +entry: + %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() + %cond = icmp slt i32 %n, 0 + br i1 %cond, label %then, label %else ; uniform +; CHECK-NOT: DIVERGENT: br i1 %cond, +then: + %a1 = add i32 %a, %tid + br label %merge +else: + %b2 = add i32 %b, %tid + br label %merge +merge: + %c = phi i32 [ %a1, %then ], [ %b2, %else ] + ret i32 %c +} + +; c = a; +; if (threadIdx.x < 5) // divergent: data dependent +; c = b; +; return c; // c is divergent: sync dependent +define i32 @sync(i32 %a, i32 %b) { +; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'sync' +bb1: + %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.y() + %cond = icmp slt i32 %tid, 5 + br i1 %cond, label %bb2, label %bb3 +; CHECK: DIVERGENT: br i1 %cond, +bb2: + br label %bb3 +bb3: + %c = phi i32 [ %a, %bb1 ], [ %b, %bb2 ] ; sync dependent on tid +; CHECK: DIVERGENT: %c = + ret i32 %c +} + +; c = 0; +; if (threadIdx.x >= 5) { // divergent +; c = (n < 0 ? a : b); // c here is uniform because n is uniform +; } +; // c here is divergent because it is sync dependent on threadIdx.x >= 5 +; return c; +define i32 @mixed(i32 %n, i32 %a, i32 %b) { +; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'mixed' +bb1: + %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.z() + %cond = icmp slt i32 %tid, 5 + br i1 %cond, label %bb6, label %bb2 +; CHECK: DIVERGENT: br i1 %cond, +bb2: + %cond2 = icmp slt i32 %n, 0 + br i1 %cond2, label %bb4, label %bb3 +bb3: + br label %bb5 +bb4: + br label %bb5 +bb5: + %c = phi i32 [ %a, %bb3 ], [ %b, %bb4 ] +; CHECK-NOT: DIVERGENT: %c = + br label %bb6 +bb6: + %c2 = phi i32 [ 0, %bb1], [ %c, %bb5 ] +; CHECK: DIVERGENT: %c2 = + ret i32 %c2 +} + +; We conservatively treats all parameters of a __device__ function as divergent. +define i32 @device(i32 %n, i32 %a, i32 %b) { +; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'device' +; CHECK: DIVERGENT: i32 %n +; CHECK: DIVERGENT: i32 %a +; CHECK: DIVERGENT: i32 %b +entry: + %cond = icmp slt i32 %n, 0 + br i1 %cond, label %then, label %else +; CHECK: DIVERGENT: br i1 %cond, +then: + br label %merge +else: + br label %merge +merge: + %c = phi i32 [ %a, %then ], [ %b, %else ] + ret i32 %c +} + +; int i = 0; +; do { +; i++; // i here is uniform +; } while (i < laneid); +; return i == 10 ? 0 : 1; // i here is divergent +; +; The i defined in the loop is used outside. +define i32 @loop() { +; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'loop' +entry: + %laneid = call i32 @llvm.ptx.read.laneid() + br label %loop +loop: + %i = phi i32 [ 0, %entry ], [ %i1, %loop ] +; CHECK-NOT: DIVERGENT: %i = + %i1 = add i32 %i, 1 + %exit_cond = icmp sge i32 %i1, %laneid + br i1 %exit_cond, label %loop_exit, label %loop +loop_exit: + %cond = icmp eq i32 %i, 10 + br i1 %cond, label %then, label %else +; CHECK: DIVERGENT: br i1 %cond, +then: + ret i32 0 +else: + ret i32 1 +} + +; Same as @loop, but the loop is in the LCSSA form. +define i32 @lcssa() { +; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'lcssa' +entry: + %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() + br label %loop +loop: + %i = phi i32 [ 0, %entry ], [ %i1, %loop ] +; CHECK-NOT: DIVERGENT: %i = + %i1 = add i32 %i, 1 + %exit_cond = icmp sge i32 %i1, %tid + br i1 %exit_cond, label %loop_exit, label %loop +loop_exit: + %i.lcssa = phi i32 [ %i, %loop ] +; CHECK: DIVERGENT: %i.lcssa = + %cond = icmp eq i32 %i.lcssa, 10 + br i1 %cond, label %then, label %else +; CHECK: DIVERGENT: br i1 %cond, +then: + ret i32 0 +else: + ret i32 1 +} + +; This test contains an unstructured loop. +; +-------------- entry ----------------+ +; | | +; V V +; i1 = phi(0, i3) i2 = phi(0, i3) +; j1 = i1 + 1 ---> i3 = phi(j1, j2) <--- j2 = i2 + 2 +; ^ | ^ +; | V | +; +-------- switch (tid / i3) ----------+ +; | +; V +; if (i3 == 5) // divergent +; because sync dependent on (tid / i3). +define i32 @unstructured_loop(i1 %entry_cond) { +; CHECK-LABEL: Printing analysis 'Divergence Analysis' for function 'unstructured_loop' +entry: + %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() + br i1 %entry_cond, label %loop_entry_1, label %loop_entry_2 +loop_entry_1: + %i1 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ] + %j1 = add i32 %i1, 1 + br label %loop_body +loop_entry_2: + %i2 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ] + %j2 = add i32 %i2, 2 + br label %loop_body +loop_body: + %i3 = phi i32 [ %j1, %loop_entry_1 ], [ %j2, %loop_entry_2 ] + br label %loop_latch +loop_latch: + %div = sdiv i32 %tid, %i3 + switch i32 %div, label %branch [ i32 1, label %loop_entry_1 + i32 2, label %loop_entry_2 ] +branch: + %cmp = icmp eq i32 %i3, 5 + br i1 %cmp, label %then, label %else +; CHECK: DIVERGENT: br i1 %cmp, +then: + ret i32 0 +else: + ret i32 1 +} + +declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() +declare i32 @llvm.nvvm.read.ptx.sreg.tid.y() +declare i32 @llvm.nvvm.read.ptx.sreg.tid.z() +declare i32 @llvm.ptx.read.laneid() + +!nvvm.annotations = !{!0, !1, !2, !3, !4} +!0 = !{i32 (i32, i32, i32)* @no_diverge, !"kernel", i32 1} +!1 = !{i32 (i32, i32)* @sync, !"kernel", i32 1} +!2 = !{i32 (i32, i32, i32)* @mixed, !"kernel", i32 1} +!3 = !{i32 ()* @loop, !"kernel", i32 1} +!4 = !{i32 (i1)* @unstructured_loop, !"kernel", i32 1} diff --git a/test/Analysis/DivergenceAnalysis/NVPTX/lit.local.cfg b/test/Analysis/DivergenceAnalysis/NVPTX/lit.local.cfg new file mode 100644 index 0000000..2cb98eb --- /dev/null +++ b/test/Analysis/DivergenceAnalysis/NVPTX/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'NVPTX' in config.root.targets: + config.unsupported = True diff --git a/test/Analysis/GlobalsModRef/volatile-instrs.ll b/test/Analysis/GlobalsModRef/volatile-instrs.ll index a331bf3..5dd47bc 100644 --- a/test/Analysis/GlobalsModRef/volatile-instrs.ll +++ b/test/Analysis/GlobalsModRef/volatile-instrs.ll @@ -25,6 +25,6 @@ main_entry: %0 = load volatile i32, i32* getelementptr inbounds (%struct.anon, %struct.anon* @b, i64 0, i32 0), align 4 store i32 %0, i32* @c, align 4 tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.anon* @b to i8*), i8* bitcast (%struct.anon* @a to i8*), i64 12, i32 4, i1 false) nounwind - %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %0) nounwind + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %0) nounwind ret i32 0 } diff --git a/test/Analysis/LazyCallGraph/basic.ll b/test/Analysis/LazyCallGraph/basic.ll index 6e2cb90..7c13d2b 100644 --- a/test/Analysis/LazyCallGraph/basic.ll +++ b/test/Analysis/LazyCallGraph/basic.ll @@ -90,7 +90,7 @@ next: select i1 true, void ()* @f3, void ()* @f4 store void ()* @f5, void ()** %x call void @f6() - call void (void ()*, void ()*)* bitcast (void ()* @f7 to void (void ()*, void ()*)*)(void ()* @f8, void ()* @f9) + call void (void ()*, void ()*) bitcast (void ()* @f7 to void (void ()*, void ()*)*)(void ()* @f8, void ()* @f9) invoke void @f10() to label %exit unwind label %unwind exit: diff --git a/test/Analysis/LoopAccessAnalysis/backward-dep-different-types.ll b/test/Analysis/LoopAccessAnalysis/backward-dep-different-types.ll index 238f3f4..5d4fb7d 100644 --- a/test/Analysis/LoopAccessAnalysis/backward-dep-different-types.ll +++ b/test/Analysis/LoopAccessAnalysis/backward-dep-different-types.ll @@ -14,7 +14,6 @@ target triple = "x86_64-apple-macosx10.10.0" ; CHECK: Report: unsafe dependent memory operations in loop ; CHECK-NOT: Memory dependences are safe -@n = global i32 20, align 4 @B = common global i32* null, align 8 @A = common global i32* null, align 8 diff --git a/test/Analysis/LoopAccessAnalysis/safe-no-checks.ll b/test/Analysis/LoopAccessAnalysis/safe-no-checks.ll new file mode 100644 index 0000000..fa70c02 --- /dev/null +++ b/test/Analysis/LoopAccessAnalysis/safe-no-checks.ll @@ -0,0 +1,43 @@ +; RUN: opt -basicaa -loop-accesses -analyze < %s | FileCheck %s + +; If the arrays don't alias this loop is safe with no memchecks: +; for (i = 0; i < n; i++) +; A[i] = A[i+1] * B[i] * C[i]; + +target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.10.0" + +; CHECK: Memory dependences are safe{{$}} + +define void @f(i16* noalias %a, + i16* noalias %b, + i16* noalias %c) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %ind = phi i64 [ 0, %entry ], [ %add, %for.body ] + + %add = add nuw nsw i64 %ind, 1 + + %arrayidxA_plus_2 = getelementptr inbounds i16, i16* %a, i64 %add + %loadA_plus_2 = load i16, i16* %arrayidxA_plus_2, align 2 + + %arrayidxB = getelementptr inbounds i16, i16* %b, i64 %ind + %loadB = load i16, i16* %arrayidxB, align 2 + + %arrayidxC = getelementptr inbounds i16, i16* %c, i64 %ind + %loadC = load i16, i16* %arrayidxC, align 2 + + %mul = mul i16 %loadB, %loadA_plus_2 + %mul1 = mul i16 %mul, %loadC + + %arrayidxA = getelementptr inbounds i16, i16* %a, i64 %ind + store i16 %mul1, i16* %arrayidxA, align 2 + + %exitcond = icmp eq i64 %add, 20 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} diff --git a/test/Analysis/LoopAccessAnalysis/store-to-invariant-check1.ll b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check1.ll new file mode 100644 index 0000000..8ab8ab2 --- /dev/null +++ b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check1.ll @@ -0,0 +1,53 @@ +; RUN: opt < %s -loop-accesses -analyze | FileCheck %s + +; Test to confirm LAA will find store to invariant address. +; Inner loop has a store to invariant address. +; +; for(; i < itr; i++) { +; for(; j < itr; j++) { +; var1[i] = var2[j] + var1[i]; +; } +; } + +; CHECK: Store to invariant address was found in loop. +; CHECK-NOT: Store to invariant address was not found in loop. + +define i32 @foo(i32* nocapture %var1, i32* nocapture readonly %var2, i32 %itr) #0 { +entry: + %cmp20 = icmp eq i32 %itr, 0 + br i1 %cmp20, label %for.end10, label %for.cond1.preheader + +for.cond1.preheader: ; preds = %entry, %for.inc8 + %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc8 ], [ 0, %entry ] + %j.022 = phi i32 [ %j.1.lcssa, %for.inc8 ], [ 0, %entry ] + %cmp218 = icmp ult i32 %j.022, %itr + br i1 %cmp218, label %for.body3.lr.ph, label %for.inc8 + +for.body3.lr.ph: ; preds = %for.cond1.preheader + %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv23 + %0 = zext i32 %j.022 to i64 + br label %for.body3 + +for.body3: ; preds = %for.body3, %for.body3.lr.ph + %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ] + %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv + %1 = load i32, i32* %arrayidx, align 4 + %2 = load i32, i32* %arrayidx5, align 4 + %add = add nsw i32 %2, %1 + store i32 %add, i32* %arrayidx5, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %itr + br i1 %exitcond, label %for.inc8, label %for.body3 + +for.inc8: ; preds = %for.body3, %for.cond1.preheader + %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %for.body3 ] + %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1 + %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32 + %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr + br i1 %exitcond26, label %for.end10, label %for.cond1.preheader + +for.end10: ; preds = %for.inc8, %entry + ret i32 undef +} + diff --git a/test/Analysis/LoopAccessAnalysis/store-to-invariant-check2.ll b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check2.ll new file mode 100644 index 0000000..4da0906 --- /dev/null +++ b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check2.ll @@ -0,0 +1,54 @@ +; RUN: opt < %s -loop-accesses -analyze | FileCheck %s + +; Test to confirm LAA will not find store to invariant address. +; Inner loop has no store to invariant address. +; +; for(; i < itr; i++) { +; for(; j < itr; j++) { +; var2[j] = var2[j] + var1[i]; +; } +; } + +; CHECK: Store to invariant address was not found in loop. +; CHECK-NOT: Store to invariant address was found in loop. + + +define i32 @foo(i32* nocapture readonly %var1, i32* nocapture %var2, i32 %itr) #0 { +entry: + %cmp20 = icmp eq i32 %itr, 0 + br i1 %cmp20, label %for.end10, label %for.cond1.preheader + +for.cond1.preheader: ; preds = %entry, %for.inc8 + %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc8 ], [ 0, %entry ] + %j.022 = phi i32 [ %j.1.lcssa, %for.inc8 ], [ 0, %entry ] + %cmp218 = icmp ult i32 %j.022, %itr + br i1 %cmp218, label %for.body3.lr.ph, label %for.inc8 + +for.body3.lr.ph: ; preds = %for.cond1.preheader + %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv23 + %0 = zext i32 %j.022 to i64 + br label %for.body3 + +for.body3: ; preds = %for.body3, %for.body3.lr.ph + %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ] + %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv + %1 = load i32, i32* %arrayidx, align 4 + %2 = load i32, i32* %arrayidx5, align 4 + %add = add nsw i32 %2, %1 + store i32 %add, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %itr + br i1 %exitcond, label %for.inc8, label %for.body3 + +for.inc8: ; preds = %for.body3, %for.cond1.preheader + %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %for.body3 ] + %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1 + %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32 + %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr + br i1 %exitcond26, label %for.end10, label %for.cond1.preheader + +for.end10: ; preds = %for.inc8, %entry + ret i32 undef +} + diff --git a/test/Analysis/LoopAccessAnalysis/store-to-invariant-check3.ll b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check3.ll new file mode 100644 index 0000000..18315a5 --- /dev/null +++ b/test/Analysis/LoopAccessAnalysis/store-to-invariant-check3.ll @@ -0,0 +1,53 @@ +; RUN: opt < %s -loop-accesses -analyze | FileCheck %s + +; Test to confirm LAA will find store to invariant address. +; Inner loop has a store to invariant address. +; +; for(; i < itr; i++) { +; for(; j < itr; j++) { +; var1[j] = ++var2[i] + var1[j]; +; } +; } + +; CHECK: Store to invariant address was found in loop. + +define void @foo(i32* nocapture %var1, i32* nocapture %var2, i32 %itr) #0 { +entry: + %cmp20 = icmp sgt i32 %itr, 0 + br i1 %cmp20, label %for.cond1.preheader, label %for.end11 + +for.cond1.preheader: ; preds = %entry, %for.inc9 + %indvars.iv23 = phi i64 [ %indvars.iv.next24, %for.inc9 ], [ 0, %entry ] + %j.022 = phi i32 [ %j.1.lcssa, %for.inc9 ], [ 0, %entry ] + %cmp218 = icmp slt i32 %j.022, %itr + br i1 %cmp218, label %for.body3.lr.ph, label %for.inc9 + +for.body3.lr.ph: ; preds = %for.cond1.preheader + %arrayidx = getelementptr inbounds i32, i32* %var2, i64 %indvars.iv23 + %0 = sext i32 %j.022 to i64 + br label %for.body3 + +for.body3: ; preds = %for.body3, %for.body3.lr.ph + %indvars.iv = phi i64 [ %0, %for.body3.lr.ph ], [ %indvars.iv.next, %for.body3 ] + %1 = load i32, i32* %arrayidx, align 4 + %inc = add nsw i32 %1, 1 + store i32 %inc, i32* %arrayidx, align 4 + %arrayidx5 = getelementptr inbounds i32, i32* %var1, i64 %indvars.iv + %2 = load i32, i32* %arrayidx5, align 4 + %add = add nsw i32 %inc, %2 + store i32 %add, i32* %arrayidx5, align 4 + %indvars.iv.next = add nsw i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %itr + br i1 %exitcond, label %for.inc9, label %for.body3 + +for.inc9: ; preds = %for.body3, %for.cond1.preheader + %j.1.lcssa = phi i32 [ %j.022, %for.cond1.preheader ], [ %itr, %for.body3 ] + %indvars.iv.next24 = add nuw nsw i64 %indvars.iv23, 1 + %lftr.wideiv25 = trunc i64 %indvars.iv.next24 to i32 + %exitcond26 = icmp eq i32 %lftr.wideiv25, %itr + br i1 %exitcond26, label %for.end11, label %for.cond1.preheader + +for.end11: ; preds = %for.inc9, %entry + ret void +} diff --git a/test/Analysis/LoopAccessAnalysis/unsafe-and-rt-checks.ll b/test/Analysis/LoopAccessAnalysis/unsafe-and-rt-checks.ll index a11fd7f..ce8b86b 100644 --- a/test/Analysis/LoopAccessAnalysis/unsafe-and-rt-checks.ll +++ b/test/Analysis/LoopAccessAnalysis/unsafe-and-rt-checks.ll @@ -20,7 +20,6 @@ target triple = "x86_64-apple-macosx10.10.0" ; CHECK-NEXT: %arrayidxA_plus_2 = getelementptr inbounds i16, i16* %a, i64 %add ; CHECK-NEXT: %arrayidxC = getelementptr inbounds i16, i16* %c, i64 %storemerge3 -@n = global i32 20, align 4 @B = common global i16* null, align 8 @A = common global i16* null, align 8 @C = common global i16* null, align 8 diff --git a/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll b/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll index 46c6c59..84561c5 100644 --- a/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll +++ b/test/Analysis/ScalarEvolution/2008-11-18-LessThanOrEqual.ll @@ -13,7 +13,7 @@ bb.nph: ; preds = %entry bb: ; preds = %bb.nph, %bb1 %indvar = phi i32 [ 0, %bb.nph ], [ %indvar.next, %bb1 ] ; [#uses=2] %argc_addr.04 = add i32 %indvar, %argc ; [#uses=1] - tail call void (...)* @Test() nounwind + tail call void (...) @Test() nounwind %1 = add i32 %argc_addr.04, 1 ; [#uses=1] br label %bb1 diff --git a/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll b/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll index c4a4c30..33fcbab 100644 --- a/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll +++ b/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll @@ -14,7 +14,7 @@ entry: br label %lbl_818 lbl_818: ; preds = %for.end, %entry - call void (...)* @func_27() + call void (...) @func_27() store i32 0, i32* @g_814, align 4 br label %for.cond diff --git a/test/Analysis/ScalarEvolution/latch-dominating-conditions.ll b/test/Analysis/ScalarEvolution/latch-dominating-conditions.ll new file mode 100644 index 0000000..3f6f958 --- /dev/null +++ b/test/Analysis/ScalarEvolution/latch-dominating-conditions.ll @@ -0,0 +1,55 @@ +; RUN: opt -S -indvars < %s | FileCheck %s + +declare void @side_effect(i1) + +define void @latch_dominating_0(i8 %start) { +; CHECK-LABEL: latch_dominating_0 + entry: + %e = icmp slt i8 %start, 42 + br i1 %e, label %loop, label %exit + + loop: +; CHECK-LABEL: loop + %idx = phi i8 [ %start, %entry ], [ %idx.inc, %be ] + %idx.inc = add i8 %idx, 1 + %folds.to.true = icmp slt i8 %idx, 42 +; CHECK: call void @side_effect(i1 true) + call void @side_effect(i1 %folds.to.true) + %c0 = icmp slt i8 %idx.inc, 42 + br i1 %c0, label %be, label %exit + + be: +; CHECK: call void @side_effect(i1 true) + call void @side_effect(i1 %folds.to.true) + %c1 = icmp slt i8 %idx.inc, 100 + br i1 %c1, label %loop, label %exit + + exit: + ret void +} + +define void @latch_dominating_1(i8 %start) { +; CHECK-LABEL: latch_dominating_1 + entry: + %e = icmp slt i8 %start, 42 + br i1 %e, label %loop, label %exit + + loop: +; CHECK-LABEL: loop + %idx = phi i8 [ %start, %entry ], [ %idx.inc, %be ] + %idx.inc = add i8 %idx, 1 + %does.not.fold.to.true = icmp slt i8 %idx, 42 +; CHECK: call void @side_effect(i1 %does.not.fold.to.true) + call void @side_effect(i1 %does.not.fold.to.true) + %c0 = icmp slt i8 %idx.inc, 42 + br i1 %c0, label %be, label %be + + be: +; CHECK: call void @side_effect(i1 %does.not.fold.to.true) + call void @side_effect(i1 %does.not.fold.to.true) + %c1 = icmp slt i8 %idx.inc, 100 + br i1 %c1, label %loop, label %exit + + exit: + ret void +} diff --git a/test/Analysis/ScalarEvolution/max-trip-count.ll b/test/Analysis/ScalarEvolution/max-trip-count.ll index 72560c7..614e9b2 100644 --- a/test/Analysis/ScalarEvolution/max-trip-count.ll +++ b/test/Analysis/ScalarEvolution/max-trip-count.ll @@ -65,7 +65,7 @@ for.inc: ; preds = %for.body br label %for.cond for.end: ; preds = %for.body, %for.cond - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %g_4.0) nounwind ; [#uses=0] + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %g_4.0) nounwind ; [#uses=0] ret i32 0 } diff --git a/test/Analysis/ScalarEvolution/zext-signed-addrec.ll b/test/Analysis/ScalarEvolution/zext-signed-addrec.ll index 31ebb3e..2b12b33 100644 --- a/test/Analysis/ScalarEvolution/zext-signed-addrec.ll +++ b/test/Analysis/ScalarEvolution/zext-signed-addrec.ll @@ -63,7 +63,7 @@ for.cond.for.end9_crit_edge: ; preds = %for.inc8 for.end9: ; preds = %entry.for.end9_crit_edge, %for.cond.for.end9_crit_edge %3 = phi i32 [ %.pre, %entry.for.end9_crit_edge ], [ %shl, %for.cond.for.end9_crit_edge ] - %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %3) #2 + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i64 0, i64 0), i32 %3) #2 br label %return return.loopexit.split: ; preds = %for.cond1.preheader.lr.ph diff --git a/test/Analysis/ValueTracking/memory-dereferenceable.ll b/test/Analysis/ValueTracking/memory-dereferenceable.ll index 51f9265..bfee5c7 100644 --- a/test/Analysis/ValueTracking/memory-dereferenceable.ll +++ b/test/Analysis/ValueTracking/memory-dereferenceable.ll @@ -9,7 +9,7 @@ declare zeroext i1 @return_i1() @globalstr = global [6 x i8] c"hello\00" -define void @test(i32 addrspace(1)* dereferenceable(8) %dparam) { +define void @test(i32 addrspace(1)* dereferenceable(8) %dparam) gc "statepoint-example" { ; CHECK: The following are dereferenceable: ; CHECK: %globalptr ; CHECK: %alloca @@ -22,7 +22,7 @@ entry: %alloca = alloca i1 %load2 = load i1, i1* %alloca %load3 = load i32, i32 addrspace(1)* %dparam - %tok = tail call i32 (i1 ()*, i32, i32, ...)* @llvm.experimental.gc.statepoint.p0f_i1f(i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 addrspace(1)* %dparam) + %tok = tail call i32 (i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 addrspace(1)* %dparam) %relocate = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(i32 %tok, i32 4, i32 4) %load4 = load i32, i32 addrspace(1)* %relocate %nparam = getelementptr i32, i32 addrspace(1)* %dparam, i32 5 diff --git a/test/Assembler/2002-07-25-ReturnPtrFunction.ll b/test/Assembler/2002-07-25-ReturnPtrFunction.ll index fdee93c..0fb9d55 100644 --- a/test/Assembler/2002-07-25-ReturnPtrFunction.ll +++ b/test/Assembler/2002-07-25-ReturnPtrFunction.ll @@ -7,7 +7,7 @@ declare void (i32)* @foo() define void @test() { - call void (i32)* ()* @foo( ) ; <%ty*>:1 [#uses=0] + call void (i32)* () @foo( ) ; <%ty*>:1 [#uses=0] ret void } diff --git a/test/Assembler/2003-05-15-AssemblerProblem.ll b/test/Assembler/2003-05-15-AssemblerProblem.ll index eba26a2..70c9617 100644 --- a/test/Assembler/2003-05-15-AssemblerProblem.ll +++ b/test/Assembler/2003-05-15-AssemblerProblem.ll @@ -4,12 +4,12 @@ ; RUN: verify-uselistorder %s define void @test() { - call void (...)* bitcast (void (i16*, i32)* @AddString to void (...)*)( i16* null, i32 0 ) + call void (...) bitcast (void (i16*, i32)* @AddString to void (...)*)( i16* null, i32 0 ) ret void } define void @AddString(i16* %tmp.124, i32 %tmp.127) { - call void (...)* bitcast (void (i16*, i32)* @AddString to void (...)*)( i16* %tmp.124, i32 %tmp.127 ) + call void (...) bitcast (void (i16*, i32)* @AddString to void (...)*)( i16* %tmp.124, i32 %tmp.127 ) ret void } diff --git a/test/Assembler/2008-01-11-VarargAttrs.ll b/test/Assembler/2008-01-11-VarargAttrs.ll index 0b6592c..3111f2d 100644 --- a/test/Assembler/2008-01-11-VarargAttrs.ll +++ b/test/Assembler/2008-01-11-VarargAttrs.ll @@ -6,6 +6,6 @@ declare void @foo(...) define void @bar() { - call void (...)* @foo(%struct* byval null ) + call void (...) @foo(%struct* byval null ) ret void } diff --git a/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll b/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll index 2dd4743..24d1713 100644 --- a/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll +++ b/test/Assembler/2010-02-05-FunctionLocalMetadataBecomesNull.ll @@ -13,7 +13,7 @@ target triple = "x86_64-apple-darwin10.2" define i32 @main() nounwind readonly { %diff1 = alloca i64 ; [#uses=2] ; CHECK: call void @llvm.dbg.value(metadata i64 72, - call void @llvm.dbg.declare(metadata i64* %diff1, metadata !0, metadata !MDExpression()) + call void @llvm.dbg.declare(metadata i64* %diff1, metadata !0, metadata !MDExpression()), !dbg !MDLocation(scope: !1) store i64 72, i64* %diff1, align 8 %v1 = load %struct.test*, %struct.test** @TestArrayPtr, align 8 ; <%struct.test*> [#uses=1] %v2 = ptrtoint %struct.test* %v1 to i64 ; [#uses=1] diff --git a/test/Assembler/debug-info.ll b/test/Assembler/debug-info.ll index 7103ed2..417c479 100644 --- a/test/Assembler/debug-info.ll +++ b/test/Assembler/debug-info.ll @@ -28,11 +28,11 @@ !9 = !MDBasicType() !10 = !MDBasicType(tag: DW_TAG_base_type, name: "", size: 0, align: 0, encoding: 0) -; CHECK-NEXT: !9 = distinct !{} +; CHECK-NEXT: !9 = !MDTemplateTypeParameter(type: !6) ; CHECK-NEXT: !10 = !MDFile(filename: "path/to/file", directory: "/path/to/dir") ; CHECK-NEXT: !11 = distinct !{} ; CHECK-NEXT: !12 = !MDFile(filename: "", directory: "") -!11 = distinct !{} +!11 = !MDTemplateTypeParameter(type: !7) !12 = !MDFile(filename: "path/to/file", directory: "/path/to/dir") !13 = distinct !{} !14 = !MDFile(filename: "", directory: "") @@ -44,7 +44,7 @@ ; CHECK-NEXT: !15 = distinct !MDCompositeType(tag: DW_TAG_structure_type, name: "Base", scope: !14, file: !10, line: 3, size: 128, align: 32, offset: 64, flags: DIFlagPublic, elements: !16, runtimeLang: DW_LANG_C_plus_plus_11, vtableHolder: !15, templateParams: !18, identifier: "MangledBase") ; CHECK-NEXT: !16 = !{!17} ; CHECK-NEXT: !17 = !MDDerivedType(tag: DW_TAG_member, name: "field", scope: !15, file: !10, line: 4, baseType: !6, size: 32, align: 32, offset: 32, flags: DIFlagPublic) -; CHECK-NEXT: !18 = !{!6} +; CHECK-NEXT: !18 = !{!9} ; CHECK-NEXT: !19 = !MDCompositeType(tag: DW_TAG_structure_type, name: "Derived", scope: !14, file: !10, line: 3, baseType: !15, size: 128, align: 32, offset: 64, flags: DIFlagPublic, elements: !20, runtimeLang: DW_LANG_C_plus_plus_11, vtableHolder: !15, templateParams: !18, identifier: "MangledBase") ; CHECK-NEXT: !20 = !{!21} ; CHECK-NEXT: !21 = !MDDerivedType(tag: DW_TAG_inheritance, scope: !19, baseType: !15) @@ -55,7 +55,7 @@ !17 = !MDCompositeType(tag: DW_TAG_structure_type, name: "Base", scope: !16, file: !12, line: 3, size: 128, align: 32, offset: 64, flags: DIFlagPublic, elements: !18, runtimeLang: DW_LANG_C_plus_plus_11, vtableHolder: !17, templateParams: !20, identifier: "MangledBase") !18 = !{!19} !19 = !MDDerivedType(tag: DW_TAG_member, name: "field", scope: !17, file: !12, line: 4, baseType: !7, size: 32, align: 32, offset: 32, flags: DIFlagPublic) -!20 = !{!7} +!20 = !{!11} !21 = !MDCompositeType(tag: DW_TAG_structure_type, name: "Derived", scope: !16, file: !12, line: 3, baseType: !17, size: 128, align: 32, offset: 64, flags: DIFlagPublic, elements: !22, runtimeLang: DW_LANG_C_plus_plus_11, vtableHolder: !17, templateParams: !20, identifier: "MangledBase") !22 = !{!23} !23 = !MDDerivedType(tag: DW_TAG_inheritance, scope: !21, baseType: !17) diff --git a/test/Assembler/invalid-mdcompileunit-null-file.ll b/test/Assembler/invalid-mdcompileunit-null-file.ll new file mode 100644 index 0000000..613948f --- /dev/null +++ b/test/Assembler/invalid-mdcompileunit-null-file.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:27: error: 'file' cannot be null +!0 = !MDCompileUnit(file: null) diff --git a/test/Assembler/invalid-mdglobalvariable-empty-name.ll b/test/Assembler/invalid-mdglobalvariable-empty-name.ll new file mode 100644 index 0000000..77a9f4d --- /dev/null +++ b/test/Assembler/invalid-mdglobalvariable-empty-name.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:30: error: 'name' cannot be empty +!0 = !MDGlobalVariable(name: "") diff --git a/test/Assembler/invalid-mdglobalvariable-missing-name.ll b/test/Assembler/invalid-mdglobalvariable-missing-name.ll new file mode 100644 index 0000000..d57d71e --- /dev/null +++ b/test/Assembler/invalid-mdglobalvariable-missing-name.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:24: error: missing required field 'name' +!0 = !MDGlobalVariable() diff --git a/test/Assembler/invalid-mdimportedentity-missing-parent.ll b/test/Assembler/invalid-mdimportedentity-missing-parent.ll deleted file mode 100644 index 710a027..0000000 --- a/test/Assembler/invalid-mdimportedentity-missing-parent.ll +++ /dev/null @@ -1,4 +0,0 @@ -; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s - -; CHECK: [[@LINE+1]]:51: error: missing required field 'scope' -!3 = !MDImportedEntity(tag: DW_TAG_imported_module) diff --git a/test/Assembler/invalid-mdimportedentity-missing-scope.ll b/test/Assembler/invalid-mdimportedentity-missing-scope.ll new file mode 100644 index 0000000..710a027 --- /dev/null +++ b/test/Assembler/invalid-mdimportedentity-missing-scope.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: [[@LINE+1]]:51: error: missing required field 'scope' +!3 = !MDImportedEntity(tag: DW_TAG_imported_module) diff --git a/test/Assembler/invalid-mdlexicalblock-missing-parent.ll b/test/Assembler/invalid-mdlexicalblock-missing-parent.ll deleted file mode 100644 index cdd12af..0000000 --- a/test/Assembler/invalid-mdlexicalblock-missing-parent.ll +++ /dev/null @@ -1,4 +0,0 @@ -; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s - -; CHECK: [[@LINE+1]]:29: error: missing required field 'scope' -!0 = !MDLexicalBlock(line: 7) diff --git a/test/Assembler/invalid-mdlexicalblock-missing-scope.ll b/test/Assembler/invalid-mdlexicalblock-missing-scope.ll new file mode 100644 index 0000000..cdd12af --- /dev/null +++ b/test/Assembler/invalid-mdlexicalblock-missing-scope.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: [[@LINE+1]]:29: error: missing required field 'scope' +!0 = !MDLexicalBlock(line: 7) diff --git a/test/Assembler/invalid-mdlexicalblock-null-scope.ll b/test/Assembler/invalid-mdlexicalblock-null-scope.ll new file mode 100644 index 0000000..59a9968 --- /dev/null +++ b/test/Assembler/invalid-mdlexicalblock-null-scope.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:29: error: 'scope' cannot be null +!0 = !MDLexicalBlock(scope: null) diff --git a/test/Assembler/invalid-mdlexicalblockfile-missing-parent.ll b/test/Assembler/invalid-mdlexicalblockfile-missing-parent.ll deleted file mode 100644 index 1c901e2..0000000 --- a/test/Assembler/invalid-mdlexicalblockfile-missing-parent.ll +++ /dev/null @@ -1,4 +0,0 @@ -; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s - -; CHECK: [[@LINE+1]]:42: error: missing required field 'scope' -!0 = !MDLexicalBlockFile(discriminator: 0) diff --git a/test/Assembler/invalid-mdlexicalblockfile-missing-scope.ll b/test/Assembler/invalid-mdlexicalblockfile-missing-scope.ll new file mode 100644 index 0000000..1c901e2 --- /dev/null +++ b/test/Assembler/invalid-mdlexicalblockfile-missing-scope.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: [[@LINE+1]]:42: error: missing required field 'scope' +!0 = !MDLexicalBlockFile(discriminator: 0) diff --git a/test/Assembler/invalid-mdlexicalblockfile-null-scope.ll b/test/Assembler/invalid-mdlexicalblockfile-null-scope.ll new file mode 100644 index 0000000..708136c --- /dev/null +++ b/test/Assembler/invalid-mdlexicalblockfile-null-scope.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:33: error: 'scope' cannot be null +!0 = !MDLexicalBlockFile(scope: null) diff --git a/test/Assembler/invalid-mdlocalvariable-missing-name.ll b/test/Assembler/invalid-mdlocalvariable-missing-name.ll deleted file mode 100644 index 5b23600..0000000 --- a/test/Assembler/invalid-mdlocalvariable-missing-name.ll +++ /dev/null @@ -1,4 +0,0 @@ -; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s - -; CHECK: :[[@LINE+1]]:29: error: missing required field 'tag' -!0 = !MDLocalVariable(arg: 7) diff --git a/test/Assembler/invalid-mdlocalvariable-missing-scope.ll b/test/Assembler/invalid-mdlocalvariable-missing-scope.ll new file mode 100644 index 0000000..d8ee8a9 --- /dev/null +++ b/test/Assembler/invalid-mdlocalvariable-missing-scope.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:48: error: missing required field 'scope' +!0 = !MDLocalVariable(tag: DW_TAG_auto_variable) diff --git a/test/Assembler/invalid-mdlocalvariable-missing-tag.ll b/test/Assembler/invalid-mdlocalvariable-missing-tag.ll new file mode 100644 index 0000000..d3ca10a --- /dev/null +++ b/test/Assembler/invalid-mdlocalvariable-missing-tag.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:45: error: missing required field 'tag' +!0 = !MDLocalVariable(scope: !MDSubprogram()) diff --git a/test/Assembler/invalid-mdlocalvariable-null-scope.ll b/test/Assembler/invalid-mdlocalvariable-null-scope.ll new file mode 100644 index 0000000..53ee94d --- /dev/null +++ b/test/Assembler/invalid-mdlocalvariable-null-scope.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:30: error: 'scope' cannot be null +!0 = !MDLocalVariable(scope: null) diff --git a/test/Assembler/invalid-mdlocation-null-scope.ll b/test/Assembler/invalid-mdlocation-null-scope.ll new file mode 100644 index 0000000..e359c9f --- /dev/null +++ b/test/Assembler/invalid-mdlocation-null-scope.ll @@ -0,0 +1,4 @@ +; RUN: not llvm-as < %s -disable-output 2>&1 | FileCheck %s + +; CHECK: :[[@LINE+1]]:25: error: 'scope' cannot be null +!0 = !MDLocation(scope: null) diff --git a/test/Assembler/mdglobalvariable.ll b/test/Assembler/mdglobalvariable.ll index 09d20bf..2726f4f 100644 --- a/test/Assembler/mdglobalvariable.ll +++ b/test/Assembler/mdglobalvariable.ll @@ -3,20 +3,25 @@ @foo = global i32 0 -; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6} -!named = !{!0, !1, !2, !3, !4, !5, !6} +; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9} +!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9} -!0 = distinct !{} +!0 = !MDFile(filename: "scope.h", directory: "/path/to/dir") !1 = distinct !{} !2 = !MDFile(filename: "path/to/file", directory: "/path/to/dir") -!3 = distinct !{} +!3 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !4 = distinct !{} -; CHECK: !5 = !MDGlobalVariable(name: "foo", linkageName: "foo", scope: !0, file: !2, line: 7, type: !3, isLocal: true, isDefinition: false, variable: i32* @foo, declaration: !4) +; CHECK: !5 = !MDGlobalVariable(name: "foo", linkageName: "foo", scope: !0, file: !2, line: 7, type: !3, isLocal: true, isDefinition: false, variable: i32* @foo) !5 = !MDGlobalVariable(name: "foo", linkageName: "foo", scope: !0, file: !2, line: 7, type: !3, isLocal: true, - isDefinition: false, variable: i32* @foo, - declaration: !4) + isDefinition: false, variable: i32* @foo) -; CHECK: !6 = !MDGlobalVariable(scope: null, isLocal: false, isDefinition: true) -!6 = !MDGlobalVariable() +; CHECK: !6 = !MDGlobalVariable(name: "foo", scope: !0, isLocal: false, isDefinition: true) +!6 = !MDGlobalVariable(name: "foo", scope: !0) + +!7 = !MDCompositeType(tag: DW_TAG_structure_type, name: "Class", size: 8, align: 8) +!8 = !MDDerivedType(tag: DW_TAG_member, name: "mem", flags: DIFlagStaticMember, scope: !7, baseType: !3) + +; CHECK: !9 = !MDGlobalVariable(name: "mem", scope: !0, isLocal: false, isDefinition: true, declaration: !8) +!9 = !MDGlobalVariable(name: "mem", scope: !0, declaration: !8) diff --git a/test/Assembler/mdimportedentity.ll b/test/Assembler/mdimportedentity.ll index 0584edb..8e98c5d 100644 --- a/test/Assembler/mdimportedentity.ll +++ b/test/Assembler/mdimportedentity.ll @@ -4,10 +4,10 @@ ; CHECK: !named = !{!0, !1, !2, !3, !3} !named = !{!0, !1, !2, !3, !4} -; CHECK: !0 = distinct !{} -; CHECK-NEXT: !1 = distinct !{} -!0 = distinct !{} -!1 = distinct !{} +; CHECK: !0 = !MDSubprogram({{.*}}) +; CHECK-NEXT: !1 = !MDCompositeType({{.*}}) +!0 = !MDSubprogram(name: "foo") +!1 = !MDCompositeType(tag: DW_TAG_structure_type, name: "Class", size: 32, align: 32) ; CHECK-NEXT: !2 = !MDImportedEntity(tag: DW_TAG_imported_module, name: "foo", scope: !0, entity: !1, line: 7) !2 = !MDImportedEntity(tag: DW_TAG_imported_module, name: "foo", scope: !0, diff --git a/test/Assembler/mdlexicalblock.ll b/test/Assembler/mdlexicalblock.ll index 0a2c339..d88eae7 100644 --- a/test/Assembler/mdlexicalblock.ll +++ b/test/Assembler/mdlexicalblock.ll @@ -5,15 +5,15 @@ !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9} !0 = distinct !{} -!1 = distinct !{} +!1 = !MDSubprogram(name: "foo", scope: !2) !2 = !MDFile(filename: "path/to/file", directory: "/path/to/dir") -; CHECK: !3 = !MDLexicalBlock(scope: !0, file: !2, line: 7, column: 35) -!3 = !MDLexicalBlock(scope: !0, file: !2, line: 7, column: 35) +; CHECK: !3 = !MDLexicalBlock(scope: !1, file: !2, line: 7, column: 35) +!3 = !MDLexicalBlock(scope: !1, file: !2, line: 7, column: 35) -; CHECK: !4 = !MDLexicalBlock(scope: !0) -!4 = !MDLexicalBlock(scope: !0) -!5 = !MDLexicalBlock(scope: !0, file: null, line: 0, column: 0) +; CHECK: !4 = !MDLexicalBlock(scope: !1) +!4 = !MDLexicalBlock(scope: !1) +!5 = !MDLexicalBlock(scope: !1, file: null, line: 0, column: 0) ; CHECK: !5 = !MDLexicalBlockFile(scope: !3, file: !2, discriminator: 0) ; CHECK: !6 = !MDLexicalBlockFile(scope: !3, file: !2, discriminator: 1) diff --git a/test/Assembler/mdlocalvariable.ll b/test/Assembler/mdlocalvariable.ll index 3a36c7d..2c0b35a 100644 --- a/test/Assembler/mdlocalvariable.ll +++ b/test/Assembler/mdlocalvariable.ll @@ -6,21 +6,21 @@ ; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8} !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8} -!0 = distinct !{} +!0 = distinct !MDSubprogram() !1 = distinct !{} !2 = !MDFile(filename: "path/to/file", directory: "/path/to/dir") -!3 = distinct !{} -!4 = distinct !{} +!3 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!4 = !MDLocation(scope: !0) -; CHECK: !5 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "foo", arg: 3, scope: !0, file: !2, line: 7, type: !3, flags: DIFlagArtificial, inlinedAt: !4) -; CHECK: !6 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "foo", scope: !0, file: !2, line: 7, type: !3, flags: DIFlagArtificial, inlinedAt: !4) +; CHECK: !5 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "foo", arg: 3, scope: !0, file: !2, line: 7, type: !3, flags: DIFlagArtificial) +; CHECK: !6 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "foo", scope: !0, file: !2, line: 7, type: !3, flags: DIFlagArtificial) !5 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "foo", arg: 3, scope: !0, file: !2, line: 7, type: !3, - flags: DIFlagArtificial, inlinedAt: !4) + flags: DIFlagArtificial) !6 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "foo", scope: !0, - file: !2, line: 7, type: !3, flags: DIFlagArtificial, inlinedAt: !4) + file: !2, line: 7, type: !3, flags: DIFlagArtificial) -; CHECK: !7 = !MDLocalVariable(tag: DW_TAG_arg_variable, arg: 0, scope: null) -; CHECK: !8 = !MDLocalVariable(tag: DW_TAG_auto_variable, scope: null) -!7 = !MDLocalVariable(tag: DW_TAG_arg_variable) -!8 = !MDLocalVariable(tag: DW_TAG_auto_variable) +; CHECK: !7 = !MDLocalVariable(tag: DW_TAG_arg_variable, arg: 0, scope: !0) +; CHECK: !8 = !MDLocalVariable(tag: DW_TAG_auto_variable, scope: !0) +!7 = !MDLocalVariable(tag: DW_TAG_arg_variable, scope: !0) +!8 = !MDLocalVariable(tag: DW_TAG_auto_variable, scope: !0) diff --git a/test/Assembler/mdnamespace.ll b/test/Assembler/mdnamespace.ll index 90cb15f..e708a3c 100644 --- a/test/Assembler/mdnamespace.ll +++ b/test/Assembler/mdnamespace.ll @@ -4,7 +4,7 @@ ; CHECK: !named = !{!0, !1, !2, !3, !4, !4} !named = !{!0, !1, !2, !3, !4, !5} -!0 = distinct !{} +!0 = !MDFile(filename: "file.cpp", directory: "/path/to/dir") !1 = distinct !{} !2 = !MDFile(filename: "path/to/file", directory: "/path/to/dir") diff --git a/test/Assembler/mdobjcproperty.ll b/test/Assembler/mdobjcproperty.ll index cb2f4d3..a3b20e5 100644 --- a/test/Assembler/mdobjcproperty.ll +++ b/test/Assembler/mdobjcproperty.ll @@ -6,10 +6,9 @@ !0 = distinct !{} !1 = !MDFile(filename: "path/to/file", directory: "/path/to/dir") -!2 = distinct !{} +!2 = !MDCompositeType(tag: DW_TAG_structure_type, name: "Object") - -; CHECK: !2 = distinct !{} +; CHECK: !2 = !MDCompositeType({{.*}}) ; CHECK-NEXT: !3 = !MDObjCProperty(name: "foo", file: !1, line: 7, setter: "setFoo", getter: "getFoo", attributes: 7, type: !2) !3 = !MDObjCProperty(name: "foo", file: !1, line: 7, setter: "setFoo", getter: "getFoo", attributes: 7, type: !2) diff --git a/test/Assembler/mdsubprogram.ll b/test/Assembler/mdsubprogram.ll index 7447166..9300089 100644 --- a/test/Assembler/mdsubprogram.ll +++ b/test/Assembler/mdsubprogram.ll @@ -6,17 +6,17 @@ declare void @_Z3foov() ; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9} !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8, !9} -!0 = distinct !{} -!1 = distinct !{} +!0 = !{null} +!1 = distinct !MDCompositeType(tag: DW_TAG_structure_type) !2 = !MDFile(filename: "path/to/file", directory: "/path/to/dir") -!3 = distinct !{} -!4 = distinct !{} +!3 = !MDSubroutineType(types: !0) +!4 = distinct !MDCompositeType(tag: DW_TAG_structure_type) !5 = distinct !{} -!6 = distinct !{} +!6 = distinct !MDSubprogram(isDefinition: false) !7 = distinct !{} -; CHECK: !8 = !MDSubprogram(name: "foo", linkageName: "_Zfoov", scope: !0, file: !2, line: 7, type: !3, isLocal: true, isDefinition: false, scopeLine: 8, containingType: !4, virtuality: DW_VIRTUALITY_pure_virtual, virtualIndex: 10, flags: DIFlagPrototyped, isOptimized: true, function: void ()* @_Z3foov, templateParams: !5, declaration: !6, variables: !7) -!8 = !MDSubprogram(name: "foo", linkageName: "_Zfoov", scope: !0, +; CHECK: !8 = !MDSubprogram(name: "foo", linkageName: "_Zfoov", scope: !1, file: !2, line: 7, type: !3, isLocal: true, isDefinition: false, scopeLine: 8, containingType: !4, virtuality: DW_VIRTUALITY_pure_virtual, virtualIndex: 10, flags: DIFlagPrototyped, isOptimized: true, function: void ()* @_Z3foov, templateParams: !5, declaration: !6, variables: !7) +!8 = !MDSubprogram(name: "foo", linkageName: "_Zfoov", scope: !1, file: !2, line: 7, type: !3, isLocal: true, isDefinition: false, scopeLine: 8, containingType: !4, virtuality: DW_VIRTUALITY_pure_virtual, virtualIndex: 10, diff --git a/test/Assembler/mdsubroutinetype.ll b/test/Assembler/mdsubroutinetype.ll new file mode 100644 index 0000000..936cbf4 --- /dev/null +++ b/test/Assembler/mdsubroutinetype.ll @@ -0,0 +1,23 @@ +; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s +; RUN: verify-uselistorder %s + +; CHECK: !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8} +!named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8} + +!0 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!1 = !{null} +!2 = !{null, !0} +!3 = !{!0, !0, !0} + + +; CHECK: !4 = !MDSubroutineType(types: !1) +; CHECK: !5 = !MDSubroutineType(types: !2) +; CHECK: !6 = !MDSubroutineType(types: !3) +; CHECK: !7 = !MDSubroutineType(flags: DIFlagLValueReference, types: !3) +!4 = !MDSubroutineType(types: !1) +!5 = !MDSubroutineType(types: !2) +!6 = !MDSubroutineType(types: !3) +!7 = !MDSubroutineType(flags: DIFlagLValueReference, types: !3) + +; CHECK: !8 = !MDSubroutineType(types: null) +!8 = !MDSubroutineType(types: null) diff --git a/test/Assembler/mdtemplateparameter.ll b/test/Assembler/mdtemplateparameter.ll index 22ee5c8..5bcef3f 100644 --- a/test/Assembler/mdtemplateparameter.ll +++ b/test/Assembler/mdtemplateparameter.ll @@ -5,8 +5,8 @@ !named = !{!0, !1, !2, !3, !4, !5, !6, !7, !8} !0 = distinct !{} -!1 = distinct !{} -; CHECK: !1 = distinct !{} +!1 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +; CHECK: !1 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) ; CHECK-NEXT: !2 = !MDTemplateTypeParameter(name: "Ty", type: !1) ; CHECK-NEXT: !3 = !MDTemplateTypeParameter(type: !1) diff --git a/test/Assembler/metadata-null-operands.ll b/test/Assembler/metadata-null-operands.ll index acae1d4..7e27eba 100644 --- a/test/Assembler/metadata-null-operands.ll +++ b/test/Assembler/metadata-null-operands.ll @@ -1,13 +1,11 @@ ; RUN: llvm-as < %s | llvm-dis | llvm-as | llvm-dis | FileCheck %s ; RUN: verify-uselistorder %s -; Don't crash on null operands. (If/when we add a verify check for these, we -; should disable the verifier for this test and remove this comment; the test -; is still important.) -!named = !{!0, !1} +; Don't crash on null operands. When we add a verify check for this, also +; require non-null in the assembler and rework this test to check for that ala +; test/Assembler/invalid-mdcompileunit-null-file.ll. +!named = !{!0} !0 = !MDDerivedType(tag: DW_TAG_pointer_type, baseType: null) -!1 = !MDCompileUnit(language: DW_LANG_C, file: null) -; CHECK: !named = !{!0, !1} +; CHECK: !named = !{!0} ; CHECK: !0 = !MDDerivedType({{.*}}baseType: null{{.*}}) -; CHECK: !1 = !MDCompileUnit({{.*}}file: null{{.*}}) diff --git a/test/Assembler/musttail-invalid-1.ll b/test/Assembler/musttail-invalid-1.ll index b123a91..e9141c8 100644 --- a/test/Assembler/musttail-invalid-1.ll +++ b/test/Assembler/musttail-invalid-1.ll @@ -8,7 +8,7 @@ declare i8* @f(i8*, ...) define i8* @f_thunk(i8* %this) { - %rv = musttail call i8* (i8*, ...)* @f(i8* %this, ...) + %rv = musttail call i8* (i8*, ...) @f(i8* %this, ...) ; CHECK: error: unexpected ellipsis in argument list for musttail call in non-varargs function ret i8* %rv } diff --git a/test/Assembler/musttail-invalid-2.ll b/test/Assembler/musttail-invalid-2.ll index 3bcb51f..8602afd 100644 --- a/test/Assembler/musttail-invalid-2.ll +++ b/test/Assembler/musttail-invalid-2.ll @@ -7,7 +7,7 @@ declare i8* @f(i8*, ...) define i8* @f_thunk(i8* %this, ...) { - %rv = musttail call i8* (i8*, ...)* @f(i8* %this) + %rv = musttail call i8* (i8*, ...) @f(i8* %this) ; CHECK: error: expected '...' at end of argument list for musttail call in varargs function ret i8* %rv } diff --git a/test/Assembler/musttail.ll b/test/Assembler/musttail.ll index 6e2a9b2..ac60ba2 100644 --- a/test/Assembler/musttail.ll +++ b/test/Assembler/musttail.ll @@ -7,8 +7,8 @@ declare i8* @f(i8*, ...) define i8* @f_thunk(i8* %this, ...) { - %rv = musttail call i8* (i8*, ...)* @f(i8* %this, ...) + %rv = musttail call i8* (i8*, ...) @f(i8* %this, ...) ret i8* %rv } ; CHECK-LABEL: define i8* @f_thunk(i8* %this, ...) -; CHECK: %rv = musttail call i8* (i8*, ...)* @f(i8* %this, ...) +; CHECK: %rv = musttail call i8* (i8*, ...) @f(i8* %this, ...) diff --git a/test/Bitcode/Inputs/invalid-no-proper-module.bc b/test/Bitcode/Inputs/invalid-no-proper-module.bc new file mode 100644 index 0000000..6d5a291 Binary files /dev/null and b/test/Bitcode/Inputs/invalid-no-proper-module.bc differ diff --git a/test/Bitcode/attributes.ll b/test/Bitcode/attributes.ll index c75ee80..9fbdfeb 100644 --- a/test/Bitcode/attributes.ll +++ b/test/Bitcode/attributes.ll @@ -245,6 +245,12 @@ define void @f41(i8* align 32, double* align 64) { ret void } +; CHECK: define dereferenceable_or_null(8) i8* @f42(i8* dereferenceable_or_null(8) %foo) +define dereferenceable_or_null(8) i8* @f42(i8* dereferenceable_or_null(8) %foo) { + entry: + ret i8* %foo +} + ; CHECK: attributes #0 = { noreturn } ; CHECK: attributes #1 = { nounwind } ; CHECK: attributes #2 = { readnone } diff --git a/test/Bitcode/invalid.test b/test/Bitcode/invalid.test index 0eacb9d..9cab227 100644 --- a/test/Bitcode/invalid.test +++ b/test/Bitcode/invalid.test @@ -50,3 +50,8 @@ EXTRACT-IDXS: EXTRACTVAL: Invalid type INSERT-ARRAY: INSERTVAL: Invalid array index INSERT-STRUCT: INSERTVAL: Invalid struct index INSERT-IDXS: INSERTVAL: Invalid type + +RUN: not llvm-dis -disable-output %p/Inputs/invalid-no-proper-module.bc 2>&1 | \ +RUN: FileCheck --check-prefix=NO-MODULE %s + +NO-MODULE: Malformed IR file diff --git a/test/Bitcode/miscInstructions.3.2.ll b/test/Bitcode/miscInstructions.3.2.ll index 6a077d5..bed26c2 100644 --- a/test/Bitcode/miscInstructions.3.2.ll +++ b/test/Bitcode/miscInstructions.3.2.ll @@ -173,8 +173,8 @@ entry: ; CHECK-NEXT: %res2 = tail call i32 @test(i32 %x) %res2 = tail call i32 @test(i32 %x) -; CHECK-NEXT: %res3 = call i32 (i8*, ...)* @printf(i8* %msg, i32 12, i8 42) - %res3 = call i32 (i8*, ...)* @printf(i8* %msg, i32 12, i8 42) +; CHECK-NEXT: %res3 = call i32 (i8*, ...) @printf(i8* %msg, i32 12, i8 42) + %res3 = call i32 (i8*, ...) @printf(i8* %msg, i32 12, i8 42) ret void } diff --git a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll new file mode 100644 index 0000000..a31c66b --- /dev/null +++ b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll @@ -0,0 +1,491 @@ +; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +; This test aims to check basic correctness of frame layout & +; frame access code. There are 8 functions in this test file, +; each function implements one element in the cartesian product +; of: +; . a function having a VLA/noVLA +; . a function with dynamic stack realignment/no dynamic stack realignment. +; . a function needing a frame pionter/no frame pointer, +; since the presence/absence of these has influence on the frame +; layout and which pointer to use to access various part of the +; frame (bp,sp,fp). +; +; Furthermore: in every test function: +; . there is always one integer and 1 floating point argument to be able +; to check those are accessed correctly. +; . there is always one local variable to check that is accessed +; correctly +; +; The LLVM-IR below was produced by clang on the following C++ code: +;extern "C" int g(); +;extern "C" int novla_nodynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10, +; double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10) +;{ +; // use an argument passed on the stack. +; volatile int l1; +; return i10 + (int)d10 + l1 + g(); +;} +;extern "C" int novla_nodynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10, +; double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10) +;{ +; // use an argument passed on the stack. +; volatile int l1; +; return i10 + (int)d10 + l1; +;} +;extern "C" int novla_dynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10, +; double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10) +;{ +; // use an argument passed on the stack. +; alignas(128) volatile int l1; +; return i10 + (int)d10 + l1 + g(); +;} +;extern "C" int novla_dynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10, +; double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10) +;{ +; // use an argument passed on the stack. +; alignas(128) volatile int l1; +; return i10 + (int)d10 + l1; +;} +; +;extern "C" int vla_nodynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10, +; double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10) +;{ +; // use an argument passed on the stack. +; volatile int l1; +; volatile int vla[i1]; +; return i10 + (int)d10 + l1 + g() + vla[0]; +;} +;extern "C" int vla_nodynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10, +; double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10) +;{ +; // use an argument passed on the stack. +; volatile int l1; +; volatile int vla[i1]; +; return i10 + (int)d10 + l1 + vla[0]; +;} +;extern "C" int vla_dynamicrealign_call(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10, +; double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10) +;{ +; // use an argument passed on the stack. +; alignas(128) volatile int l1; +; volatile int vla[i1]; +; return i10 + (int)d10 + l1 + g() + vla[0]; +;} +;extern "C" int vla_dynamicrealign_nocall(int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, int i10, +; double d1, double d2, double d3, double d4, double d5, double d6, double d7, double d8, double d9, double d10) +;{ +; // use an argument passed on the stack. +; alignas(128) volatile int l1; +; volatile int vla[i1]; +; return i10 + (int)d10 + l1 + vla[0]; +;} + + + +define i32 @novla_nodynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 { +entry: + %l1 = alloca i32, align 4 + %conv = fptosi double %d10 to i32 + %add = add nsw i32 %conv, %i10 + %l1.0.l1.0. = load volatile i32, i32* %l1, align 4 + %add1 = add nsw i32 %add, %l1.0.l1.0. + %call = tail call i32 @g() + %add2 = add nsw i32 %add1, %call + ret i32 %add2 +} +; CHECK-LABEL: novla_nodynamicrealign_call +; CHECK: .cfi_startproc +; Check that used callee-saved registers are saved +; CHECK: stp x20, x19, [sp, #-32]! +; Check that the frame pointer is created: +; CHECK: stp x29, x30, [sp, #16] +; CHECK: add x29, sp, #16 +; Check correctness of cfi pseudo-instructions +; CHECK: .cfi_def_cfa w29, 16 +; CHECK: .cfi_offset w30, -8 +; CHECK: .cfi_offset w29, -16 +; CHECK: .cfi_offset w19, -24 +; CHECK: .cfi_offset w20, -32 +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] +; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] +; Check correct access to local variable on the stack, through stack pointer +; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12] +; Check epilogue: +; CHECK: ldp x29, x30, [sp, #16] +; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ret +; CHECK: .cfi_endproc + + +declare i32 @g() #0 + +; Function Attrs: nounwind +define i32 @novla_nodynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 { +entry: + %l1 = alloca i32, align 4 + %conv = fptosi double %d10 to i32 + %add = add nsw i32 %conv, %i10 + %l1.0.l1.0. = load volatile i32, i32* %l1, align 4 + %add1 = add nsw i32 %add, %l1.0.l1.0. + ret i32 %add1 +} +; CHECK-LABEL: novla_nodynamicrealign_nocall +; Check that space is reserved for one local variable on the stack. +; CHECK: sub sp, sp, #16 // =16 +; Check correct access to arguments passed on the stack, through stack pointer +; CHECK: ldr d[[DARG:[0-9]+]], [sp, #40] +; CHECK: ldr w[[IARG:[0-9]+]], [sp, #24] +; Check correct access to local variable on the stack, through stack pointer +; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12] +; Check epilogue: +; CHECK: add sp, sp, #16 // =16 +; CHECK: ret + + +define i32 @novla_dynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 { +entry: + %l1 = alloca i32, align 128 + %conv = fptosi double %d10 to i32 + %add = add nsw i32 %conv, %i10 + %l1.0.l1.0. = load volatile i32, i32* %l1, align 128 + %add1 = add nsw i32 %add, %l1.0.l1.0. + %call = tail call i32 @g() + %add2 = add nsw i32 %add1, %call + ret i32 %add2 +} + +; CHECK-LABEL: novla_dynamicrealign_call +; CHECK: .cfi_startproc +; Check that used callee-saved registers are saved +; CHECK: stp x20, x19, [sp, #-32]! +; Check that the frame pointer is created: +; CHECK: stp x29, x30, [sp, #16] +; CHECK: add x29, sp, #16 +; Check the dynamic realignment of the stack pointer to a 128-byte boundary +; CHECK: sub x9, sp, #96 +; CHECK: and sp, x9, #0xffffffffffffff80 +; Check correctness of cfi pseudo-instructions +; CHECK: .cfi_def_cfa w29, 16 +; CHECK: .cfi_offset w30, -8 +; CHECK: .cfi_offset w29, -16 +; CHECK: .cfi_offset w19, -24 +; CHECK: .cfi_offset w20, -32 +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] +; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] +; Check correct access to local variable on the stack, through re-aligned stack pointer +; CHECK: ldr w[[ILOC:[0-9]+]], [sp] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK: sub sp, x29, #16 // =16 +; CHECK: ldp x29, x30, [sp, #16] +; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ret +; CHECK: .cfi_endproc + + +; Function Attrs: nounwind +define i32 @novla_dynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 { +entry: + %l1 = alloca i32, align 128 + %conv = fptosi double %d10 to i32 + %add = add nsw i32 %conv, %i10 + %l1.0.l1.0. = load volatile i32, i32* %l1, align 128 + %add1 = add nsw i32 %add, %l1.0.l1.0. + ret i32 %add1 +} + +; CHECK-LABEL: novla_dynamicrealign_nocall +; Check that the frame pointer is created: +; CHECK: stp x29, x30, [sp, #-16]! +; CHECK: mov x29, sp +; Check the dynamic realignment of the stack pointer to a 128-byte boundary +; CHECK: sub x9, sp, #112 +; CHECK: and sp, x9, #0xffffffffffffff80 +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] +; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] +; Check correct access to local variable on the stack, through re-aligned stack pointer +; CHECK: ldr w[[ILOC:[0-9]+]], [sp] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK: mov sp, x29 +; CHECK: ldp x29, x30, [sp], #16 +; CHECK: ret + + +define i32 @vla_nodynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 { +entry: + %l1 = alloca i32, align 4 + %0 = zext i32 %i1 to i64 + %vla = alloca i32, i64 %0, align 4 + %conv = fptosi double %d10 to i32 + %add = add nsw i32 %conv, %i10 + %l1.0.l1.0. = load volatile i32, i32* %l1, align 4 + %add1 = add nsw i32 %add, %l1.0.l1.0. + %call = tail call i32 @g() + %add2 = add nsw i32 %add1, %call + %1 = load volatile i32, i32* %vla, align 4, !tbaa !1 + %add3 = add nsw i32 %add2, %1 + ret i32 %add3 +} + +; CHECK-LABEL: vla_nodynamicrealign_call +; CHECK: .cfi_startproc +; Check that used callee-saved registers are saved +; CHECK: stp x20, x19, [sp, #-32]! +; Check that the frame pointer is created: +; CHECK: stp x29, x30, [sp, #16] +; CHECK: add x29, sp, #16 +; Check that space is reserved on the stack for the local variable, +; rounded up to a multiple of 16 to keep the stack pointer 16-byte aligned. +; CHECK: sub sp, sp, #16 +; Check correctness of cfi pseudo-instructions +; CHECK: .cfi_def_cfa w29, 16 +; CHECK: .cfi_offset w30, -8 +; CHECK: .cfi_offset w29, -16 +; CHECK: .cfi_offset w19, -24 +; CHECK: .cfi_offset w20, -32 +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] +; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] +; Check correct reservation of 16-byte aligned VLA (size in w0) on stack +; CHECK: ubfx x9, x0, #0, #32 +; CHECK: lsl x9, x9, #2 +; CHECK: add x9, x9, #15 +; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: mov x10, sp +; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 +; CHECK: mov sp, x[[VLASPTMP]] +; Check correct access to local variable, through frame pointer +; CHECK: ldur w[[ILOC:[0-9]+]], [x29, #-20] +; Check correct accessing of the VLA variable through the base pointer +; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK: sub sp, x29, #16 // =16 +; CHECK: ldp x29, x30, [sp, #16] +; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ret +; CHECK: .cfi_endproc + + +; Function Attrs: nounwind +define i32 @vla_nodynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 { +entry: + %l1 = alloca i32, align 4 + %0 = zext i32 %i1 to i64 + %vla = alloca i32, i64 %0, align 4 + %conv = fptosi double %d10 to i32 + %add = add nsw i32 %conv, %i10 + %l1.0.l1.0. = load volatile i32, i32* %l1, align 4 + %add1 = add nsw i32 %add, %l1.0.l1.0. + %1 = load volatile i32, i32* %vla, align 4, !tbaa !1 + %add2 = add nsw i32 %add1, %1 + ret i32 %add2 +} + +; CHECK-LABEL: vla_nodynamicrealign_nocall +; Check that the frame pointer is created: +; CHECK: stp x29, x30, [sp, #-16]! +; CHECK: mov x29, sp +; Check that space is reserved on the stack for the local variable, +; rounded up to a multiple of 16 to keep the stack pointer 16-byte aligned. +; CHECK: sub sp, sp, #16 +; Check correctness of cfi pseudo-instructions +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] +; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] +; Check correct reservation of 16-byte aligned VLA (size in w0) on stack +; CHECK: ubfx x9, x0, #0, #32 +; CHECK: lsl x9, x9, #2 +; CHECK: add x9, x9, #15 +; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: mov x10, sp +; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 +; CHECK: mov sp, x[[VLASPTMP]] +; Check correct access to local variable, through frame pointer +; CHECK: ldur w[[ILOC:[0-9]+]], [x29, #-4] +; Check correct accessing of the VLA variable through the base pointer +; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK: mov sp, x29 +; CHECK: ldp x29, x30, [sp], #16 +; CHECK: ret + + +define i32 @vla_dynamicrealign_call(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #0 { +entry: + %l1 = alloca i32, align 128 + %0 = zext i32 %i1 to i64 + %vla = alloca i32, i64 %0, align 4 + %conv = fptosi double %d10 to i32 + %add = add nsw i32 %conv, %i10 + %l1.0.l1.0. = load volatile i32, i32* %l1, align 128 + %add1 = add nsw i32 %add, %l1.0.l1.0. + %call = tail call i32 @g() + %add2 = add nsw i32 %add1, %call + %1 = load volatile i32, i32* %vla, align 4, !tbaa !1 + %add3 = add nsw i32 %add2, %1 + ret i32 %add3 +} + +; CHECK-LABEL: vla_dynamicrealign_call +; CHECK: .cfi_startproc +; Check that used callee-saved registers are saved +; CHECK: stp x22, x21, [sp, #-48]! +; CHECK: stp x20, x19, [sp, #16] +; Check that the frame pointer is created: +; CHECK: stp x29, x30, [sp, #32] +; CHECK: add x29, sp, #32 +; Check that the stack pointer gets re-aligned to 128 +; bytes & the base pointer (x19) gets initialized to +; this 128-byte aligned area for local variables & +; spill slots +; CHECK: sub x9, sp, #80 // =80 +; CHECK: and sp, x9, #0xffffffffffffff80 +; CHECK: mov x19, sp +; Check correctness of cfi pseudo-instructions +; CHECK: .cfi_def_cfa w29, 16 +; CHECK: .cfi_offset w30, -8 +; CHECK: .cfi_offset w29, -16 +; CHECK: .cfi_offset w19, -24 +; CHECK: .cfi_offset w20, -32 +; CHECK: .cfi_offset w21, -40 +; CHECK: .cfi_offset w22, -48 +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] +; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] +; Check correct reservation of 16-byte aligned VLA (size in w0) on stack +; and set-up of base pointer (x19). +; CHECK: ubfx x9, x0, #0, #32 +; CHECK: lsl x9, x9, #2 +; CHECK: add x9, x9, #15 +; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: mov x10, sp +; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 +; CHECK: mov sp, x[[VLASPTMP]] +; Check correct access to local variable, through base pointer +; CHECK: ldr w[[ILOC:[0-9]+]], [x19] +; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK: sub sp, x29, #32 +; CHECK: ldp x29, x30, [sp, #32] +; CHECK: ldp x20, x19, [sp, #16] +; CHECK: ldp x22, x21, [sp], #48 +; CHECK: ret +; CHECK: .cfi_endproc + + +; Function Attrs: nounwind +define i32 @vla_dynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 { +entry: + %l1 = alloca i32, align 128 + %0 = zext i32 %i1 to i64 + %vla = alloca i32, i64 %0, align 4 + %conv = fptosi double %d10 to i32 + %add = add nsw i32 %conv, %i10 + %l1.0.l1.0. = load volatile i32, i32* %l1, align 128 + %add1 = add nsw i32 %add, %l1.0.l1.0. + %1 = load volatile i32, i32* %vla, align 4, !tbaa !1 + %add2 = add nsw i32 %add1, %1 + ret i32 %add2 +} + +; CHECK-LABEL: vla_dynamicrealign_nocall +; Check that used callee-saved registers are saved +; CHECK: stp x20, x19, [sp, #-32]! +; Check that the frame pointer is created: +; CHECK: stp x29, x30, [sp, #16] +; CHECK: add x29, sp, #16 +; Check that the stack pointer gets re-aligned to 128 +; bytes & the base pointer (x19) gets initialized to +; this 128-byte aligned area for local variables & +; spill slots +; CHECK: sub x9, sp, #96 +; CHECK: and sp, x9, #0xffffffffffffff80 +; CHECK: mov x19, sp +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] +; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] +; Check correct reservation of 16-byte aligned VLA (size in w0) on stack +; and set-up of base pointer (x19). +; CHECK: ubfx x9, x0, #0, #32 +; CHECK: lsl x9, x9, #2 +; CHECK: add x9, x9, #15 +; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: mov x10, sp +; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 +; CHECK: mov sp, x[[VLASPTMP]] +; Check correct access to local variable, through base pointer +; CHECK: ldr w[[ILOC:[0-9]+]], [x19] +; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK: sub sp, x29, #16 +; CHECK: ldp x29, x30, [sp, #16] +; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ret + + +; Function Attrs: nounwind +define i32 @vla_dynamicrealign_nocall_large_align(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 { +entry: + %l1 = alloca i32, align 32768 + %0 = zext i32 %i1 to i64 + %vla = alloca i32, i64 %0, align 4 + %conv = fptosi double %d10 to i32 + %add = add nsw i32 %conv, %i10 + %l1.0.l1.0. = load volatile i32, i32* %l1, align 32768 + %add1 = add nsw i32 %add, %l1.0.l1.0. + %1 = load volatile i32, i32* %vla, align 4, !tbaa !1 + %add2 = add nsw i32 %add1, %1 + ret i32 %add2 +} + +; CHECK-LABEL: vla_dynamicrealign_nocall_large_align +; Check that used callee-saved registers are saved +; CHECK: stp x20, x19, [sp, #-32]! +; Check that the frame pointer is created: +; CHECK: stp x29, x30, [sp, #16] +; CHECK: add x29, sp, #16 +; Check that the stack pointer gets re-aligned to 128 +; bytes & the base pointer (x19) gets initialized to +; this 128-byte aligned area for local variables & +; spill slots +; CHECK: sub x9, sp, #7, lsl #12 +; CHECK: and sp, x9, #0xffffffffffff8000 +; CHECK: mov x19, sp +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] +; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] +; Check correct reservation of 16-byte aligned VLA (size in w0) on stack +; and set-up of base pointer (x19). +; CHECK: ubfx x9, x0, #0, #32 +; CHECK: lsl x9, x9, #2 +; CHECK: add x9, x9, #15 +; CHECK: and x9, x9, #0xfffffffffffffff0 +; CHECK: mov x10, sp +; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 +; CHECK: mov sp, x[[VLASPTMP]] +; Check correct access to local variable, through base pointer +; CHECK: ldr w[[ILOC:[0-9]+]], [x19] +; CHECK: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK: sub sp, x29, #16 +; CHECK: ldp x29, x30, [sp, #16] +; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ret + +attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll index 09b9f62..d6350a6 100644 --- a/test/CodeGen/AArch64/addsub.ll +++ b/test/CodeGen/AArch64/addsub.ll @@ -24,6 +24,34 @@ define void @add_small() { ret void } +; Make sure we grab the imm variant when the register operand +; can be implicitly zero-extend. +; We used to generate something horrible like this: +; wA = ldrb +; xB = ldimm 12 +; xC = add xB, wA, uxtb +; whereas this can be achieved with: +; wA = ldrb +; xC = add xA, #12 ; <- xA implicitly zero extend wA. +define void @add_small_imm(i8* %p, i64* %q, i32 %b, i32* %addr) { +; CHECK-LABEL: add_small_imm: +entry: + +; CHECK: ldrb w[[LOAD32:[0-9]+]], [x0] + %t = load i8, i8* %p + %promoted = zext i8 %t to i64 + %zextt = zext i8 %t to i32 + %add = add nuw i32 %zextt, %b + +; CHECK: add [[ADD2:x[0-9]+]], x[[LOAD32]], #12 + %add2 = add nuw i64 %promoted, 12 + store i32 %add, i32* %addr + +; CHECK: str [[ADD2]], [x1] + store i64 %add2, i64* %q + ret void +} + ; Add 12-bit immediates, shifted left by 12 bits define void @add_med() { ; CHECK-LABEL: add_med: diff --git a/test/CodeGen/AArch64/argument-blocks.ll b/test/CodeGen/AArch64/argument-blocks.ll index f1dcfa6..3169abc 100644 --- a/test/CodeGen/AArch64/argument-blocks.ll +++ b/test/CodeGen/AArch64/argument-blocks.ll @@ -64,7 +64,7 @@ define void @test_varargs_stackalign() { ; CHECK-LABEL: test_varargs_stackalign: ; CHECK-DARWINPCS: stp {{w[0-9]+}}, {{w[0-9]+}}, [sp, #16] - call void(...)* @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0]) + call void(...) @callee([3 x float] undef, [2 x float] [float 1.0, float 2.0]) ret void } diff --git a/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll b/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll index 41e22e9..b760261 100644 --- a/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll +++ b/test/CodeGen/AArch64/arm64-2012-06-06-FPToUI.ll @@ -16,11 +16,11 @@ entry: %0 = load double, double* %d.addr, align 8 %1 = load double, double* %d.addr, align 8 %conv = fptoui double %1 to i64 - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), double %0, i64 %conv) + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), double %0, i64 %conv) %2 = load double, double* %d.addr, align 8 %3 = load double, double* %d.addr, align 8 %conv1 = fptoui double %3 to i32 - %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), double %2, i32 %conv1) + %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str1, i32 0, i32 0), double %2, i32 %conv1) ret void } @@ -37,12 +37,12 @@ entry: %conv = fpext float %0 to double %1 = load float, float* %f.addr, align 4 %conv1 = fptoui float %1 to i64 - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str2, i32 0, i32 0), double %conv, i64 %conv1) + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str2, i32 0, i32 0), double %conv, i64 %conv1) %2 = load float, float* %f.addr, align 4 %conv2 = fpext float %2 to double %3 = load float, float* %f.addr, align 4 %conv3 = fptoui float %3 to i32 - %call4 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), double %conv2, i32 %conv3) + %call4 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str3, i32 0, i32 0), double %conv2, i32 %conv3) ret void } diff --git a/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll b/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll index 6266d1c..8784abd 100644 --- a/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll +++ b/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll @@ -7,13 +7,13 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone { ; CHECK-LABEL: bar: ; CHECK: add.2d v[[REG:[0-9]+]], v0, v1 ; CHECK: add d[[REG3:[0-9]+]], d[[REG]], d1 +; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1 ; Without advanced copy optimization, we end up with cross register ; banks copies that cannot be coalesced. ; CHECK-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]] ; With advanced copy optimization, we end up with just one copy ; to insert the computed high part into the V register. ; CHECK-OPT-NOT: fmov -; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1 ; CHECK: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]] ; CHECK-NOOPT: fmov d0, [[COPY_REG3]] ; CHECK-OPT-NOT: fmov @@ -23,9 +23,9 @@ define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone { ; GENERIC-LABEL: bar: ; GENERIC: add v[[REG:[0-9]+]].2d, v0.2d, v1.2d ; GENERIC: add d[[REG3:[0-9]+]], d[[REG]], d1 +; GENERIC: sub d[[REG2:[0-9]+]], d[[REG]], d1 ; GENERIC-NOOPT: fmov [[COPY_REG3:x[0-9]+]], d[[REG3]] ; GENERIC-OPT-NOT: fmov -; GENERIC: sub d[[REG2:[0-9]+]], d[[REG]], d1 ; GENERIC: fmov [[COPY_REG2:x[0-9]+]], d[[REG2]] ; GENERIC-NOOPT: fmov d0, [[COPY_REG3]] ; GENERIC-OPT-NOT: fmov diff --git a/test/CodeGen/AArch64/arm64-aapcs.ll b/test/CodeGen/AArch64/arm64-aapcs.ll index 41c3ad5..390a3c7 100644 --- a/test/CodeGen/AArch64/arm64-aapcs.ll +++ b/test/CodeGen/AArch64/arm64-aapcs.ll @@ -78,7 +78,7 @@ declare void @variadic(i32 %a, ...) ; Under AAPCS variadic functions have the same calling convention as ; others. The extra arguments should go in registers rather than on the stack. define void @test_variadic() { - call void(i32, ...)* @variadic(i32 0, i64 1, double 2.0) + call void(i32, ...) @variadic(i32 0, i64 1, double 2.0) ; CHECK: fmov d0, #2.0 ; CHECK: orr w1, wzr, #0x1 ; CHECK: bl variadic diff --git a/test/CodeGen/AArch64/arm64-abi-varargs.ll b/test/CodeGen/AArch64/arm64-abi-varargs.ll index f95fec6..03414b5 100644 --- a/test/CodeGen/AArch64/arm64-abi-varargs.ll +++ b/test/CodeGen/AArch64/arm64-abi-varargs.ll @@ -94,7 +94,7 @@ define i32 @main() nounwind ssp { %10 = load i32, i32* %a10, align 4 %11 = load i32, i32* %a11, align 4 %12 = load i32, i32* %a12, align 4 - call void (i32, i32, i32, i32, i32, i32, i32, i32, i32, ...)* @fn9(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12) + call void (i32, i32, i32, i32, i32, i32, i32, i32, i32, ...) @fn9(i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12) ret i32 0 } @@ -133,7 +133,7 @@ entry: store <4 x i32> %y, <4 x i32>* %y.addr, align 16 %0 = load i32, i32* %x.addr, align 4 %1 = load <4 x i32>, <4 x i32>* %y.addr, align 16 - call void (i8*, ...)* @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1) + call void (i8*, ...) @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1) ret void } @@ -186,6 +186,6 @@ entry: %1 = load i32, i32* %x.addr, align 4 %2 = bitcast %struct.s41* %s41 to i128* %3 = load i128, i128* %2, align 1 - call void (i8*, ...)* @foo2(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3) + call void (i8*, ...) @foo2(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %1, i128 %3) ret void } diff --git a/test/CodeGen/AArch64/arm64-anyregcc-crash.ll b/test/CodeGen/AArch64/arm64-anyregcc-crash.ll index 241cf97..56c62d5 100644 --- a/test/CodeGen/AArch64/arm64-anyregcc-crash.ll +++ b/test/CodeGen/AArch64/arm64-anyregcc-crash.ll @@ -8,7 +8,7 @@ define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i6 i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24, i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) { entry: - %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32, + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32, i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8, i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16, i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24, diff --git a/test/CodeGen/AArch64/arm64-anyregcc.ll b/test/CodeGen/AArch64/arm64-anyregcc.ll index e26875d..2a2f451 100644 --- a/test/CodeGen/AArch64/arm64-anyregcc.ll +++ b/test/CodeGen/AArch64/arm64-anyregcc.ll @@ -55,7 +55,7 @@ ; CHECK-NEXT: .long 3 define i64 @test() nounwind ssp uwtable { entry: - call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3) + call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 16, i8* null, i32 2, i32 1, i32 2, i64 3) ret i64 0 } @@ -77,7 +77,7 @@ entry: define i64 @property_access1(i8* %obj) nounwind ssp uwtable { entry: %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 1, i32 20, i8* %f, i32 1, i8* %obj) ret i64 %ret } @@ -100,7 +100,7 @@ define i64 @property_access2() nounwind ssp uwtable { entry: %obj = alloca i64, align 8 %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %f, i32 1, i64* %obj) ret i64 %ret } @@ -123,7 +123,7 @@ define i64 @property_access3() nounwind ssp uwtable { entry: %obj = alloca i64, align 8 %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 3, i32 20, i8* %f, i32 0, i64* %obj) ret i64 %ret } @@ -205,7 +205,7 @@ entry: define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 4, i32 20, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) ret i64 %ret } @@ -287,7 +287,7 @@ entry: define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { entry: %f = inttoptr i64 281474417671919 to i8* - %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) ret i64 %ret } @@ -315,7 +315,7 @@ entry: ; CHECK-NEXT: .long 0 define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: - %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2) + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 12, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2) tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind ret i64 %result } @@ -355,7 +355,7 @@ entry: define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind - %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4) + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 13, i32 16, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4) ret i64 %result } diff --git a/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll b/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll index c280bef..d089767 100644 --- a/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll +++ b/test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll @@ -1,6 +1,10 @@ ; RUN: llc -mtriple aarch64_be < %s -aarch64-load-store-opt=false -o - | FileCheck %s ; RUN: llc -mtriple aarch64_be < %s -aarch64-load-store-opt=false -fast-isel=true -O0 -o - | FileCheck %s +; Note, we split the functions in to multiple BBs below to isolate the call +; instruction we want to test, from fast-isel failing to select instructions +; after it. + ; CHECK-LABEL: test_i64_f64: declare i64 @test_i64_f64_helper(double %p) define void @test_i64_f64(double* %p, i64* %q) { @@ -8,6 +12,8 @@ define void @test_i64_f64(double* %p, i64* %q) { %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call i64 @test_i64_f64_helper(double %2) + br label %return_bb +return_bb: %4 = add i64 %3, %3 store i64 %4, i64* %q ret void @@ -20,6 +26,8 @@ define void @test_i64_v1i64(<1 x i64>* %p, i64* %q) { %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call i64 @test_i64_v1i64_helper(<1 x i64> %2) + br label %return_bb +return_bb: %4 = add i64 %3, %3 store i64 %4, i64* %q ret void @@ -32,6 +40,8 @@ define void @test_i64_v2f32(<2 x float>* %p, i64* %q) { %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call i64 @test_i64_v2f32_helper(<2 x float> %2) + br label %return_bb +return_bb: %4 = add i64 %3, %3 store i64 %4, i64* %q ret void @@ -44,6 +54,8 @@ define void @test_i64_v2i32(<2 x i32>* %p, i64* %q) { %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call i64 @test_i64_v2i32_helper(<2 x i32> %2) + br label %return_bb +return_bb: %4 = add i64 %3, %3 store i64 %4, i64* %q ret void @@ -56,6 +68,8 @@ define void @test_i64_v4i16(<4 x i16>* %p, i64* %q) { %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call i64 @test_i64_v4i16_helper(<4 x i16> %2) + br label %return_bb +return_bb: %4 = add i64 %3, %3 store i64 %4, i64* %q ret void @@ -68,6 +82,8 @@ define void @test_i64_v8i8(<8 x i8>* %p, i64* %q) { %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call i64 @test_i64_v8i8_helper(<8 x i8> %2) + br label %return_bb +return_bb: %4 = add i64 %3, %3 store i64 %4, i64* %q ret void @@ -80,6 +96,8 @@ define void @test_f64_i64(i64* %p, double* %q) { %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call double @test_f64_i64_helper(i64 %2) + br label %return_bb +return_bb: %4 = fadd double %3, %3 store double %4, double* %q ret void @@ -92,6 +110,8 @@ define void @test_f64_v1i64(<1 x i64>* %p, double* %q) { %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call double @test_f64_v1i64_helper(<1 x i64> %2) + br label %return_bb +return_bb: %4 = fadd double %3, %3 store double %4, double* %q ret void @@ -104,6 +124,8 @@ define void @test_f64_v2f32(<2 x float>* %p, double* %q) { %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call double @test_f64_v2f32_helper(<2 x float> %2) + br label %return_bb +return_bb: %4 = fadd double %3, %3 store double %4, double* %q ret void @@ -116,6 +138,8 @@ define void @test_f64_v2i32(<2 x i32>* %p, double* %q) { %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call double @test_f64_v2i32_helper(<2 x i32> %2) + br label %return_bb +return_bb: %4 = fadd double %3, %3 store double %4, double* %q ret void @@ -128,6 +152,8 @@ define void @test_f64_v4i16(<4 x i16>* %p, double* %q) { %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call double @test_f64_v4i16_helper(<4 x i16> %2) + br label %return_bb +return_bb: %4 = fadd double %3, %3 store double %4, double* %q ret void @@ -140,6 +166,8 @@ define void @test_f64_v8i8(<8 x i8>* %p, double* %q) { %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call double @test_f64_v8i8_helper(<8 x i8> %2) + br label %return_bb +return_bb: %4 = fadd double %3, %3 store double %4, double* %q ret void @@ -152,6 +180,8 @@ define void @test_v1i64_i64(i64* %p, <1 x i64>* %q) { %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <1 x i64> @test_v1i64_i64_helper(i64 %2) + br label %return_bb +return_bb: %4 = add <1 x i64> %3, %3 store <1 x i64> %4, <1 x i64>* %q ret void @@ -164,6 +194,8 @@ define void @test_v1i64_f64(double* %p, <1 x i64>* %q) { %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <1 x i64> @test_v1i64_f64_helper(double %2) + br label %return_bb +return_bb: %4 = add <1 x i64> %3, %3 store <1 x i64> %4, <1 x i64>* %q ret void @@ -176,6 +208,8 @@ define void @test_v1i64_v2f32(<2 x float>* %p, <1 x i64>* %q) { %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <1 x i64> @test_v1i64_v2f32_helper(<2 x float> %2) + br label %return_bb +return_bb: %4 = add <1 x i64> %3, %3 store <1 x i64> %4, <1 x i64>* %q ret void @@ -188,6 +222,8 @@ define void @test_v1i64_v2i32(<2 x i32>* %p, <1 x i64>* %q) { %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <1 x i64> @test_v1i64_v2i32_helper(<2 x i32> %2) + br label %return_bb +return_bb: %4 = add <1 x i64> %3, %3 store <1 x i64> %4, <1 x i64>* %q ret void @@ -200,6 +236,8 @@ define void @test_v1i64_v4i16(<4 x i16>* %p, <1 x i64>* %q) { %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <1 x i64> @test_v1i64_v4i16_helper(<4 x i16> %2) + br label %return_bb +return_bb: %4 = add <1 x i64> %3, %3 store <1 x i64> %4, <1 x i64>* %q ret void @@ -212,6 +250,8 @@ define void @test_v1i64_v8i8(<8 x i8>* %p, <1 x i64>* %q) { %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <1 x i64> @test_v1i64_v8i8_helper(<8 x i8> %2) + br label %return_bb +return_bb: %4 = add <1 x i64> %3, %3 store <1 x i64> %4, <1 x i64>* %q ret void @@ -224,6 +264,8 @@ define void @test_v2f32_i64(i64* %p, <2 x float>* %q) { %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <2 x float> @test_v2f32_i64_helper(i64 %2) + br label %return_bb +return_bb: %4 = fadd <2 x float> %3, %3 store <2 x float> %4, <2 x float>* %q ret void @@ -236,6 +278,8 @@ define void @test_v2f32_f64(double* %p, <2 x float>* %q) { %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <2 x float> @test_v2f32_f64_helper(double %2) + br label %return_bb +return_bb: %4 = fadd <2 x float> %3, %3 store <2 x float> %4, <2 x float>* %q ret void @@ -248,6 +292,8 @@ define void @test_v2f32_v1i64(<1 x i64>* %p, <2 x float>* %q) { %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <2 x float> @test_v2f32_v1i64_helper(<1 x i64> %2) + br label %return_bb +return_bb: %4 = fadd <2 x float> %3, %3 store <2 x float> %4, <2 x float>* %q ret void @@ -261,6 +307,8 @@ define void @test_v2f32_v2i32(<2 x i32>* %p, <2 x float>* %q) { %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <2 x float> @test_v2f32_v2i32_helper(<2 x i32> %2) + br label %return_bb +return_bb: %4 = fadd <2 x float> %3, %3 store <2 x float> %4, <2 x float>* %q ret void @@ -274,6 +322,8 @@ define void @test_v2f32_v4i16(<4 x i16>* %p, <2 x float>* %q) { %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <2 x float> @test_v2f32_v4i16_helper(<4 x i16> %2) + br label %return_bb +return_bb: %4 = fadd <2 x float> %3, %3 store <2 x float> %4, <2 x float>* %q ret void @@ -287,6 +337,8 @@ define void @test_v2f32_v8i8(<8 x i8>* %p, <2 x float>* %q) { %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <2 x float> @test_v2f32_v8i8_helper(<8 x i8> %2) + br label %return_bb +return_bb: %4 = fadd <2 x float> %3, %3 store <2 x float> %4, <2 x float>* %q ret void @@ -299,6 +351,8 @@ define void @test_v2i32_i64(i64* %p, <2 x i32>* %q) { %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <2 x i32> @test_v2i32_i64_helper(i64 %2) + br label %return_bb +return_bb: %4 = add <2 x i32> %3, %3 store <2 x i32> %4, <2 x i32>* %q ret void @@ -311,6 +365,8 @@ define void @test_v2i32_f64(double* %p, <2 x i32>* %q) { %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <2 x i32> @test_v2i32_f64_helper(double %2) + br label %return_bb +return_bb: %4 = add <2 x i32> %3, %3 store <2 x i32> %4, <2 x i32>* %q ret void @@ -323,6 +379,8 @@ define void @test_v2i32_v1i64(<1 x i64>* %p, <2 x i32>* %q) { %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <2 x i32> @test_v2i32_v1i64_helper(<1 x i64> %2) + br label %return_bb +return_bb: %4 = add <2 x i32> %3, %3 store <2 x i32> %4, <2 x i32>* %q ret void @@ -336,6 +394,8 @@ define void @test_v2i32_v2f32(<2 x float>* %p, <2 x i32>* %q) { %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <2 x i32> @test_v2i32_v2f32_helper(<2 x float> %2) + br label %return_bb +return_bb: %4 = add <2 x i32> %3, %3 store <2 x i32> %4, <2 x i32>* %q ret void @@ -349,6 +409,8 @@ define void @test_v2i32_v4i16(<4 x i16>* %p, <2 x i32>* %q) { %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <2 x i32> @test_v2i32_v4i16_helper(<4 x i16> %2) + br label %return_bb +return_bb: %4 = add <2 x i32> %3, %3 store <2 x i32> %4, <2 x i32>* %q ret void @@ -362,6 +424,8 @@ define void @test_v2i32_v8i8(<8 x i8>* %p, <2 x i32>* %q) { %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <2 x i32> @test_v2i32_v8i8_helper(<8 x i8> %2) + br label %return_bb +return_bb: %4 = add <2 x i32> %3, %3 store <2 x i32> %4, <2 x i32>* %q ret void @@ -374,6 +438,8 @@ define void @test_v4i16_i64(i64* %p, <4 x i16>* %q) { %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <4 x i16> @test_v4i16_i64_helper(i64 %2) + br label %return_bb +return_bb: %4 = add <4 x i16> %3, %3 store <4 x i16> %4, <4 x i16>* %q ret void @@ -386,6 +452,8 @@ define void @test_v4i16_f64(double* %p, <4 x i16>* %q) { %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <4 x i16> @test_v4i16_f64_helper(double %2) + br label %return_bb +return_bb: %4 = add <4 x i16> %3, %3 store <4 x i16> %4, <4 x i16>* %q ret void @@ -398,6 +466,8 @@ define void @test_v4i16_v1i64(<1 x i64>* %p, <4 x i16>* %q) { %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <4 x i16> @test_v4i16_v1i64_helper(<1 x i64> %2) + br label %return_bb +return_bb: %4 = add <4 x i16> %3, %3 store <4 x i16> %4, <4 x i16>* %q ret void @@ -411,6 +481,8 @@ define void @test_v4i16_v2f32(<2 x float>* %p, <4 x i16>* %q) { %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <4 x i16> @test_v4i16_v2f32_helper(<2 x float> %2) + br label %return_bb +return_bb: %4 = add <4 x i16> %3, %3 store <4 x i16> %4, <4 x i16>* %q ret void @@ -424,6 +496,8 @@ define void @test_v4i16_v2i32(<2 x i32>* %p, <4 x i16>* %q) { %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <4 x i16> @test_v4i16_v2i32_helper(<2 x i32> %2) + br label %return_bb +return_bb: %4 = add <4 x i16> %3, %3 store <4 x i16> %4, <4 x i16>* %q ret void @@ -437,6 +511,8 @@ define void @test_v4i16_v8i8(<8 x i8>* %p, <4 x i16>* %q) { %1 = load <8 x i8>, <8 x i8>* %p %2 = add <8 x i8> %1, %1 %3 = call <4 x i16> @test_v4i16_v8i8_helper(<8 x i8> %2) + br label %return_bb +return_bb: %4 = add <4 x i16> %3, %3 store <4 x i16> %4, <4 x i16>* %q ret void @@ -449,6 +525,8 @@ define void @test_v8i8_i64(i64* %p, <8 x i8>* %q) { %1 = load i64, i64* %p %2 = add i64 %1, %1 %3 = call <8 x i8> @test_v8i8_i64_helper(i64 %2) + br label %return_bb +return_bb: %4 = add <8 x i8> %3, %3 store <8 x i8> %4, <8 x i8>* %q ret void @@ -461,6 +539,8 @@ define void @test_v8i8_f64(double* %p, <8 x i8>* %q) { %1 = load double, double* %p %2 = fadd double %1, %1 %3 = call <8 x i8> @test_v8i8_f64_helper(double %2) + br label %return_bb +return_bb: %4 = add <8 x i8> %3, %3 store <8 x i8> %4, <8 x i8>* %q ret void @@ -473,6 +553,8 @@ define void @test_v8i8_v1i64(<1 x i64>* %p, <8 x i8>* %q) { %1 = load <1 x i64>, <1 x i64>* %p %2 = add <1 x i64> %1, %1 %3 = call <8 x i8> @test_v8i8_v1i64_helper(<1 x i64> %2) + br label %return_bb +return_bb: %4 = add <8 x i8> %3, %3 store <8 x i8> %4, <8 x i8>* %q ret void @@ -486,6 +568,8 @@ define void @test_v8i8_v2f32(<2 x float>* %p, <8 x i8>* %q) { %1 = load <2 x float>, <2 x float>* %p %2 = fadd <2 x float> %1, %1 %3 = call <8 x i8> @test_v8i8_v2f32_helper(<2 x float> %2) + br label %return_bb +return_bb: %4 = add <8 x i8> %3, %3 store <8 x i8> %4, <8 x i8>* %q ret void @@ -499,6 +583,8 @@ define void @test_v8i8_v2i32(<2 x i32>* %p, <8 x i8>* %q) { %1 = load <2 x i32>, <2 x i32>* %p %2 = add <2 x i32> %1, %1 %3 = call <8 x i8> @test_v8i8_v2i32_helper(<2 x i32> %2) + br label %return_bb +return_bb: %4 = add <8 x i8> %3, %3 store <8 x i8> %4, <8 x i8>* %q ret void @@ -512,6 +598,8 @@ define void @test_v8i8_v4i16(<4 x i16>* %p, <8 x i8>* %q) { %1 = load <4 x i16>, <4 x i16>* %p %2 = add <4 x i16> %1, %1 %3 = call <8 x i8> @test_v8i8_v4i16_helper(<4 x i16> %2) + br label %return_bb +return_bb: %4 = add <8 x i8> %3, %3 store <8 x i8> %4, <8 x i8>* %q ret void @@ -524,6 +612,8 @@ define void @test_f128_v2f64(<2 x double>* %p, fp128* %q) { %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call fp128 @test_f128_v2f64_helper(<2 x double> %2) + br label %return_bb +return_bb: %4 = fadd fp128 %3, %3 store fp128 %4, fp128* %q ret void @@ -536,6 +626,8 @@ define void @test_f128_v2i64(<2 x i64>* %p, fp128* %q) { %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call fp128 @test_f128_v2i64_helper(<2 x i64> %2) + br label %return_bb +return_bb: %4 = fadd fp128 %3, %3 store fp128 %4, fp128* %q ret void @@ -549,6 +641,8 @@ define void @test_f128_v4f32(<4 x float>* %p, fp128* %q) { %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call fp128 @test_f128_v4f32_helper(<4 x float> %2) + br label %return_bb +return_bb: %4 = fadd fp128 %3, %3 store fp128 %4, fp128* %q ret void @@ -562,6 +656,8 @@ define void @test_f128_v4i32(<4 x i32>* %p, fp128* %q) { %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call fp128 @test_f128_v4i32_helper(<4 x i32> %2) + br label %return_bb +return_bb: %4 = fadd fp128 %3, %3 store fp128 %4, fp128* %q ret void @@ -575,6 +671,8 @@ define void @test_f128_v8i16(<8 x i16>* %p, fp128* %q) { %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call fp128 @test_f128_v8i16_helper(<8 x i16> %2) + br label %return_bb +return_bb: %4 = fadd fp128 %3, %3 store fp128 %4, fp128* %q ret void @@ -588,6 +686,8 @@ define void @test_f128_v16i8(<16 x i8>* %p, fp128* %q) { %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call fp128 @test_f128_v16i8_helper(<16 x i8> %2) + br label %return_bb +return_bb: %4 = fadd fp128 %3, %3 store fp128 %4, fp128* %q ret void @@ -600,6 +700,8 @@ define void @test_v2f64_f128(fp128* %p, <2 x double>* %q) { %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <2 x double> @test_v2f64_f128_helper(fp128 %2) + br label %return_bb +return_bb: %4 = fadd <2 x double> %3, %3 store <2 x double> %4, <2 x double>* %q ret void @@ -613,6 +715,8 @@ define void @test_v2f64_v2i64(<2 x i64>* %p, <2 x double>* %q) { %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <2 x double> @test_v2f64_v2i64_helper(<2 x i64> %2) + br label %return_bb +return_bb: %4 = fadd <2 x double> %3, %3 store <2 x double> %4, <2 x double>* %q ret void @@ -627,6 +731,8 @@ define void @test_v2f64_v4f32(<4 x float>* %p, <2 x double>* %q) { %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <2 x double> @test_v2f64_v4f32_helper(<4 x float> %2) + br label %return_bb +return_bb: %4 = fadd <2 x double> %3, %3 store <2 x double> %4, <2 x double>* %q ret void @@ -641,6 +747,8 @@ define void @test_v2f64_v4i32(<4 x i32>* %p, <2 x double>* %q) { %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <2 x double> @test_v2f64_v4i32_helper(<4 x i32> %2) + br label %return_bb +return_bb: %4 = fadd <2 x double> %3, %3 store <2 x double> %4, <2 x double>* %q ret void @@ -655,6 +763,8 @@ define void @test_v2f64_v8i16(<8 x i16>* %p, <2 x double>* %q) { %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <2 x double> @test_v2f64_v8i16_helper(<8 x i16> %2) + br label %return_bb +return_bb: %4 = fadd <2 x double> %3, %3 store <2 x double> %4, <2 x double>* %q ret void @@ -669,6 +779,8 @@ define void @test_v2f64_v16i8(<16 x i8>* %p, <2 x double>* %q) { %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <2 x double> @test_v2f64_v16i8_helper(<16 x i8> %2) + br label %return_bb +return_bb: %4 = fadd <2 x double> %3, %3 store <2 x double> %4, <2 x double>* %q ret void @@ -681,6 +793,8 @@ define void @test_v2i64_f128(fp128* %p, <2 x i64>* %q) { %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <2 x i64> @test_v2i64_f128_helper(fp128 %2) + br label %return_bb +return_bb: %4 = add <2 x i64> %3, %3 store <2 x i64> %4, <2 x i64>* %q ret void @@ -694,6 +808,8 @@ define void @test_v2i64_v2f64(<2 x double>* %p, <2 x i64>* %q) { %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <2 x i64> @test_v2i64_v2f64_helper(<2 x double> %2) + br label %return_bb +return_bb: %4 = add <2 x i64> %3, %3 store <2 x i64> %4, <2 x i64>* %q ret void @@ -708,6 +824,8 @@ define void @test_v2i64_v4f32(<4 x float>* %p, <2 x i64>* %q) { %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <2 x i64> @test_v2i64_v4f32_helper(<4 x float> %2) + br label %return_bb +return_bb: %4 = add <2 x i64> %3, %3 store <2 x i64> %4, <2 x i64>* %q ret void @@ -722,6 +840,8 @@ define void @test_v2i64_v4i32(<4 x i32>* %p, <2 x i64>* %q) { %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <2 x i64> @test_v2i64_v4i32_helper(<4 x i32> %2) + br label %return_bb +return_bb: %4 = add <2 x i64> %3, %3 store <2 x i64> %4, <2 x i64>* %q ret void @@ -736,6 +856,8 @@ define void @test_v2i64_v8i16(<8 x i16>* %p, <2 x i64>* %q) { %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <2 x i64> @test_v2i64_v8i16_helper(<8 x i16> %2) + br label %return_bb +return_bb: %4 = add <2 x i64> %3, %3 store <2 x i64> %4, <2 x i64>* %q ret void @@ -750,6 +872,8 @@ define void @test_v2i64_v16i8(<16 x i8>* %p, <2 x i64>* %q) { %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <2 x i64> @test_v2i64_v16i8_helper(<16 x i8> %2) + br label %return_bb +return_bb: %4 = add <2 x i64> %3, %3 store <2 x i64> %4, <2 x i64>* %q ret void @@ -763,6 +887,8 @@ define void @test_v4f32_f128(fp128* %p, <4 x float>* %q) { %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <4 x float> @test_v4f32_f128_helper(fp128 %2) + br label %return_bb +return_bb: %4 = fadd <4 x float> %3, %3 store <4 x float> %4, <4 x float>* %q ret void @@ -777,6 +903,8 @@ define void @test_v4f32_v2f64(<2 x double>* %p, <4 x float>* %q) { %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <4 x float> @test_v4f32_v2f64_helper(<2 x double> %2) + br label %return_bb +return_bb: %4 = fadd <4 x float> %3, %3 store <4 x float> %4, <4 x float>* %q ret void @@ -791,6 +919,8 @@ define void @test_v4f32_v2i64(<2 x i64>* %p, <4 x float>* %q) { %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <4 x float> @test_v4f32_v2i64_helper(<2 x i64> %2) + br label %return_bb +return_bb: %4 = fadd <4 x float> %3, %3 store <4 x float> %4, <4 x float>* %q ret void @@ -806,6 +936,8 @@ define void @test_v4f32_v4i32(<4 x i32>* %p, <4 x float>* %q) { %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <4 x float> @test_v4f32_v4i32_helper(<4 x i32> %2) + br label %return_bb +return_bb: %4 = fadd <4 x float> %3, %3 store <4 x float> %4, <4 x float>* %q ret void @@ -821,6 +953,8 @@ define void @test_v4f32_v8i16(<8 x i16>* %p, <4 x float>* %q) { %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <4 x float> @test_v4f32_v8i16_helper(<8 x i16> %2) + br label %return_bb +return_bb: %4 = fadd <4 x float> %3, %3 store <4 x float> %4, <4 x float>* %q ret void @@ -836,6 +970,8 @@ define void @test_v4f32_v16i8(<16 x i8>* %p, <4 x float>* %q) { %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <4 x float> @test_v4f32_v16i8_helper(<16 x i8> %2) + br label %return_bb +return_bb: %4 = fadd <4 x float> %3, %3 store <4 x float> %4, <4 x float>* %q ret void @@ -849,6 +985,8 @@ define void @test_v4i32_f128(fp128* %p, <4 x i32>* %q) { %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <4 x i32> @test_v4i32_f128_helper(fp128 %2) + br label %return_bb +return_bb: %4 = add <4 x i32> %3, %3 store <4 x i32> %4, <4 x i32>* %q ret void @@ -863,6 +1001,8 @@ define void @test_v4i32_v2f64(<2 x double>* %p, <4 x i32>* %q) { %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <4 x i32> @test_v4i32_v2f64_helper(<2 x double> %2) + br label %return_bb +return_bb: %4 = add <4 x i32> %3, %3 store <4 x i32> %4, <4 x i32>* %q ret void @@ -877,6 +1017,8 @@ define void @test_v4i32_v2i64(<2 x i64>* %p, <4 x i32>* %q) { %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <4 x i32> @test_v4i32_v2i64_helper(<2 x i64> %2) + br label %return_bb +return_bb: %4 = add <4 x i32> %3, %3 store <4 x i32> %4, <4 x i32>* %q ret void @@ -892,6 +1034,8 @@ define void @test_v4i32_v4f32(<4 x float>* %p, <4 x i32>* %q) { %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <4 x i32> @test_v4i32_v4f32_helper(<4 x float> %2) + br label %return_bb +return_bb: %4 = add <4 x i32> %3, %3 store <4 x i32> %4, <4 x i32>* %q ret void @@ -907,6 +1051,8 @@ define void @test_v4i32_v8i16(<8 x i16>* %p, <4 x i32>* %q) { %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <4 x i32> @test_v4i32_v8i16_helper(<8 x i16> %2) + br label %return_bb +return_bb: %4 = add <4 x i32> %3, %3 store <4 x i32> %4, <4 x i32>* %q ret void @@ -922,6 +1068,8 @@ define void @test_v4i32_v16i8(<16 x i8>* %p, <4 x i32>* %q) { %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <4 x i32> @test_v4i32_v16i8_helper(<16 x i8> %2) + br label %return_bb +return_bb: %4 = add <4 x i32> %3, %3 store <4 x i32> %4, <4 x i32>* %q ret void @@ -935,6 +1083,8 @@ define void @test_v8i16_f128(fp128* %p, <8 x i16>* %q) { %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <8 x i16> @test_v8i16_f128_helper(fp128 %2) + br label %return_bb +return_bb: %4 = add <8 x i16> %3, %3 store <8 x i16> %4, <8 x i16>* %q ret void @@ -949,6 +1099,8 @@ define void @test_v8i16_v2f64(<2 x double>* %p, <8 x i16>* %q) { %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <8 x i16> @test_v8i16_v2f64_helper(<2 x double> %2) + br label %return_bb +return_bb: %4 = add <8 x i16> %3, %3 store <8 x i16> %4, <8 x i16>* %q ret void @@ -963,6 +1115,8 @@ define void @test_v8i16_v2i64(<2 x i64>* %p, <8 x i16>* %q) { %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <8 x i16> @test_v8i16_v2i64_helper(<2 x i64> %2) + br label %return_bb +return_bb: %4 = add <8 x i16> %3, %3 store <8 x i16> %4, <8 x i16>* %q ret void @@ -978,6 +1132,8 @@ define void @test_v8i16_v4f32(<4 x float>* %p, <8 x i16>* %q) { %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <8 x i16> @test_v8i16_v4f32_helper(<4 x float> %2) + br label %return_bb +return_bb: %4 = add <8 x i16> %3, %3 store <8 x i16> %4, <8 x i16>* %q ret void @@ -993,6 +1149,8 @@ define void @test_v8i16_v4i32(<4 x i32>* %p, <8 x i16>* %q) { %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <8 x i16> @test_v8i16_v4i32_helper(<4 x i32> %2) + br label %return_bb +return_bb: %4 = add <8 x i16> %3, %3 store <8 x i16> %4, <8 x i16>* %q ret void @@ -1008,6 +1166,8 @@ define void @test_v8i16_v16i8(<16 x i8>* %p, <8 x i16>* %q) { %1 = load <16 x i8>, <16 x i8>* %p %2 = add <16 x i8> %1, %1 %3 = call <8 x i16> @test_v8i16_v16i8_helper(<16 x i8> %2) + br label %return_bb +return_bb: %4 = add <8 x i16> %3, %3 store <8 x i16> %4, <8 x i16>* %q ret void @@ -1021,6 +1181,8 @@ define void @test_v16i8_f128(fp128* %p, <16 x i8>* %q) { %1 = load fp128, fp128* %p %2 = fadd fp128 %1, %1 %3 = call <16 x i8> @test_v16i8_f128_helper(fp128 %2) + br label %return_bb +return_bb: %4 = add <16 x i8> %3, %3 store <16 x i8> %4, <16 x i8>* %q ret void @@ -1035,6 +1197,8 @@ define void @test_v16i8_v2f64(<2 x double>* %p, <16 x i8>* %q) { %1 = load <2 x double>, <2 x double>* %p %2 = fadd <2 x double> %1, %1 %3 = call <16 x i8> @test_v16i8_v2f64_helper(<2 x double> %2) + br label %return_bb +return_bb: %4 = add <16 x i8> %3, %3 store <16 x i8> %4, <16 x i8>* %q ret void @@ -1049,6 +1213,8 @@ define void @test_v16i8_v2i64(<2 x i64>* %p, <16 x i8>* %q) { %1 = load <2 x i64>, <2 x i64>* %p %2 = add <2 x i64> %1, %1 %3 = call <16 x i8> @test_v16i8_v2i64_helper(<2 x i64> %2) + br label %return_bb +return_bb: %4 = add <16 x i8> %3, %3 store <16 x i8> %4, <16 x i8>* %q ret void @@ -1064,6 +1230,8 @@ define void @test_v16i8_v4f32(<4 x float>* %p, <16 x i8>* %q) { %1 = load <4 x float>, <4 x float>* %p %2 = fadd <4 x float> %1, %1 %3 = call <16 x i8> @test_v16i8_v4f32_helper(<4 x float> %2) + br label %return_bb +return_bb: %4 = add <16 x i8> %3, %3 store <16 x i8> %4, <16 x i8>* %q ret void @@ -1079,6 +1247,8 @@ define void @test_v16i8_v4i32(<4 x i32>* %p, <16 x i8>* %q) { %1 = load <4 x i32>, <4 x i32>* %p %2 = add <4 x i32> %1, %1 %3 = call <16 x i8> @test_v16i8_v4i32_helper(<4 x i32> %2) + br label %return_bb +return_bb: %4 = add <16 x i8> %3, %3 store <16 x i8> %4, <16 x i8>* %q ret void @@ -1094,6 +1264,8 @@ define void @test_v16i8_v8i16(<8 x i16>* %p, <16 x i8>* %q) { %1 = load <8 x i16>, <8 x i16>* %p %2 = add <8 x i16> %1, %1 %3 = call <16 x i8> @test_v16i8_v8i16_helper(<8 x i16> %2) + br label %return_bb +return_bb: %4 = add <16 x i8> %3, %3 store <16 x i8> %4, <16 x i8>* %q ret void diff --git a/test/CodeGen/AArch64/arm64-call-tailcalls.ll b/test/CodeGen/AArch64/arm64-call-tailcalls.ll index 71d9327..6621db2 100644 --- a/test/CodeGen/AArch64/arm64-call-tailcalls.ll +++ b/test/CodeGen/AArch64/arm64-call-tailcalls.ll @@ -53,9 +53,9 @@ bb: ; preds = %entry define i32 @t8(i32 %x) nounwind ssp { ; CHECK-LABEL: t8: +; CHECK: b _c ; CHECK: b _a ; CHECK: b _b -; CHECK: b _c %and = and i32 %x, 1 %tobool = icmp eq i32 %and, 0 br i1 %tobool, label %if.end, label %if.then diff --git a/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll b/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll new file mode 100644 index 0000000..f0b8299 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll @@ -0,0 +1,638 @@ +; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=NONSTRESS +; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -stress-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=OPT --check-prefix=STRESS +; RUN: opt -codegenprepare < %s -mtriple=aarch64-apple-ios -S -disable-cgp-ext-ld-promotion | FileCheck %s --check-prefix=OPTALL --check-prefix=DISABLE + +; CodeGenPrepare should move the zext into the block with the load +; so that SelectionDAG can select it with the load. +; +; OPTALL-LABEL: @foo +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; OPTALL-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; OPTALL: store i32 [[ZEXT]], i32* %q +; OPTALL: ret +define void @foo(i8* %p, i32* %q) { +entry: + %t = load i8, i8* %p + %a = icmp slt i8 %t, 20 + br i1 %a, label %true, label %false +true: + %s = zext i8 %t to i32 + store i32 %s, i32* %q + ret void +false: + ret void +} + +; Check that we manage to form a zextload is an operation with only one +; argument to explicitly extend is in the the way. +; OPTALL-LABEL: @promoteOneArg +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; OPT-NEXT: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT]], 2 +; Make sure the operation is not promoted when the promotion pass is disabled. +; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], 2 +; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 +; OPTALL: store i32 [[RES]], i32* %q +; OPTALL: ret +define void @promoteOneArg(i8* %p, i32* %q) { +entry: + %t = load i8, i8* %p + %add = add nuw i8 %t, 2 + %a = icmp slt i8 %t, 20 + br i1 %a, label %true, label %false +true: + %s = zext i8 %add to i32 + store i32 %s, i32* %q + ret void +false: + ret void +} + +; Check that we manage to form a sextload is an operation with only one +; argument to explicitly extend is in the the way. +; Version with sext. +; OPTALL-LABEL: @promoteOneArgSExt +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32 +; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXT]], 2 +; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], 2 +; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32 +; OPTALL: store i32 [[RES]], i32* %q +; OPTALL: ret +define void @promoteOneArgSExt(i8* %p, i32* %q) { +entry: + %t = load i8, i8* %p + %add = add nsw i8 %t, 2 + %a = icmp slt i8 %t, 20 + br i1 %a, label %true, label %false +true: + %s = sext i8 %add to i32 + store i32 %s, i32* %q + ret void +false: + ret void +} + +; Check that we manage to form a zextload is an operation with two +; arguments to explicitly extend is in the the way. +; Extending %add will create two extensions: +; 1. One for %b. +; 2. One for %t. +; #1 will not be removed as we do not know anything about %b. +; #2 may not be merged with the load because %t is used in a comparison. +; Since two extensions may be emitted in the end instead of one before the +; transformation, the regular heuristic does not apply the optimization. +; +; OPTALL-LABEL: @promoteTwoArgZext +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32 +; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]] +; +; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b +; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 +; +; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b +; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 +; +; OPTALL: store i32 [[RES]], i32* %q +; OPTALL: ret +define void @promoteTwoArgZext(i8* %p, i32* %q, i8 %b) { +entry: + %t = load i8, i8* %p + %add = add nuw i8 %t, %b + %a = icmp slt i8 %t, 20 + br i1 %a, label %true, label %false +true: + %s = zext i8 %add to i32 + store i32 %s, i32* %q + ret void +false: + ret void +} + +; Check that we manage to form a sextload is an operation with two +; arguments to explicitly extend is in the the way. +; Version with sext. +; OPTALL-LABEL: @promoteTwoArgSExt +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; STRESS-NEXT: [[SEXTLD:%[a-zA-Z_0-9-]+]] = sext i8 [[LD]] to i32 +; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i8 %b to i32 +; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SEXTLD]], [[SEXTB]] +; +; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b +; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32 +; +; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i8 [[LD]], %b +; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i8 [[ADD]] to i32 +; OPTALL: store i32 [[RES]], i32* %q +; OPTALL: ret +define void @promoteTwoArgSExt(i8* %p, i32* %q, i8 %b) { +entry: + %t = load i8, i8* %p + %add = add nsw i8 %t, %b + %a = icmp slt i8 %t, 20 + br i1 %a, label %true, label %false +true: + %s = sext i8 %add to i32 + store i32 %s, i32* %q + ret void +false: + ret void +} + +; Check that we do not a zextload if we need to introduce more than +; one additional extension. +; OPTALL-LABEL: @promoteThreeArgZext +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i8 %b to i32 +; STRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]] +; STRESS-NEXT: [[ZEXTC:%[a-zA-Z_0-9-]+]] = zext i8 %c to i32 +; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[TMP]], [[ZEXTC]] +; +; NONSTRESS-NEXT: [[TMP:%[a-zA-Z_0-9-]+]] = add nuw i8 [[LD]], %b +; NONSTRESS-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 [[TMP]], %c +; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 +; +; DISABLE: add nuw i8 +; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i8 +; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i8 [[ADD]] to i32 +; +; OPTALL: store i32 [[RES]], i32* %q +; OPTALL: ret +define void @promoteThreeArgZext(i8* %p, i32* %q, i8 %b, i8 %c) { +entry: + %t = load i8, i8* %p + %tmp = add nuw i8 %t, %b + %add = add nuw i8 %tmp, %c + %a = icmp slt i8 %t, 20 + br i1 %a, label %true, label %false +true: + %s = zext i8 %add to i32 + store i32 %s, i32* %q + ret void +false: + ret void +} + +; Check that we manage to form a zextload after promoting and merging +; two extensions. +; OPTALL-LABEL: @promoteMergeExtArgZExt +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i16 %b to i32 +; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXTLD]], [[ZEXTB]] +; +; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16 +; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b +; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32 +; +; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16 +; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw i16 [[ZEXTLD]], %b +; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = zext i16 [[ADD]] to i32 +; +; OPTALL: store i32 [[RES]], i32* %q +; OPTALL: ret +define void @promoteMergeExtArgZExt(i8* %p, i32* %q, i16 %b) { +entry: + %t = load i8, i8* %p + %ext = zext i8 %t to i16 + %add = add nuw i16 %ext, %b + %a = icmp slt i8 %t, 20 + br i1 %a, label %true, label %false +true: + %s = zext i16 %add to i32 + store i32 %s, i32* %q + ret void +false: + ret void +} + +; Check that we manage to form a sextload after promoting and merging +; two extensions. +; Version with sext. +; OPTALL-LABEL: @promoteMergeExtArgSExt +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; STRESS-NEXT: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; STRESS-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = sext i16 %b to i32 +; STRESS-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXTLD]], [[ZEXTB]] +; +; NONSTRESS: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16 +; NONSTRESS: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b +; NONSTRESS: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32 +; +; DISABLE: [[ZEXTLD:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i16 +; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i16 [[ZEXTLD]], %b +; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32 +; OPTALL: store i32 [[RES]], i32* %q +; OPTALL: ret +define void @promoteMergeExtArgSExt(i8* %p, i32* %q, i16 %b) { +entry: + %t = load i8, i8* %p + %ext = zext i8 %t to i16 + %add = add nsw i16 %ext, %b + %a = icmp slt i8 %t, 20 + br i1 %a, label %true, label %false +true: + %s = sext i16 %add to i32 + store i32 %s, i32* %q + ret void +false: + ret void +} + +; Check that we manage to catch all the extload opportunities that are exposed +; by the different iterations of codegen prepare. +; Moreover, check that we do not promote more than we need to. +; Here is what is happening in this test (not necessarly in this order): +; 1. We try to promote the operand of %sextadd. +; a. This creates one sext of %ld2 and one of %zextld +; b. The sext of %ld2 can be combine with %ld2, so we remove one sext but +; introduced one. This is fine with the current heuristic: neutral. +; => We have one zext of %zextld left and we created one sext of %ld2. +; 2. We try to promote the operand of %sextaddza. +; a. This creates one sext of %zexta and one of %zextld +; b. The sext of %zexta does not lead to any load, it stays here, even if it +; could have been combine with the zext of %a. +; c. The sext of %zextld leads to %ld and can be combined with it. This is +; done by promoting %zextld. This is fine with the current heuristic: +; neutral. +; => We have created a new zext of %ld and we created one sext of %zexta. +; 3. We try to promote the operand of %sextaddb. +; a. This creates one sext of %b and one of %zextld +; b. The sext of %b is a dead-end, nothing to be done. +; c. Same thing as 2.c. happens. +; => We have created a new zext of %ld and we created one sext of %b. +; 4. We try to promote the operand of the zext of %zextld introduced in #1. +; a. Same thing as 2.c. happens. +; b. %zextld does not have any other uses. It is dead coded. +; => We have created a new zext of %ld and we removed a zext of %zextld and +; a zext of %ld. +; Currently we do not try to reuse existing extensions, so in the end we have +; 3 identical zext of %ld. The extensions will be CSE'ed by SDag. +; +; OPTALL-LABEL: @severalPromotions +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %addr1 +; OPT-NEXT: [[ZEXTLD1_1:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; OPT-NEXT: [[ZEXTLD1_2:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; OPT-NEXT: [[ZEXTLD1_3:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; OPT-NEXT: [[LD2:%[a-zA-Z_0-9-]+]] = load i32, i32* %addr2 +; OPT-NEXT: [[SEXTLD2:%[a-zA-Z_0-9-]+]] = sext i32 [[LD2]] to i64 +; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD2]], [[ZEXTLD1_1]] +; We do not combine this one: see 2.b. +; OPT-NEXT: [[ZEXTA:%[a-zA-Z_0-9-]+]] = zext i8 %a to i32 +; OPT-NEXT: [[SEXTZEXTA:%[a-zA-Z_0-9-]+]] = sext i32 [[ZEXTA]] to i64 +; OPT-NEXT: [[RESZA:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTZEXTA]], [[ZEXTLD1_3]] +; OPT-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64 +; OPT-NEXT: [[RESB:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTB]], [[ZEXTLD1_2]] +; +; DISABLE: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 +; DISABLE: [[RES:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64 +; DISABLE: [[ADDZA:%[a-zA-Z_0-9-]+]] = add nsw i32 +; DISABLE: [[RESZA:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDZA]] to i64 +; DISABLE: [[ADDB:%[a-zA-Z_0-9-]+]] = add nsw i32 +; DISABLE: [[RESB:%[a-zA-Z_0-9-]+]] = sext i32 [[ADDB]] to i64 +; +; OPTALL: call void @dummy(i64 [[RES]], i64 [[RESZA]], i64 [[RESB]]) +; OPTALL: ret +define void @severalPromotions(i8* %addr1, i32* %addr2, i8 %a, i32 %b) { + %ld = load i8, i8* %addr1 + %zextld = zext i8 %ld to i32 + %ld2 = load i32, i32* %addr2 + %add = add nsw i32 %ld2, %zextld + %sextadd = sext i32 %add to i64 + %zexta = zext i8 %a to i32 + %addza = add nsw i32 %zexta, %zextld + %sextaddza = sext i32 %addza to i64 + %addb = add nsw i32 %b, %zextld + %sextaddb = sext i32 %addb to i64 + call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb) + ret void +} + +declare void @dummy(i64, i64, i64) + +; Make sure we do not try to promote vector types since the type promotion +; helper does not support them for now. +; OPTALL-LABEL: @vectorPromotion +; OPTALL: [[SHL:%[a-zA-Z_0-9-]+]] = shl nuw nsw <2 x i32> zeroinitializer, +; OPTALL: [[ZEXT:%[a-zA-Z_0-9-]+]] = zext <2 x i32> [[SHL]] to <2 x i64> +; OPTALL: ret +define void @vectorPromotion() { +entry: + %a = shl nuw nsw <2 x i32> zeroinitializer, + %b = zext <2 x i32> %a to <2 x i64> + ret void +} + +@a = common global i32 0, align 4 +@c = common global [2 x i32] zeroinitializer, align 4 + +; Make sure we support promotion of operands that produces a Value as opposed +; to an instruction. +; This used to cause a crash. +; OPTALL-LABEL: @promotionOfArgEndsUpInValue +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i16, i16* %addr +; +; OPT-NEXT: [[SEXT:%[a-zA-Z_0-9-]+]] = sext i16 [[LD]] to i32 +; OPT-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nuw nsw i32 [[SEXT]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i32) +; +; DISABLE-NEXT: [[ADD:%[a-zA-Z_0-9-]+]] = add nuw nsw i16 [[LD]], zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i16) +; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = sext i16 [[ADD]] to i32 +; +; OPTALL-NEXT: ret i32 [[RES]] +define i32 @promotionOfArgEndsUpInValue(i16* %addr) { +entry: + %val = load i16, i16* %addr + %add = add nuw nsw i16 %val, zext (i1 icmp ne (i32* getelementptr inbounds ([2 x i32], [2 x i32]* @c, i64 0, i64 1), i32* @a) to i16) + %conv3 = sext i16 %add to i32 + ret i32 %conv3 +} + +; Check that we see that one zext can be derived from the other for free. +; OPTALL-LABEL: @promoteTwoArgZextWithSourceExtendedTwice +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; OPT-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b +; OPT-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], 12 +; OPT-NEXT: store i32 [[RES32]], i32* %addr +; OPT-NEXT: store i64 [[RES64]], i64* %q +; +; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b +; DISABLE-NEXT: [[RES2_32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], 12 +; DISABLE-NEXT: store i32 [[RES32]], i32* %addr +; DISABLE-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES2_32]] to i64 +; DISABLE-NEXT: store i64 [[ZEXT64]], i64* %q +; +; OPTALL-NEXT: ret void +define void @promoteTwoArgZextWithSourceExtendedTwice(i8* %p, i64* %q, i32 %b, i32* %addr) { +entry: + %t = load i8, i8* %p + %zextt = zext i8 %t to i32 + %add = add nuw i32 %zextt, %b + %add2 = add nuw i32 %zextt, 12 + store i32 %add, i32 *%addr + %s = zext i32 %add2 to i64 + store i64 %s, i64* %q + ret void +} + +; Check that we do not increase the cost of the code. +; The input has one free zext and one free sext. If we would have promoted +; all the way through the load we would end up with a free zext and a +; non-free sext (of %b). +; OPTALL-LABEL: @doNotPromoteFreeSExtFromAddrMode +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64 +; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]] +; STRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = trunc i64 [[IDX64]] to i32 +; +; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b +; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64 +; +; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b +; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64 +; +; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i32, i32* %addr, i64 [[IDX64]] +; OPTALL-NEXT: store i32 [[RES32]], i32* [[GEP]] +; OPTALL-NEXT: ret void +define void @doNotPromoteFreeSExtFromAddrMode(i8* %p, i32 %b, i32* %addr) { +entry: + %t = load i8, i8* %p + %zextt = zext i8 %t to i32 + %add = add nsw i32 %zextt, %b + %idx64 = sext i32 %add to i64 + %staddr = getelementptr inbounds i32, i32* %addr, i64 %idx64 + store i32 %add, i32 *%staddr + ret void +} + +; Check that we do not increase the cost of the code. +; The input has one free zext and one free sext. If we would have promoted +; all the way through the load we would end up with a free zext and a +; non-free sext (of %b). +; OPTALL-LABEL: @doNotPromoteFreeSExtFromAddrMode64 +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64 +; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]] +; +; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b +; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64 +; +; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b +; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64 +; +; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i64, i64* %addr, i64 [[IDX64]] +; OPTALL-NEXT: store i64 %stuff, i64* [[GEP]] +; OPTALL-NEXT: ret void +define void @doNotPromoteFreeSExtFromAddrMode64(i8* %p, i32 %b, i64* %addr, i64 %stuff) { +entry: + %t = load i8, i8* %p + %zextt = zext i8 %t to i32 + %add = add nsw i32 %zextt, %b + %idx64 = sext i32 %add to i64 + %staddr = getelementptr inbounds i64, i64* %addr, i64 %idx64 + store i64 %stuff, i64 *%staddr + ret void +} + +; Check that we do not increase the cost of the code. +; The input has one free zext and one free sext. If we would have promoted +; all the way through the load we would end up with a free zext and a +; non-free sext (of %b). +; OPTALL-LABEL: @doNotPromoteFreeSExtFromAddrMode128 +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64 +; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]] +; +; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b +; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64 +; +; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b +; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64 +; +; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i128, i128* %addr, i64 [[IDX64]] +; OPTALL-NEXT: store i128 %stuff, i128* [[GEP]] +; OPTALL-NEXT: ret void +define void @doNotPromoteFreeSExtFromAddrMode128(i8* %p, i32 %b, i128* %addr, i128 %stuff) { +entry: + %t = load i8, i8* %p + %zextt = zext i8 %t to i32 + %add = add nsw i32 %zextt, %b + %idx64 = sext i32 %add to i64 + %staddr = getelementptr inbounds i128, i128* %addr, i64 %idx64 + store i128 %stuff, i128 *%staddr + ret void +} + + +; Check that we do not increase the cost of the code. +; The input has one free zext and one free sext. If we would have promoted +; all the way through the load we would end up with a free zext and a +; non-free sext (of %b). +; OPTALL-LABEL: @promoteSExtFromAddrMode256 +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; OPT-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64 +; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]] +; +; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b +; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64 +; +; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i256, i256* %addr, i64 [[IDX64]] +; OPTALL-NEXT: store i256 %stuff, i256* [[GEP]] +; OPTALL-NEXT: ret void +define void @promoteSExtFromAddrMode256(i8* %p, i32 %b, i256* %addr, i256 %stuff) { +entry: + %t = load i8, i8* %p + %zextt = zext i8 %t to i32 + %add = add nsw i32 %zextt, %b + %idx64 = sext i32 %add to i64 + %staddr = getelementptr inbounds i256, i256* %addr, i64 %idx64 + store i256 %stuff, i256 *%staddr + ret void +} + +; Check that we do not increase the cost of the code. +; The input has one free zext and one free zext. +; When we promote all the way through the load, we end up with +; a free zext and a non-free zext (of %b). +; However, the current target lowering says zext i32 to i64 is free +; so the promotion happens because the cost did not change and may +; expose more opportunities. +; This would need to be fixed at some point. +; OPTALL-LABEL: @doNotPromoteFreeZExtFromAddrMode +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; This transformation should really happen only for stress mode. +; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; OPT-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64 +; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]] +; OPT-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = trunc i64 [[IDX64]] to i32 +; +; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b +; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES32]] to i64 +; +; OPTALL-NEXT: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i32, i32* %addr, i64 [[IDX64]] +; OPTALL-NEXT: store i32 [[RES32]], i32* [[GEP]] +; OPTALL-NEXT: ret void +define void @doNotPromoteFreeZExtFromAddrMode(i8* %p, i32 %b, i32* %addr) { +entry: + %t = load i8, i8* %p + %zextt = zext i8 %t to i32 + %add = add nuw i32 %zextt, %b + %idx64 = zext i32 %add to i64 + %staddr = getelementptr inbounds i32, i32* %addr, i64 %idx64 + store i32 %add, i32 *%staddr + ret void +} + +; OPTALL-LABEL: @doNotPromoteFreeSExtFromShift +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; STRESS-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; STRESS-NEXT: [[SEXTB:%[a-zA-Z_0-9-]+]] = sext i32 %b to i64 +; STRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nsw i64 [[ZEXT64]], [[SEXTB]] +; +; NONSTRESS-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; NONSTRESS-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b +; NONSTRESS-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64 +; +; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nsw i32 [[ZEXT32]], %b +; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = sext i32 [[RES32]] to i64 +; +; OPTALL-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = shl i64 [[IDX64]], 12 +; OPTALL-NEXT: ret i64 %staddr +define i64 @doNotPromoteFreeSExtFromShift(i8* %p, i32 %b) { +entry: + %t = load i8, i8* %p + %zextt = zext i8 %t to i32 + %add = add nsw i32 %zextt, %b + %idx64 = sext i32 %add to i64 + %staddr = shl i64 %idx64, 12 + ret i64 %staddr +} + +; Same comment as doNotPromoteFreeZExtFromAddrMode. +; OPTALL-LABEL: @doNotPromoteFreeZExtFromShift +; OPTALL: [[LD:%[a-zA-Z_0-9-]+]] = load i8, i8* %p +; +; This transformation should really happen only for stress mode. +; OPT-NEXT: [[ZEXT64:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i64 +; OPT-NEXT: [[ZEXTB:%[a-zA-Z_0-9-]+]] = zext i32 %b to i64 +; OPT-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = add nuw i64 [[ZEXT64]], [[ZEXTB]] +; +; DISABLE-NEXT: [[ZEXT32:%[a-zA-Z_0-9-]+]] = zext i8 [[LD]] to i32 +; DISABLE-NEXT: [[RES32:%[a-zA-Z_0-9-]+]] = add nuw i32 [[ZEXT32]], %b +; DISABLE-NEXT: [[IDX64:%[a-zA-Z_0-9-]+]] = zext i32 [[RES32]] to i64 +; +; OPTALL-NEXT: [[RES64:%[a-zA-Z_0-9-]+]] = shl i64 [[IDX64]], 12 +; OPTALL-NEXT: ret i64 %staddr +define i64 @doNotPromoteFreeZExtFromShift(i8* %p, i32 %b) { +entry: + %t = load i8, i8* %p + %zextt = zext i8 %t to i32 + %add = add nuw i32 %zextt, %b + %idx64 = zext i32 %add to i64 + %staddr = shl i64 %idx64, 12 + ret i64 %staddr +} + +; The input has one free zext and one non-free sext. +; When we promote all the way through to the load, we end up with +; a free zext, a free sext (%ld1), and a non-free sext (of %cst). +; However, we when generate load pair and the free sext(%ld1) becomes +; non-free. So technically, we trade a non-free sext to two non-free +; sext. +; This would need to be fixed at some point. +; OPTALL-LABEL: @doNotPromoteBecauseOfPairedLoad +; OPTALL: [[LD0:%[a-zA-Z_0-9-]+]] = load i32, i32* %p +; OPTALL: [[GEP:%[a-zA-Z_0-9-]+]] = getelementptr inbounds i32, i32* %p, i64 1 +; OPTALL: [[LD1:%[a-zA-Z_0-9-]+]] = load i32, i32* [[GEP]] +; +; This transformation should really happen only for stress mode. +; OPT-NEXT: [[SEXTLD1:%[a-zA-Z_0-9-]+]] = sext i32 [[LD1]] to i64 +; OPT-NEXT: [[SEXTCST:%[a-zA-Z_0-9-]+]] = sext i32 %cst to i64 +; OPT-NEXT: [[SEXTRES:%[a-zA-Z_0-9-]+]] = add nsw i64 [[SEXTLD1]], [[SEXTCST]] +; +; DISABLE-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = add nsw i32 [[LD1]], %cst +; DISABLE-NEXT: [[SEXTRES:%[a-zA-Z_0-9-]+]] = sext i32 [[RES]] to i64 +; +; OPTALL-NEXT: [[ZEXTLD0:%[a-zA-Z_0-9-]+]] = zext i32 [[LD0]] to i64 +; OPTALL-NEXT: [[FINAL:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTRES]], [[ZEXTLD0]] +; OPTALL-NEXT: ret i64 [[FINAL]] +define i64 @doNotPromoteBecauseOfPairedLoad(i32* %p, i32 %cst) { + %ld0 = load i32, i32* %p + %idxLd1 = getelementptr inbounds i32, i32* %p, i64 1 + %ld1 = load i32, i32* %idxLd1 + %res = add nsw i32 %ld1, %cst + %sextres = sext i32 %res to i64 + %zextLd0 = zext i32 %ld0 to i64 + %final = add i64 %sextres, %zextLd0 + ret i64 %final +} diff --git a/test/CodeGen/AArch64/arm64-convert-v4f64.ll b/test/CodeGen/AArch64/arm64-convert-v4f64.ll index c6b7d83..c4e3e4e 100644 --- a/test/CodeGen/AArch64/arm64-convert-v4f64.ll +++ b/test/CodeGen/AArch64/arm64-convert-v4f64.ll @@ -3,11 +3,11 @@ define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) { ; CHECK: fptosi_v4f64_to_v4i16 -; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v1.2d -; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v0.2d -; CHECK-DAG: xtn v[[LHS_NA:[0-9]+]].2s, v[[LHS]].2d -; CHECK-DAG: xtn v[[RHS_NA:[0-9]+]].2s, v[[RHS]].2d -; CHECK: uzp1 v0.4h, v[[RHS_NA]].4h, v[[LHS_NA]].4h +; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d +; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d +; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d +; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d +; CHECK: xtn v0.4h, v[[MID]].4s %tmp1 = load <4 x double>, <4 x double>* %ptr %tmp2 = fptosi <4 x double> %tmp1 to <4 x i16> ret <4 x i16> %tmp2 @@ -15,17 +15,17 @@ define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) { define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) { ; CHECK: fptosi_v4f64_to_v4i8 -; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d -; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d -; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d ; CHECK-DAG: fcvtzs v[[CONV0:[0-9]+]].2d, v0.2d -; CHECK-DAG: xtn v[[NA3:[0-9]+]].2s, v[[CONV3]].2d +; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d +; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d +; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d ; CHECK-DAG: xtn v[[NA2:[0-9]+]].2s, v[[CONV2]].2d -; CHECK-DAG: xtn v[[NA1:[0-9]+]].2s, v[[CONV1]].2d +; CHECK-DAG: xtn2 v[[NA2]].4s, v[[CONV3]].2d ; CHECK-DAG: xtn v[[NA0:[0-9]+]].2s, v[[CONV0]].2d -; CHECK-DAG: uzp1 v[[TMP1:[0-9]+]].4h, v[[CONV2]].4h, v[[CONV3]].4h -; CHECK-DAG: uzp1 v[[TMP2:[0-9]+]].4h, v[[CONV0]].4h, v[[CONV1]].4h -; CHECK: uzp1 v0.8b, v[[TMP2]].8b, v[[TMP1]].8b +; CHECK-DAG: xtn2 v[[NA0]].4s, v[[CONV1]].2d +; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA0]].4s +; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA2]].4s +; CHECK: xtn v0.8b, v[[TMP1]].8h %tmp1 = load <8 x double>, <8 x double>* %ptr %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8> ret <8 x i8> %tmp2 diff --git a/test/CodeGen/AArch64/arm64-dup.ll b/test/CodeGen/AArch64/arm64-dup.ll index 849e227..c6b7de3 100644 --- a/test/CodeGen/AArch64/arm64-dup.ll +++ b/test/CodeGen/AArch64/arm64-dup.ll @@ -321,3 +321,40 @@ entry: %sub = sub <4 x i16> %a, %mul ret <4 x i16> %sub } + +; Also test the DUP path in the PerfectShuffle generator. + +; CHECK-LABEL: test_perfectshuffle_dupext_v4i16: +; CHECK-NEXT: dup.4h v0, v0[0] +; CHECK-NEXT: ext.8b v0, v0, v1, #4 +define <4 x i16> @test_perfectshuffle_dupext_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind { + %r = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> + ret <4 x i16> %r +} + +; CHECK-LABEL: test_perfectshuffle_dupext_v4f16: +; CHECK-NEXT: dup.4h v0, v0[0] +; CHECK-NEXT: ext.8b v0, v0, v1, #4 +; CHECK-NEXT: ret +define <4 x half> @test_perfectshuffle_dupext_v4f16(<4 x half> %a, <4 x half> %b) nounwind { + %r = shufflevector <4 x half> %a, <4 x half> %b, <4 x i32> + ret <4 x half> %r +} + +; CHECK-LABEL: test_perfectshuffle_dupext_v4i32: +; CHECK-NEXT: dup.4s v0, v0[0] +; CHECK-NEXT: ext.16b v0, v0, v1, #8 +; CHECK-NEXT: ret +define <4 x i32> @test_perfectshuffle_dupext_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { + %r = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> + ret <4 x i32> %r +} + +; CHECK-LABEL: test_perfectshuffle_dupext_v4f32: +; CHECK-NEXT: dup.4s v0, v0[0] +; CHECK-NEXT: ext.16b v0, v0, v1, #8 +; CHECK-NEXT: ret +define <4 x float> @test_perfectshuffle_dupext_v4f32(<4 x float> %a, <4 x float> %b) nounwind { + %r = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %r +} diff --git a/test/CodeGen/AArch64/arm64-fcopysign.ll b/test/CodeGen/AArch64/arm64-fcopysign.ll index 66241df..feffd41 100644 --- a/test/CodeGen/AArch64/arm64-fcopysign.ll +++ b/test/CodeGen/AArch64/arm64-fcopysign.ll @@ -39,7 +39,7 @@ entry: ; CHECK: fcvt s0, d0 ; CHECK: movi.4s v[[CONST:[0-9]+]], #0x80, lsl #24 ; CHECK: bit.16b v{{[0-9]+}}, v0, v[[CONST]] - %0 = tail call double (...)* @bar() nounwind + %0 = tail call double (...) @bar() nounwind %1 = fptrunc double %0 to float %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone %3 = fadd float %1, %2 diff --git a/test/CodeGen/AArch64/arm64-join-reserved.ll b/test/CodeGen/AArch64/arm64-join-reserved.ll index e99168b..dee0344 100644 --- a/test/CodeGen/AArch64/arm64-join-reserved.ll +++ b/test/CodeGen/AArch64/arm64-join-reserved.ll @@ -10,7 +10,7 @@ target triple = "arm64-apple-macosx10" ; CHECK: ret define void @g() nounwind ssp { entry: - tail call void (i32, ...)* @f(i32 0, i32 0) nounwind + tail call void (i32, ...) @f(i32 0, i32 0) nounwind ret void } diff --git a/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll b/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll new file mode 100644 index 0000000..5bc4d71 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-misaligned-memcpy-inline.ll @@ -0,0 +1,14 @@ +; RUN: llc -mtriple=arm64-apple-ios -aarch64-strict-align < %s | FileCheck %s + +; Small (16-bytes here) unaligned memcpys should stay memcpy calls if +; strict-alignment is turned on. +define void @t0(i8* %out, i8* %in) { +; CHECK-LABEL: t0: +; CHECK: orr w2, wzr, #0x10 +; CHECK-NEXT: bl _memcpy +entry: + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %out, i8* %in, i64 16, i32 1, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) diff --git a/test/CodeGen/AArch64/arm64-neon-copy.ll b/test/CodeGen/AArch64/arm64-neon-copy.ll index 4a92c3d..b74a406 100644 --- a/test/CodeGen/AArch64/arm64-neon-copy.ll +++ b/test/CodeGen/AArch64/arm64-neon-copy.ll @@ -1086,7 +1086,7 @@ define <2 x i32> @test_concat_diff_v1i32_v1i32(i32 %a, i32 %b) { ; CHECK-LABEL: test_concat_diff_v1i32_v1i32: ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}} ; CHECK: sqabs s{{[0-9]+}}, s{{[0-9]+}} -; CHECK-NEXT: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: ins {{v[0-9]+}}.s[1], w{{[0-9]+}} entry: %c = tail call i32 @llvm.aarch64.neon.sqabs.i32(i32 %a) %d = insertelement <2 x i32> undef, i32 %c, i32 0 diff --git a/test/CodeGen/AArch64/arm64-neon-v8.1a.ll b/test/CodeGen/AArch64/arm64-neon-v8.1a.ll new file mode 100644 index 0000000..51ed8a1 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-neon-v8.1a.ll @@ -0,0 +1,456 @@ +; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V8a +; RUN: llc < %s -verify-machineinstrs -march=arm64 -mattr=+v8.1a -aarch64-neon-syntax=generic | FileCheck %s --check-prefix=CHECK-V81a +; RUN: llc < %s -verify-machineinstrs -march=arm64 -mattr=+v8.1a -aarch64-neon-syntax=apple | FileCheck %s --check-prefix=CHECK-V81a-apple + +declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>) +declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>) +declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>) +declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>) +declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32) +declare i16 @llvm.aarch64.neon.sqrdmulh.i16(i16, i16) + +declare <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>) +declare <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>) +declare <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>) +declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>) +declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) +declare i16 @llvm.aarch64.neon.sqadd.i16(i16, i16) + +declare <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16>, <4 x i16>) +declare <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16>, <8 x i16>) +declare <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32>, <2 x i32>) +declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>) +declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32) +declare i16 @llvm.aarch64.neon.sqsub.i16(i16, i16) + +;----------------------------------------------------------------------------- +; RDMA Vector +; test for SIMDThreeSameVectorSQRDMLxHTiedHS + +define <4 x i16> @test_sqrdmlah_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) { +; CHECK-LABEL: test_sqrdmlah_v4i16: + %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs) + %retval = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc, <4 x i16> %prod) +; CHECK-V8a: sqrdmulh v1.4h, v1.4h, v2.4h +; CHECK-V81a: sqrdmlah v0.4h, v1.4h, v2.4h +; CHECK-V81a-apple: sqrdmlah.4h v0, v1, v2 + ret <4 x i16> %retval +} + +define <8 x i16> @test_sqrdmlah_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) { +; CHECK-LABEL: test_sqrdmlah_v8i16: + %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs) + %retval = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %acc, <8 x i16> %prod) +; CHECK-V8a: sqrdmulh v1.8h, v1.8h, v2.8h +; CHECK-V81a: sqrdmlah v0.8h, v1.8h, v2.8h +; CHECK-V81a-apple: sqrdmlah.8h v0, v1, v2 + ret <8 x i16> %retval +} + +define <2 x i32> @test_sqrdmlah_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) { +; CHECK-LABEL: test_sqrdmlah_v2i32: + %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs) + %retval = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %acc, <2 x i32> %prod) +; CHECK-V8a: sqrdmulh v1.2s, v1.2s, v2.2s +; CHECK-V81a: sqrdmlah v0.2s, v1.2s, v2.2s +; CHECK-V81a-apple: sqrdmlah.2s v0, v1, v2 + ret <2 x i32> %retval +} + +define <4 x i32> @test_sqrdmlah_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) { +; CHECK-LABEL: test_sqrdmlah_v4i32: + %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs) + %retval = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %acc, <4 x i32> %prod) +; CHECK-V81: sqrdmulh v1.4s, v1.4s, v2.4s +; CHECK-V81a: sqrdmlah v0.4s, v1.4s, v2.4s +; CHECK-V81a-apple: sqrdmlah.4s v0, v1, v2 + ret <4 x i32> %retval +} + +define <4 x i16> @test_sqrdmlsh_v4i16(<4 x i16> %acc, <4 x i16> %mhs, <4 x i16> %rhs) { +; CHECK-LABEL: test_sqrdmlsh_v4i16: + %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs) + %retval = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc, <4 x i16> %prod) +; CHECK-V8a: sqrdmulh v1.4h, v1.4h, v2.4h +; CHECK-V81a: sqrdmlsh v0.4h, v1.4h, v2.4h +; CHECK-V81a-apple: sqrdmlsh.4h v0, v1, v2 + ret <4 x i16> %retval +} + +define <8 x i16> @test_sqrdmlsh_v8i16(<8 x i16> %acc, <8 x i16> %mhs, <8 x i16> %rhs) { +; CHECK-LABEL: test_sqrdmlsh_v8i16: + %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs) + %retval = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc, <8 x i16> %prod) +; CHECK-V8a: sqrdmulh v1.8h, v1.8h, v2.8h +; CHECK-V81a: sqrdmlsh v0.8h, v1.8h, v2.8h +; CHECK-V81a-apple: sqrdmlsh.8h v0, v1, v2 + ret <8 x i16> %retval +} + +define <2 x i32> @test_sqrdmlsh_v2i32(<2 x i32> %acc, <2 x i32> %mhs, <2 x i32> %rhs) { +; CHECK-LABEL: test_sqrdmlsh_v2i32: + %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs) + %retval = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %acc, <2 x i32> %prod) +; CHECK-V8a: sqrdmulh v1.2s, v1.2s, v2.2s +; CHECK-V81a: sqrdmlsh v0.2s, v1.2s, v2.2s +; CHECK-V81a-apple: sqrdmlsh.2s v0, v1, v2 + ret <2 x i32> %retval +} + +define <4 x i32> @test_sqrdmlsh_v4i32(<4 x i32> %acc, <4 x i32> %mhs, <4 x i32> %rhs) { +; CHECK-LABEL: test_sqrdmlsh_v4i32: + %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs) + %retval = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %acc, <4 x i32> %prod) +; CHECK-V8a: sqrdmulh v1.4s, v1.4s, v2.4s +; CHECK-V81a: sqrdmlsh v0.4s, v1.4s, v2.4s +; CHECK-V81a-apple: sqrdmlsh.4s v0, v1, v2 + ret <4 x i32> %retval +} + +;----------------------------------------------------------------------------- +; RDMA Vector, by element +; tests for vXiYY_indexed in SIMDIndexedSQRDMLxHSDTied + +define <4 x i16> @test_sqrdmlah_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) { +; CHECK-LABEL: test_sqrdmlah_lane_s16: +entry: + %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> + %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle) + %retval = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc, <4 x i16> %prod) +; CHECK-V8a : sqrdmulh v1.4h, v1.4h, v2.h[3] +; CHECK-V81a: sqrdmlah v0.4h, v1.4h, v2.h[3] +; CHECK-V81a-apple: sqrdmlah.4h v0, v1, v2[3] + ret <4 x i16> %retval +} + +define <8 x i16> @test_sqrdmlahq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <8 x i16> %v) { +; CHECK-LABEL: test_sqrdmlahq_lane_s16: +entry: + %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> + %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle) + %retval = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %acc, <8 x i16> %prod) +; CHECK-V8a: sqrdmulh v1.8h, v1.8h, v2.h[2] +; CHECK-V81a: sqrdmlah v0.8h, v1.8h, v2.h[2] +; CHECK-V81a-apple: sqrdmlah.8h v0, v1, v2[2] + ret <8 x i16> %retval +} + +define <2 x i32> @test_sqrdmlah_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) { +; CHECK-LABEL: test_sqrdmlah_lane_s32: +entry: + %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> + %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle) + %retval = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %acc, <2 x i32> %prod) +; CHECK-V8a: sqrdmulh v1.2s, v1.2s, v2.s[1] +; CHECK-V81a: sqrdmlah v0.2s, v1.2s, v2.s[1] +; CHECK-V81a-apple: sqrdmlah.2s v0, v1, v2[1] + ret <2 x i32> %retval +} + +define <4 x i32> @test_sqrdmlahq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <4 x i32> %v) { +; CHECK-LABEL: test_sqrdmlahq_lane_s32: +entry: + %shuffle = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> zeroinitializer + %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle) + %retval = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %acc, <4 x i32> %prod) +; CHECK-V8a: sqrdmulh v1.4s, v1.4s, v2.s[0] +; CHECK-V81a: sqrdmlah v0.4s, v1.4s, v2.s[0] +; CHECK-V81a-apple: sqrdmlah.4s v0, v1, v2[0] + ret <4 x i32> %retval +} + +define <4 x i16> @test_sqrdmlsh_lane_s16(<4 x i16> %acc, <4 x i16> %x, <4 x i16> %v) { +; CHECK-LABEL: test_sqrdmlsh_lane_s16: +entry: + %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> + %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle) + %retval = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc, <4 x i16> %prod) +; CHECK-V8a: sqrdmulh v1.4h, v1.4h, v2.h[3] +; CHECK-V81a: sqrdmlsh v0.4h, v1.4h, v2.h[3] +; CHECK-V81a-apple: sqrdmlsh.4h v0, v1, v2[3] + ret <4 x i16> %retval +} + +define <8 x i16> @test_sqrdmlshq_lane_s16(<8 x i16> %acc, <8 x i16> %x, <8 x i16> %v) { +; CHECK-LABEL: test_sqrdmlshq_lane_s16: +entry: + %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> + %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle) + %retval = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc, <8 x i16> %prod) +; CHECK-V8a: sqrdmulh v1.8h, v1.8h, v2.h[2] +; CHECK-V81a: sqrdmlsh v0.8h, v1.8h, v2.h[2] +; CHECK-V81a-apple: sqrdmlsh.8h v0, v1, v2[2] + ret <8 x i16> %retval +} + +define <2 x i32> @test_sqrdmlsh_lane_s32(<2 x i32> %acc, <2 x i32> %x, <2 x i32> %v) { +; CHECK-LABEL: test_sqrdmlsh_lane_s32: +entry: + %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> + %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle) + %retval = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %acc, <2 x i32> %prod) +; CHECK-V8a: sqrdmulh v1.2s, v1.2s, v2.s[1] +; CHECK-V81a: sqrdmlsh v0.2s, v1.2s, v2.s[1] +; CHECK-V81a-apple: sqrdmlsh.2s v0, v1, v2[1] + ret <2 x i32> %retval +} + +define <4 x i32> @test_sqrdmlshq_lane_s32(<4 x i32> %acc,<4 x i32> %x, <4 x i32> %v) { +; CHECK-LABEL: test_sqrdmlshq_lane_s32: +entry: + %shuffle = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> zeroinitializer + %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle) + %retval = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %acc, <4 x i32> %prod) +; CHECK-V8a: sqrdmulh v1.4s, v1.4s, v2.s[0] +; CHECK-V81a: sqrdmlsh v0.4s, v1.4s, v2.s[0] +; CHECK-V81a-apple: sqrdmlsh.4s v0, v1, v2[0] + ret <4 x i32> %retval +} + +;----------------------------------------------------------------------------- +; RDMA Vector, by element, extracted +; i16 tests are for vXi16_indexed in SIMDIndexedSQRDMLxHSDTied, with IR in ACLE style +; i32 tests are for "def : Pat" in SIMDIndexedSQRDMLxHSDTied + +define i16 @test_sqrdmlah_extracted_lane_s16(i16 %acc,<4 x i16> %x, <4 x i16> %v) { +; CHECK-LABEL: test_sqrdmlah_extracted_lane_s16: +entry: + %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> + %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle) + %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0 + %retval_vec = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc_vec, <4 x i16> %prod) + %retval = extractelement <4 x i16> %retval_vec, i64 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.4h, v0.4h, v1.h[1] +; CHECK-V81a: sqrdmlah {{v[2-9]+}}.4h, v0.4h, v1.h[1] +; CHECK-V81a-apple: sqrdmlah.4h {{v[2-9]+}}, v0, v1[1] + ret i16 %retval +} + +define i16 @test_sqrdmlahq_extracted_lane_s16(i16 %acc,<8 x i16> %x, <8 x i16> %v) { +; CHECK-LABEL: test_sqrdmlahq_extracted_lane_s16: +entry: + %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> + %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle) + %acc_vec = insertelement <8 x i16> undef, i16 %acc, i64 0 + %retval_vec = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %acc_vec, <8 x i16> %prod) + %retval = extractelement <8 x i16> %retval_vec, i64 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.8h, v0.8h, v1.h[1] +; CHECK-V81a: sqrdmlah {{v[2-9]+}}.8h, v0.8h, v1.h[1] +; CHECK-V81a-apple: sqrdmlah.8h {{v[2-9]+}}, v0, v1[1] + ret i16 %retval +} + +define i32 @test_sqrdmlah_extracted_lane_s32(i32 %acc,<2 x i32> %x, <2 x i32> %v) { +; CHECK-LABEL: test_sqrdmlah_extracted_lane_s32: +entry: + %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> zeroinitializer + %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle) + %extract = extractelement <2 x i32> %prod, i64 0 + %retval = call i32 @llvm.aarch64.neon.sqadd.i32(i32 %acc, i32 %extract) +; CHECK-V8a: sqrdmulh v0.2s, v0.2s, v1.s[0] +; CHECK-V81a: sqrdmlah v2.2s, v0.2s, v1.s[0] +; CHECK-V81a-apple: sqrdmlah.2s v2, v0, v1[0] + ret i32 %retval +} + +define i32 @test_sqrdmlahq_extracted_lane_s32(i32 %acc,<4 x i32> %x, <4 x i32> %v) { +; CHECK-LABEL: test_sqrdmlahq_extracted_lane_s32: +entry: + %shuffle = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> zeroinitializer + %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle) + %extract = extractelement <4 x i32> %prod, i64 0 + %retval = call i32 @llvm.aarch64.neon.sqadd.i32(i32 %acc, i32 %extract) +; CHECK-V8a: sqrdmulh v0.4s, v0.4s, v1.s[0] +; CHECK-V81a: sqrdmlah v2.4s, v0.4s, v1.s[0] +; CHECK-V81a-apple: sqrdmlah.4s v2, v0, v1[0] + ret i32 %retval +} + +define i16 @test_sqrdmlsh_extracted_lane_s16(i16 %acc,<4 x i16> %x, <4 x i16> %v) { +; CHECK-LABEL: test_sqrdmlsh_extracted_lane_s16: +entry: + %shuffle = shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> + %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x, <4 x i16> %shuffle) + %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0 + %retval_vec = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc_vec, <4 x i16> %prod) + %retval = extractelement <4 x i16> %retval_vec, i64 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.4h, v0.4h, v1.h[1] +; CHECK-V81a: sqrdmlsh {{v[2-9]+}}.4h, v0.4h, v1.h[1] +; CHECK-V81a-apple: sqrdmlsh.4h {{v[2-9]+}}, v0, v1[1] + ret i16 %retval +} + +define i16 @test_sqrdmlshq_extracted_lane_s16(i16 %acc,<8 x i16> %x, <8 x i16> %v) { +; CHECK-LABEL: test_sqrdmlshq_extracted_lane_s16: +entry: + %shuffle = shufflevector <8 x i16> %v, <8 x i16> undef, <8 x i32> + %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x, <8 x i16> %shuffle) + %acc_vec = insertelement <8 x i16> undef, i16 %acc, i64 0 + %retval_vec = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc_vec, <8 x i16> %prod) + %retval = extractelement <8 x i16> %retval_vec, i64 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.8h, v0.8h, v1.h[1] +; CHECK-V81a: sqrdmlsh {{v[2-9]+}}.8h, v0.8h, v1.h[1] +; CHECK-V81a-apple: sqrdmlsh.8h {{v[2-9]+}}, v0, v1[1] + ret i16 %retval +} + +define i32 @test_sqrdmlsh_extracted_lane_s32(i32 %acc,<2 x i32> %x, <2 x i32> %v) { +; CHECK-LABEL: test_sqrdmlsh_extracted_lane_s32: +entry: + %shuffle = shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> zeroinitializer + %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %x, <2 x i32> %shuffle) + %extract = extractelement <2 x i32> %prod, i64 0 + %retval = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %acc, i32 %extract) +; CHECK-V8a: sqrdmulh v0.2s, v0.2s, v1.s[0] +; CHECK-V81a: sqrdmlsh v2.2s, v0.2s, v1.s[0] +; CHECK-V81a-apple: sqrdmlsh.2s v2, v0, v1[0] + ret i32 %retval +} + +define i32 @test_sqrdmlshq_extracted_lane_s32(i32 %acc,<4 x i32> %x, <4 x i32> %v) { +; CHECK-LABEL: test_sqrdmlshq_extracted_lane_s32: +entry: + %shuffle = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> zeroinitializer + %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x, <4 x i32> %shuffle) + %extract = extractelement <4 x i32> %prod, i64 0 + %retval = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %acc, i32 %extract) +; CHECK-V8a: sqrdmulh v0.4s, v0.4s, v1.s[0] +; CHECK-V81a: sqrdmlsh v2.4s, v0.4s, v1.s[0] +; CHECK-V81a-apple: sqrdmlsh.4s v2, v0, v1[0] + ret i32 %retval +} + +;----------------------------------------------------------------------------- +; RDMA Scalar +; test for "def : Pat" near SIMDThreeScalarHSTied in AArch64InstInfo.td + +define i16 @test_sqrdmlah_v1i16(i16 %acc, i16 %x, i16 %y) { +; CHECK-LABEL: test_sqrdmlah_v1i16: + %x_vec = insertelement <4 x i16> undef, i16 %x, i64 0 + %y_vec = insertelement <4 x i16> undef, i16 %y, i64 0 + %prod_vec = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x_vec, <4 x i16> %y_vec) + %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0 + %retval_vec = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc_vec, <4 x i16> %prod_vec) + %retval = extractelement <4 x i16> %retval_vec, i64 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +; CHECK-V81a: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +; CHECK-V81a-apple: sqrdmlah.4h {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} + ret i16 %retval +} + +define i32 @test_sqrdmlah_v1i32(i32 %acc, i32 %x, i32 %y) { +; CHECK-LABEL: test_sqrdmlah_v1i32: + %x_vec = insertelement <4 x i32> undef, i32 %x, i64 0 + %y_vec = insertelement <4 x i32> undef, i32 %y, i64 0 + %prod_vec = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x_vec, <4 x i32> %y_vec) + %acc_vec = insertelement <4 x i32> undef, i32 %acc, i64 0 + %retval_vec = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %acc_vec, <4 x i32> %prod_vec) + %retval = extractelement <4 x i32> %retval_vec, i64 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +; CHECK-V81a: sqrdmlah {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +; CHECK-V81a-apple: sqrdmlah.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} + ret i32 %retval +} + + +define i16 @test_sqrdmlsh_v1i16(i16 %acc, i16 %x, i16 %y) { +; CHECK-LABEL: test_sqrdmlsh_v1i16: + %x_vec = insertelement <4 x i16> undef, i16 %x, i64 0 + %y_vec = insertelement <4 x i16> undef, i16 %y, i64 0 + %prod_vec = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x_vec, <4 x i16> %y_vec) + %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0 + %retval_vec = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %acc_vec, <4 x i16> %prod_vec) + %retval = extractelement <4 x i16> %retval_vec, i64 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +; CHECK-V81a: sqrdmlsh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h +; CHECK-V81a-apple: sqrdmlsh.4h {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} + ret i16 %retval +} + +define i32 @test_sqrdmlsh_v1i32(i32 %acc, i32 %x, i32 %y) { +; CHECK-LABEL: test_sqrdmlsh_v1i32: + %x_vec = insertelement <4 x i32> undef, i32 %x, i64 0 + %y_vec = insertelement <4 x i32> undef, i32 %y, i64 0 + %prod_vec = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %x_vec, <4 x i32> %y_vec) + %acc_vec = insertelement <4 x i32> undef, i32 %acc, i64 0 + %retval_vec = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %acc_vec, <4 x i32> %prod_vec) + %retval = extractelement <4 x i32> %retval_vec, i64 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +; CHECK-V81a: sqrdmlsh {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s +; CHECK-V81a-apple: sqrdmlsh.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} + ret i32 %retval +} +define i32 @test_sqrdmlah_i32(i32 %acc, i32 %mhs, i32 %rhs) { +; CHECK-LABEL: test_sqrdmlah_i32: + %prod = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %mhs, i32 %rhs) + %retval = call i32 @llvm.aarch64.neon.sqadd.i32(i32 %acc, i32 %prod) +; CHECK-V8a: sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; CHECK-V81a: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; CHECK-V81a-apple: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret i32 %retval +} + +define i32 @test_sqrdmlsh_i32(i32 %acc, i32 %mhs, i32 %rhs) { +; CHECK-LABEL: test_sqrdmlsh_i32: + %prod = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %mhs, i32 %rhs) + %retval = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %acc, i32 %prod) +; CHECK-V8a: sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; CHECK-V81a: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +; CHECK-V81a-apple: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} + ret i32 %retval +} + +;----------------------------------------------------------------------------- +; RDMA Scalar, by element +; i16 tests are performed via tests in above chapter, with IR in ACLE style +; i32 tests are for i32_indexed in SIMDIndexedSQRDMLxHSDTied + +define i16 @test_sqrdmlah_extract_i16(i16 %acc, i16 %x, <4 x i16> %y_vec) { +; CHECK-LABEL: test_sqrdmlah_extract_i16: + %shuffle = shufflevector <4 x i16> %y_vec, <4 x i16> undef, <4 x i32> + %x_vec = insertelement <4 x i16> undef, i16 %x, i64 0 + %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %x_vec, <4 x i16> %shuffle) + %acc_vec = insertelement <4 x i16> undef, i16 %acc, i64 0 + %retval_vec = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %acc_vec, <4 x i16> %prod) + %retval = extractelement <4 x i16> %retval_vec, i32 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, v0.h[1] +; CHECK-V81a: sqrdmlah {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, v0.h[1] +; CHECK-V81a-apple: sqrdmlah.4h {{v[0-9]+}}, {{v[0-9]+}}, v0[1] + ret i16 %retval +} + +define i32 @test_sqrdmlah_extract_i32(i32 %acc, i32 %mhs, <4 x i32> %rhs) { +; CHECK-LABEL: test_sqrdmlah_extract_i32: + %extract = extractelement <4 x i32> %rhs, i32 3 + %prod = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %mhs, i32 %extract) + %retval = call i32 @llvm.aarch64.neon.sqadd.i32(i32 %acc, i32 %prod) +; CHECK-V8a: sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, v0.s[3] +; CHECK-V81a: sqrdmlah {{s[0-9]+}}, {{s[0-9]+}}, v0.s[3] +; CHECK-V81a-apple: sqrdmlah.s {{s[0-9]+}}, {{s[0-9]+}}, v0[3] + ret i32 %retval +} + +define i16 @test_sqrdmlshq_extract_i16(i16 %acc, i16 %x, <8 x i16> %y_vec) { +; CHECK-LABEL: test_sqrdmlshq_extract_i16: + %shuffle = shufflevector <8 x i16> %y_vec, <8 x i16> undef, <8 x i32> + %x_vec = insertelement <8 x i16> undef, i16 %x, i64 0 + %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %x_vec, <8 x i16> %shuffle) + %acc_vec = insertelement <8 x i16> undef, i16 %acc, i64 0 + %retval_vec = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %acc_vec, <8 x i16> %prod) + %retval = extractelement <8 x i16> %retval_vec, i32 0 +; CHECK-V8a: sqrdmulh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, v0.h[1] +; CHECK-V81a: sqrdmlsh {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, v0.h[1] +; CHECK-V81a-apple: sqrdmlsh.8h {{v[0-9]+}}, {{v[0-9]+}}, v0[1] + ret i16 %retval +} + +define i32 @test_sqrdmlsh_extract_i32(i32 %acc, i32 %mhs, <4 x i32> %rhs) { +; CHECK-LABEL: test_sqrdmlsh_extract_i32: + %extract = extractelement <4 x i32> %rhs, i32 3 + %prod = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %mhs, i32 %extract) + %retval = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %acc, i32 %prod) +; CHECK-V8a: sqrdmulh {{s[0-9]+}}, {{s[0-9]+}}, v0.s[3] +; CHECK-V81a: sqrdmlsh {{s[0-9]+}}, {{s[0-9]+}}, v0.s[3] +; CHECK-V81a-apple: sqrdmlsh.s {{s[0-9]+}}, {{s[0-9]+}}, v0[3] + ret i32 %retval +} diff --git a/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll b/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll index 5a740d8..2651f11 100644 --- a/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll +++ b/test/CodeGen/AArch64/arm64-patchpoint-scratch-regs.ll @@ -9,7 +9,7 @@ define void @clobberScratch(i32* %p) { %v = load i32, i32* %p tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x30},~{x31}"() nounwind - tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 5, i32 20, i8* null, i32 0, i32* %p, i32 %v) + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 5, i32 20, i8* null, i32 0, i32* %p, i32 %v) store i32 %v, i32* %p ret void } diff --git a/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll b/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll index 8f79f80..b8236c5 100644 --- a/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll +++ b/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll @@ -23,9 +23,9 @@ entry: ; FAST-NEXT: movk x16, #0xbeef ; FAST-NEXT: blr x16 %resolveCall2 = inttoptr i64 281474417671919 to i8* - %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2) + %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2) %resolveCall3 = inttoptr i64 244837814038255 to i8* - tail call webkit_jscc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result) + tail call webkit_jscc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveCall3, i32 2, i64 %p4, i64 %result) ret void } @@ -59,7 +59,7 @@ entry: ; FAST-NEXT: movk x16, #0xbeef ; FAST-NEXT: blr x16 %call = inttoptr i64 281474417671919 to i8* - %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6) + %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6) ret i64 %result } @@ -101,7 +101,7 @@ entry: ; FAST-NEXT: movk x16, #0xbeef ; FAST-NEXT: blr x16 %call = inttoptr i64 281474417671919 to i8* - %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10) + %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10) ret i64 %result } diff --git a/test/CodeGen/AArch64/arm64-patchpoint.ll b/test/CodeGen/AArch64/arm64-patchpoint.ll index cf06653..d9ec7e5 100644 --- a/test/CodeGen/AArch64/arm64-patchpoint.ll +++ b/test/CodeGen/AArch64/arm64-patchpoint.ll @@ -16,9 +16,9 @@ entry: ; CHECK-NEXT: blr x16 ; CHECK: ret %resolveCall2 = inttoptr i64 244837814094590 to i8* - %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4) + %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 2, i32 20, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4) %resolveCall3 = inttoptr i64 244837814094591 to i8* - tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 20, i8* %resolveCall3, i32 2, i64 %p1, i64 %result) + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 3, i32 20, i8* %resolveCall3, i32 2, i64 %p1, i64 %result) ret i64 %result } @@ -38,7 +38,7 @@ entry: store i64 11, i64* %metadata store i64 12, i64* %metadata store i64 13, i64* %metadata - call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata) + call void (i64, i32, ...) @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata) ret void } @@ -51,14 +51,14 @@ entry: %tmp80 = add i64 %tmp79, -16 %tmp81 = inttoptr i64 %tmp80 to i64* %tmp82 = load i64, i64* %tmp81, align 8 - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82) - tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82) + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82) %tmp83 = load i64, i64* %tmp33, align 8 %tmp84 = add i64 %tmp83, -24 %tmp85 = inttoptr i64 %tmp84 to i64* %tmp86 = load i64, i64* %tmp85, align 8 - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86) - tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86) + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86) ret i64 10 } @@ -74,7 +74,7 @@ entry: ; CHECK-NEXT: nop ; CHECK-NEXT: ldp ; CHECK-NEXT: ret - %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2) + %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2) ret void } diff --git a/test/CodeGen/AArch64/arm64-stackmap-nops.ll b/test/CodeGen/AArch64/arm64-stackmap-nops.ll index 5915b64..2647ac4 100644 --- a/test/CodeGen/AArch64/arm64-stackmap-nops.ll +++ b/test/CodeGen/AArch64/arm64-stackmap-nops.ll @@ -8,7 +8,7 @@ entry: ; CHECK: nop ; CHECK-NEXT: nop ; CHECK-NOT: nop - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 16) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 16) ret void } diff --git a/test/CodeGen/AArch64/arm64-stackmap.ll b/test/CodeGen/AArch64/arm64-stackmap.ll index 29e4484..1a4df7a 100644 --- a/test/CodeGen/AArch64/arm64-stackmap.ll +++ b/test/CodeGen/AArch64/arm64-stackmap.ll @@ -78,7 +78,7 @@ target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" define void @constantargs() { entry: %0 = inttoptr i64 244837814094590 to i8* - tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 20, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296) + tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 20, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296) ret void } @@ -100,7 +100,7 @@ entry: ; Runtime void->void call. call void inttoptr (i64 244837814094590 to void ()*)() ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars. - call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b) + call void (i64, i32, ...) @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b) ret void } @@ -126,7 +126,7 @@ entry: cold: ; OSR patchpoint with 12-byte nop-slide and 2 live vars. %thunk = inttoptr i64 244837814094590 to i8* - call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4, i32 20, i8* %thunk, i32 0, i64 %a, i64 %b) + call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 4, i32 20, i8* %thunk, i32 0, i64 %a, i64 %b) unreachable ret: ret void @@ -142,7 +142,7 @@ ret: define i64 @propertyRead(i64* %obj) { entry: %resolveRead = inttoptr i64 244837814094590 to i8* - %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveRead, i32 1, i64* %obj) + %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveRead, i32 1, i64* %obj) %add = add i64 %result, 3 ret i64 %add } @@ -162,7 +162,7 @@ entry: define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) { entry: %resolveWrite = inttoptr i64 244837814094590 to i8* - call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveWrite, i32 2, i64* %obj, i64 %a) + call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 6, i32 20, i8* %resolveWrite, i32 2, i64* %obj, i64 %a) ret void } @@ -184,7 +184,7 @@ entry: define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: %resolveCall = inttoptr i64 244837814094590 to i8* - call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 7, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) + call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 7, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) ret void } @@ -206,7 +206,7 @@ entry: define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { entry: %resolveCall = inttoptr i64 244837814094590 to i8* - %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 8, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) + %result = call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 8, i32 20, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) %add = add i64 %result, 3 ret i64 %add } @@ -226,7 +226,7 @@ entry: ; CHECK-NEXT: .short 29 define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) { entry: - call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) + call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 11, i32 20, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) ret void } @@ -245,7 +245,7 @@ entry: ; CHECK-NEXT: .short 29 define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) { entry: - call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) + call void (i64, i32, ...) @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) ret void } @@ -263,7 +263,7 @@ entry: ; CHECK-NEXT: .long 33 define void @liveConstant() { - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 8, i32 33) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 15, i32 8, i32 33) ret void } @@ -280,7 +280,7 @@ define void @liveConstant() { ; CHECK-NEXT: .long -{{[0-9]+}} define void @clobberLR(i32 %a) { tail call void asm sideeffect "nop", "~{x0},~{x1},~{x2},~{x3},~{x4},~{x5},~{x6},~{x7},~{x8},~{x9},~{x10},~{x11},~{x12},~{x13},~{x14},~{x15},~{x16},~{x17},~{x18},~{x19},~{x20},~{x21},~{x22},~{x23},~{x24},~{x25},~{x26},~{x27},~{x28},~{x29},~{x31}"() nounwind - tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 8, i32 %a) + tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 16, i32 8, i32 %a) ret void } diff --git a/test/CodeGen/AArch64/arm64-vshuffle.ll b/test/CodeGen/AArch64/arm64-vshuffle.ll index 75e0d80..15ea21b 100644 --- a/test/CodeGen/AArch64/arm64-vshuffle.ll +++ b/test/CodeGen/AArch64/arm64-vshuffle.ll @@ -1,22 +1,8 @@ ; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -mcpu=cyclone | FileCheck %s -; The mask: -; CHECK: lCPI0_0: -; CHECK: .byte 2 ; 0x2 -; CHECK: .byte 255 ; 0xff -; CHECK: .byte 6 ; 0x6 -; CHECK: .byte 255 ; 0xff -; The second vector is legalized to undef and the elements of the first vector -; are used instead. -; CHECK: .byte 2 ; 0x2 -; CHECK: .byte 4 ; 0x4 -; CHECK: .byte 6 ; 0x6 -; CHECK: .byte 0 ; 0x0 ; CHECK: test1 -; CHECK: ldr d[[REG0:[0-9]+]], [{{.*}}, lCPI0_0 -; CHECK: movi.8h v[[REG1:[0-9]+]], #0x1, lsl #8 -; CHECK: tbl.8b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]] +; CHECK: movi d[[REG0:[0-9]+]], #0000000000000000 define <8 x i1> @test1() { entry: %Shuff = shufflevector <8 x i1> @test2() { bb: %Shuff = shufflevector <8 x i1> zeroinitializer, @@ -51,28 +35,8 @@ bb: ret <8 x i1> %Shuff } -; CHECK: lCPI2_0: -; CHECK: .byte 2 ; 0x2 -; CHECK: .byte 255 ; 0xff -; CHECK: .byte 6 ; 0x6 -; CHECK: .byte 255 ; 0xff -; CHECK: .byte 10 ; 0xa -; CHECK: .byte 12 ; 0xc -; CHECK: .byte 14 ; 0xe -; CHECK: .byte 0 ; 0x0 -; CHECK: .byte 2 ; 0x2 -; CHECK: .byte 255 ; 0xff -; CHECK: .byte 6 ; 0x6 -; CHECK: .byte 255 ; 0xff -; CHECK: .byte 10 ; 0xa -; CHECK: .byte 12 ; 0xc -; CHECK: .byte 14 ; 0xe -; CHECK: .byte 0 ; 0x0 ; CHECK: test3 -; CHECK: adrp x[[REG3:[0-9]+]], lCPI2_0@PAGE -; CHECK: ldr q[[REG0:[0-9]+]], [x[[REG3]], lCPI2_0@PAGEOFF] -; CHECK: ldr q[[REG1:[0-9]+]], [x[[REG3]], lCPI2_1@PAGEOFF] -; CHECK: tbl.16b v{{[0-9]+}}, { v[[REG1]] }, v[[REG0]] +; CHECK: movi.4s v{{[0-9]+}}, #0x1 define <16 x i1> @test3(i1* %ptr, i32 %v) { bb: %Shuff = shufflevector <16 x i1> , <16 x i1> undef, @@ -81,29 +45,26 @@ bb: i32 14, i32 0> ret <16 x i1> %Shuff } -; CHECK: lCPI3_1: +; CHECK: lCPI3_0: +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 1 ; 0x1 -; CHECK: .byte 2 ; 0x2 -; CHECK: .byte 18 ; 0x12 -; CHECK: .byte 4 ; 0x4 -; CHECK: .byte 5 ; 0x5 -; CHECK: .byte 6 ; 0x6 -; CHECK: .byte 7 ; 0x7 -; CHECK: .byte 8 ; 0x8 -; CHECK: .byte 31 ; 0x1f -; CHECK: .byte 10 ; 0xa -; CHECK: .byte 30 ; 0x1e -; CHECK: .byte 12 ; 0xc -; CHECK: .byte 13 ; 0xd -; CHECK: .byte 14 ; 0xe -; CHECK: .byte 15 ; 0xf +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 +; CHECK: .byte 0 ; 0x0 ; CHECK: _test4: -; CHECK: ldr q[[REG1:[0-9]+]] -; CHECK: movi.2d v[[REG0:[0-9]+]], #0000000000000000 -; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_1@PAGE -; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_1@PAGEOFF] -; CHECK: tbl.16b v{{[0-9]+}}, { v[[REG0]], v[[REG1]] }, v[[REG2]] +; CHECK: adrp x[[REG3:[0-9]+]], lCPI3_0@PAGE +; CHECK: ldr q[[REG2:[0-9]+]], [x[[REG3]], lCPI3_0@PAGEOFF] define <16 x i1> @test4(i1* %ptr, i32 %v) { bb: %Shuff = shufflevector <16 x i1> zeroinitializer, diff --git a/test/CodeGen/AArch64/bitcast.ll b/test/CodeGen/AArch64/bitcast.ll new file mode 100644 index 0000000..e88ea9e --- /dev/null +++ b/test/CodeGen/AArch64/bitcast.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s + +; PR23065: SCALAR_TO_VECTOR implies the top elements 1 to N-1 of the N-element vector are undefined. + +define <4 x i16> @foo1(<2 x i32> %a) { +; CHECK-LABEL: foo1: +; CHECK: movi d0, #0000000000000000 +; CHECK-NEXT: ret + + %1 = shufflevector <2 x i32> , <2 x i32> %a, <2 x i32> +; Can't optimize the following bitcast to scalar_to_vector. + %2 = bitcast <2 x i32> %1 to <4 x i16> + %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <4 x i32> + ret <4 x i16> %3 +} + +define <4 x i16> @foo2(<2 x i32> %a) { +; CHECK-LABEL: foo2: +; CHECK: movi d0, #0000000000000000 +; CHECK-NEXT: ret + + %1 = shufflevector <2 x i32> , <2 x i32> %a, <2 x i32> +; Can't optimize the following bitcast to scalar_to_vector. + %2 = bitcast <2 x i32> %1 to <4 x i16> + %3 = shufflevector <4 x i16> %2, <4 x i16> undef, <4 x i32> + ret <4 x i16> %3 +} diff --git a/test/CodeGen/AArch64/br-to-eh-lpad.ll b/test/CodeGen/AArch64/br-to-eh-lpad.ll index e948b87..f304ba4 100644 --- a/test/CodeGen/AArch64/br-to-eh-lpad.ll +++ b/test/CodeGen/AArch64/br-to-eh-lpad.ll @@ -30,12 +30,12 @@ invoke.cont7: unreachable if.end50.thread: - tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 125) - tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 128) + tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 125) + tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 128) unreachable invoke.cont33: - tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 119) + tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 119) unreachable invoke.cont41: @@ -51,7 +51,7 @@ lpad40: br label %finally.catchall finally.catchall: - tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 125) + tail call void (i8*, ...) @printf(i8* getelementptr inbounds ([17 x i8], [17 x i8]* @.str1, i64 0, i64 0), i32 125) unreachable } diff --git a/test/CodeGen/AArch64/concat_vector-scalar-combine.ll b/test/CodeGen/AArch64/concat_vector-scalar-combine.ll new file mode 100644 index 0000000..1c64af6 --- /dev/null +++ b/test/CodeGen/AArch64/concat_vector-scalar-combine.ll @@ -0,0 +1,125 @@ +; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +; Test the (concat_vectors (bitcast (scalar)), ..) pattern. + +define <8 x i8> @test_concat_scalar_v2i8_to_v8i8_dup(i32 %x) #0 { +entry: +; CHECK-LABEL: test_concat_scalar_v2i8_to_v8i8_dup: +; CHECK-NEXT: dup.4h v0, w0 +; CHECK-NEXT: ret + %t = trunc i32 %x to i16 + %0 = bitcast i16 %t to <2 x i8> + %1 = shufflevector <2 x i8> %0, <2 x i8> undef, <8 x i32> + ret <8 x i8> %1 +} + +define <8 x i8> @test_concat_scalar_v4i8_to_v8i8_dup(i32 %x) #0 { +entry: +; CHECK-LABEL: test_concat_scalar_v4i8_to_v8i8_dup: +; CHECK-NEXT: dup.2s v0, w0 +; CHECK-NEXT: ret + %0 = bitcast i32 %x to <4 x i8> + %1 = shufflevector <4 x i8> %0, <4 x i8> undef, <8 x i32> + ret <8 x i8> %1 +} + +define <8 x i16> @test_concat_scalar_v2i16_to_v8i16_dup(i32 %x) #0 { +entry: +; CHECK-LABEL: test_concat_scalar_v2i16_to_v8i16_dup: +; CHECK-NEXT: dup.4s v0, w0 +; CHECK-NEXT: ret + %0 = bitcast i32 %x to <2 x i16> + %1 = shufflevector <2 x i16> %0, <2 x i16> undef, <8 x i32> + ret <8 x i16> %1 +} + +define <8 x i8> @test_concat_scalars_2x_v2i8_to_v8i8(i32 %x, i32 %y) #0 { +entry: +; CHECK-LABEL: test_concat_scalars_2x_v2i8_to_v8i8: +; CHECK-NEXT: ins.h v0[0], w0 +; CHECK-NEXT: ins.h v0[1], w1 +; CHECK-NEXT: ins.h v0[3], w1 +; CHECK-NEXT: ret + %tx = trunc i32 %x to i16 + %ty = trunc i32 %y to i16 + %bx = bitcast i16 %tx to <2 x i8> + %by = bitcast i16 %ty to <2 x i8> + %r = shufflevector <2 x i8> %bx, <2 x i8> %by, <8 x i32> + ret <8 x i8> %r +} + +define <8 x i8> @test_concat_scalars_2x_v4i8_to_v8i8_dup(i32 %x, i32 %y) #0 { +entry: +; CHECK-LABEL: test_concat_scalars_2x_v4i8_to_v8i8_dup: +; CHECK-NEXT: fmov s0, w1 +; CHECK-NEXT: ins.s v0[1], w0 +; CHECK-NEXT: ret + %bx = bitcast i32 %x to <4 x i8> + %by = bitcast i32 %y to <4 x i8> + %r = shufflevector <4 x i8> %bx, <4 x i8> %by, <8 x i32> + ret <8 x i8> %r +} + +define <8 x i16> @test_concat_scalars_2x_v2i16_to_v8i16_dup(i32 %x, i32 %y) #0 { +entry: +; CHECK-LABEL: test_concat_scalars_2x_v2i16_to_v8i16_dup: +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: ins.s v0[1], w1 +; CHECK-NEXT: ins.s v0[2], w1 +; CHECK-NEXT: ins.s v0[3], w0 +; CHECK-NEXT: ret + %bx = bitcast i32 %x to <2 x i16> + %by = bitcast i32 %y to <2 x i16> + %r = shufflevector <2 x i16> %bx, <2 x i16> %by, <8 x i32> + ret <8 x i16> %r +} + +; Also make sure we minimize bitcasts. + +; This is a pretty artificial testcase: make sure we bitcast to floating-point +; if any of the scalars is floating-point. +define <8 x i8> @test_concat_scalars_mixed_2x_v2i8_to_v8i8(float %dummy, i32 %x, half %y) #0 { +entry: +; CHECK-LABEL: test_concat_scalars_mixed_2x_v2i8_to_v8i8: +; CHECK-NEXT: fmov s[[X:[0-9]+]], w0 +; CHECK-NEXT: ins.h v0[0], v[[X]][0] +; CHECK-NEXT: ins.h v0[1], v1[0] +; CHECK-NEXT: ins.h v0[2], v[[X]][0] +; CHECK-NEXT: ins.h v0[3], v1[0] +; CHECK-NEXT: ret + %t = trunc i32 %x to i16 + %0 = bitcast i16 %t to <2 x i8> + %y0 = bitcast half %y to <2 x i8> + %1 = shufflevector <2 x i8> %0, <2 x i8> %y0, <8 x i32> + ret <8 x i8> %1 +} + +define <2 x float> @test_concat_scalars_fp_2x_v2i8_to_v8i8(float %dummy, half %x, half %y) #0 { +entry: +; CHECK-LABEL: test_concat_scalars_fp_2x_v2i8_to_v8i8: +; CHECK-NEXT: ins.h v0[0], v1[0] +; CHECK-NEXT: ins.h v0[1], v2[0] +; CHECK-NEXT: ins.h v0[2], v1[0] +; CHECK-NEXT: ins.h v0[3], v2[0] +; CHECK-NEXT: ret + %0 = bitcast half %x to <2 x i8> + %y0 = bitcast half %y to <2 x i8> + %1 = shufflevector <2 x i8> %0, <2 x i8> %y0, <8 x i32> + %2 = bitcast <8 x i8> %1 to <2 x float> + ret <2 x float> %2 +} + +define <4 x float> @test_concat_scalar_fp_v2i16_to_v16i8_dup(float %x) #0 { +entry: +; CHECK-LABEL: test_concat_scalar_fp_v2i16_to_v16i8_dup: +; CHECK-NEXT: dup.4s v0, v0[0] +; CHECK-NEXT: ret + %0 = bitcast float %x to <2 x i16> + %1 = shufflevector <2 x i16> %0, <2 x i16> undef, <8 x i32> + %2 = bitcast <8 x i16> %1 to <4 x float> + ret <4 x float> %2 +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/concat_vector-truncate-combine.ll b/test/CodeGen/AArch64/concat_vector-truncate-combine.ll index c510e27..ee52786 100644 --- a/test/CodeGen/AArch64/concat_vector-truncate-combine.ll +++ b/test/CodeGen/AArch64/concat_vector-truncate-combine.ll @@ -2,6 +2,8 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +; Test the (concat_vectors (trunc), (trunc)) pattern. + define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 { entry: ; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16: diff --git a/test/CodeGen/AArch64/concat_vector-truncated-scalar-combine.ll b/test/CodeGen/AArch64/concat_vector-truncated-scalar-combine.ll new file mode 100644 index 0000000..eb6c80d --- /dev/null +++ b/test/CodeGen/AArch64/concat_vector-truncated-scalar-combine.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple aarch64-unknown-unknown -asm-verbose=false | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +; Test the (concat_vectors (bitcast (trunc (scalar))), undef..) pattern. + +define <8 x i8> @test_concat_from_truncated_scalar(i32 %x) #0 { +entry: +; CHECK-LABEL: test_concat_from_truncated_scalar: +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: ret + %t = trunc i32 %x to i16 + %0 = bitcast i16 %t to <2 x i8> + %1 = shufflevector <2 x i8> %0, <2 x i8> undef, <8 x i32> + ret <8 x i8> %1 +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/dag-combine-invaraints.ll b/test/CodeGen/AArch64/dag-combine-invaraints.ll index 3614133..ac2d057 100644 --- a/test/CodeGen/AArch64/dag-combine-invaraints.ll +++ b/test/CodeGen/AArch64/dag-combine-invaraints.ll @@ -20,7 +20,7 @@ main_: %DHSelect = select i1 %tmp8, i32 %tmp9, i32 %tmp10 store i32 %DHSelect, i32* %i32X, align 4 %tmp15 = load i32, i32* %i32X, align 4 - %tmp17 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str2, i32 0, i32 0), i32 %tmp15) + %tmp17 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str2, i32 0, i32 0), i32 %tmp15) ret i32 0 ; CHECK: main: diff --git a/test/CodeGen/AArch64/f16-instructions.ll b/test/CodeGen/AArch64/f16-instructions.ll new file mode 100644 index 0000000..be5e2e5 --- /dev/null +++ b/test/CodeGen/AArch64/f16-instructions.ll @@ -0,0 +1,765 @@ +; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +; CHECK-LABEL: test_fadd: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fadd s0, s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_fadd(half %a, half %b) #0 { + %r = fadd half %a, %b + ret half %r +} + +; CHECK-LABEL: test_fsub: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fsub s0, s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_fsub(half %a, half %b) #0 { + %r = fsub half %a, %b + ret half %r +} + +; CHECK-LABEL: test_fmul: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fmul s0, s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_fmul(half %a, half %b) #0 { + %r = fmul half %a, %b + ret half %r +} + +; CHECK-LABEL: test_fdiv: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fdiv s0, s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_fdiv(half %a, half %b) #0 { + %r = fdiv half %a, %b + ret half %r +} + +; CHECK-LABEL: test_frem: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: bl {{_?}}fmodf +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_frem(half %a, half %b) #0 { + %r = frem half %a, %b + ret half %r +} + +; CHECK-LABEL: test_store: +; CHECK-NEXT: str h0, [x0] +; CHECK-NEXT: ret +define void @test_store(half %a, half* %b) #0 { + store half %a, half* %b + ret void +} + +; CHECK-LABEL: test_load: +; CHECK-NEXT: ldr h0, [x0] +; CHECK-NEXT: ret +define half @test_load(half* %a) #0 { + %r = load half, half* %a + ret half %r +} + + +declare half @test_callee(half %a, half %b) #0 + +; CHECK-LABEL: test_call: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: bl {{_?}}test_callee +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_call(half %a, half %b) #0 { + %r = call half @test_callee(half %a, half %b) + ret half %r +} + +; CHECK-LABEL: test_call_flipped: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: mov.16b v2, v0 +; CHECK-NEXT: mov.16b v0, v1 +; CHECK-NEXT: mov.16b v1, v2 +; CHECK-NEXT: bl {{_?}}test_callee +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_call_flipped(half %a, half %b) #0 { + %r = call half @test_callee(half %b, half %a) + ret half %r +} + +; CHECK-LABEL: test_tailcall_flipped: +; CHECK-NEXT: mov.16b v2, v0 +; CHECK-NEXT: mov.16b v0, v1 +; CHECK-NEXT: mov.16b v1, v2 +; CHECK-NEXT: b {{_?}}test_callee +define half @test_tailcall_flipped(half %a, half %b) #0 { + %r = tail call half @test_callee(half %b, half %a) + ret half %r +} + +; CHECK-LABEL: test_select: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: cmp w0, #0 +; CHECK-NEXT: fcsel s0, s0, s1, ne +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_select(half %a, half %b, i1 zeroext %c) #0 { + %r = select i1 %c, half %a, half %b + ret half %r +} + +; CHECK-LABEL: test_select_cc: +; CHECK-DAG: fcvt s3, h3 +; CHECK-DAG: fcvt s2, h2 +; CHECK-DAG: fcvt s1, h1 +; CHECK-DAG: fcvt s0, h0 +; CHECK-DAG: fcmp s2, s3 +; CHECK-DAG: cset [[CC:w[0-9]+]], ne +; CHECK-DAG: cmp [[CC]], #0 +; CHECK-NEXT: fcsel s0, s0, s1, ne +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_select_cc(half %a, half %b, half %c, half %d) #0 { + %cc = fcmp une half %c, %d + %r = select i1 %cc, half %a, half %b + ret half %r +} + +; CHECK-LABEL: test_fcmp_une: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, ne +; CHECK-NEXT: ret +define i1 @test_fcmp_une(half %a, half %b) #0 { + %r = fcmp une half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_ueq: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: orr [[TRUE:w[0-9]+]], wzr, #0x1 +; CHECK-NEXT: csel [[CC:w[0-9]+]], [[TRUE]], wzr, eq +; CHECK-NEXT: csel w0, [[TRUE]], [[CC]], vs +; CHECK-NEXT: ret +define i1 @test_fcmp_ueq(half %a, half %b) #0 { + %r = fcmp ueq half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_ugt: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, hi +; CHECK-NEXT: ret +define i1 @test_fcmp_ugt(half %a, half %b) #0 { + %r = fcmp ugt half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_uge: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, pl +; CHECK-NEXT: ret +define i1 @test_fcmp_uge(half %a, half %b) #0 { + %r = fcmp uge half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_ult: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, lt +; CHECK-NEXT: ret +define i1 @test_fcmp_ult(half %a, half %b) #0 { + %r = fcmp ult half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_ule: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, le +; CHECK-NEXT: ret +define i1 @test_fcmp_ule(half %a, half %b) #0 { + %r = fcmp ule half %a, %b + ret i1 %r +} + + +; CHECK-LABEL: test_fcmp_uno: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, vs +; CHECK-NEXT: ret +define i1 @test_fcmp_uno(half %a, half %b) #0 { + %r = fcmp uno half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_one: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: orr [[TRUE:w[0-9]+]], wzr, #0x1 +; CHECK-NEXT: csel [[CC:w[0-9]+]], [[TRUE]], wzr, mi +; CHECK-NEXT: csel w0, [[TRUE]], [[CC]], gt +; CHECK-NEXT: ret +define i1 @test_fcmp_one(half %a, half %b) #0 { + %r = fcmp one half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_oeq: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: ret +define i1 @test_fcmp_oeq(half %a, half %b) #0 { + %r = fcmp oeq half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_ogt: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, gt +; CHECK-NEXT: ret +define i1 @test_fcmp_ogt(half %a, half %b) #0 { + %r = fcmp ogt half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_oge: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, ge +; CHECK-NEXT: ret +define i1 @test_fcmp_oge(half %a, half %b) #0 { + %r = fcmp oge half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_olt: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, mi +; CHECK-NEXT: ret +define i1 @test_fcmp_olt(half %a, half %b) #0 { + %r = fcmp olt half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_ole: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, ls +; CHECK-NEXT: ret +define i1 @test_fcmp_ole(half %a, half %b) #0 { + %r = fcmp ole half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_fcmp_ord: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: cset w0, vc +; CHECK-NEXT: ret +define i1 @test_fcmp_ord(half %a, half %b) #0 { + %r = fcmp ord half %a, %b + ret i1 %r +} + +; CHECK-LABEL: test_br_cc: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcmp s0, s1 +; CHECK-NEXT: b.mi [[BRCC_ELSE:.?LBB[0-9_]+]] +; CHECK-NEXT: str wzr, [x0] +; CHECK-NEXT: ret +; CHECK-NEXT: [[BRCC_ELSE]]: +; CHECK-NEXT: str wzr, [x1] +; CHECK-NEXT: ret +define void @test_br_cc(half %a, half %b, i32* %p1, i32* %p2) #0 { + %c = fcmp uge half %a, %b + br i1 %c, label %then, label %else +then: + store i32 0, i32* %p1 + ret void +else: + store i32 0, i32* %p2 + ret void +} + +; CHECK-LABEL: test_phi: +; CHECK: mov x[[PTR:[0-9]+]], x0 +; CHECK: ldr h[[AB:[0-9]+]], [x[[PTR]]] +; CHECK: [[LOOP:LBB[0-9_]+]]: +; CHECK: mov.16b v[[R:[0-9]+]], v[[AB]] +; CHECK: ldr h[[AB]], [x[[PTR]]] +; CHECK: mov x0, x[[PTR]] +; CHECK: bl {{_?}}test_dummy +; CHECK: mov.16b v0, v[[R]] +; CHECK: ret +define half @test_phi(half* %p1) #0 { +entry: + %a = load half, half* %p1 + br label %loop +loop: + %r = phi half [%a, %entry], [%b, %loop] + %b = load half, half* %p1 + %c = call i1 @test_dummy(half* %p1) + br i1 %c, label %loop, label %return +return: + ret half %r +} +declare i1 @test_dummy(half* %p1) #0 + +; CHECK-LABEL: test_fptosi_i32: +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvtzs w0, s0 +; CHECK-NEXT: ret +define i32 @test_fptosi_i32(half %a) #0 { + %r = fptosi half %a to i32 + ret i32 %r +} + +; CHECK-LABEL: test_fptosi_i64: +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvtzs x0, s0 +; CHECK-NEXT: ret +define i64 @test_fptosi_i64(half %a) #0 { + %r = fptosi half %a to i64 + ret i64 %r +} + +; CHECK-LABEL: test_fptoui_i32: +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvtzu w0, s0 +; CHECK-NEXT: ret +define i32 @test_fptoui_i32(half %a) #0 { + %r = fptoui half %a to i32 + ret i32 %r +} + +; CHECK-LABEL: test_fptoui_i64: +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvtzu x0, s0 +; CHECK-NEXT: ret +define i64 @test_fptoui_i64(half %a) #0 { + %r = fptoui half %a to i64 + ret i64 %r +} + +; CHECK-LABEL: test_uitofp_i32: +; CHECK-NEXT: ucvtf s0, w0 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_uitofp_i32(i32 %a) #0 { + %r = uitofp i32 %a to half + ret half %r +} + +; CHECK-LABEL: test_uitofp_i64: +; CHECK-NEXT: ucvtf s0, x0 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_uitofp_i64(i64 %a) #0 { + %r = uitofp i64 %a to half + ret half %r +} + +; CHECK-LABEL: test_sitofp_i32: +; CHECK-NEXT: scvtf s0, w0 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_sitofp_i32(i32 %a) #0 { + %r = sitofp i32 %a to half + ret half %r +} + +; CHECK-LABEL: test_sitofp_i64: +; CHECK-NEXT: scvtf s0, x0 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_sitofp_i64(i64 %a) #0 { + %r = sitofp i64 %a to half + ret half %r +} + +; CHECK-LABEL: test_fptrunc_float: +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret + +define half @test_fptrunc_float(float %a) #0 { + %r = fptrunc float %a to half + ret half %r +} + +; CHECK-LABEL: test_fptrunc_double: +; CHECK-NEXT: fcvt h0, d0 +; CHECK-NEXT: ret +define half @test_fptrunc_double(double %a) #0 { + %r = fptrunc double %a to half + ret half %r +} + +; CHECK-LABEL: test_fpext_float: +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: ret +define float @test_fpext_float(half %a) #0 { + %r = fpext half %a to float + ret float %r +} + +; CHECK-LABEL: test_fpext_double: +; CHECK-NEXT: fcvt d0, h0 +; CHECK-NEXT: ret +define double @test_fpext_double(half %a) #0 { + %r = fpext half %a to double + ret double %r +} + + +; CHECK-LABEL: test_bitcast_halftoi16: +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret +define i16 @test_bitcast_halftoi16(half %a) #0 { + %r = bitcast half %a to i16 + ret i16 %r +} + +; CHECK-LABEL: test_bitcast_i16tohalf: +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: ret +define half @test_bitcast_i16tohalf(i16 %a) #0 { + %r = bitcast i16 %a to half + ret half %r +} + + +declare half @llvm.sqrt.f16(half %a) #0 +declare half @llvm.powi.f16(half %a, i32 %b) #0 +declare half @llvm.sin.f16(half %a) #0 +declare half @llvm.cos.f16(half %a) #0 +declare half @llvm.pow.f16(half %a, half %b) #0 +declare half @llvm.exp.f16(half %a) #0 +declare half @llvm.exp2.f16(half %a) #0 +declare half @llvm.log.f16(half %a) #0 +declare half @llvm.log10.f16(half %a) #0 +declare half @llvm.log2.f16(half %a) #0 +declare half @llvm.fma.f16(half %a, half %b, half %c) #0 +declare half @llvm.fabs.f16(half %a) #0 +declare half @llvm.minnum.f16(half %a, half %b) #0 +declare half @llvm.maxnum.f16(half %a, half %b) #0 +declare half @llvm.copysign.f16(half %a, half %b) #0 +declare half @llvm.floor.f16(half %a) #0 +declare half @llvm.ceil.f16(half %a) #0 +declare half @llvm.trunc.f16(half %a) #0 +declare half @llvm.rint.f16(half %a) #0 +declare half @llvm.nearbyint.f16(half %a) #0 +declare half @llvm.round.f16(half %a) #0 +declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0 + +; CHECK-LABEL: test_sqrt: +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fsqrt s0, s0 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_sqrt(half %a) #0 { + %r = call half @llvm.sqrt.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_powi: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: bl {{_?}}__powisf2 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_powi(half %a, i32 %b) #0 { + %r = call half @llvm.powi.f16(half %a, i32 %b) + ret half %r +} + +; CHECK-LABEL: test_sin: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: bl {{_?}}sinf +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_sin(half %a) #0 { + %r = call half @llvm.sin.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_cos: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: bl {{_?}}cosf +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_cos(half %a) #0 { + %r = call half @llvm.cos.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_pow: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: bl {{_?}}powf +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_pow(half %a, half %b) #0 { + %r = call half @llvm.pow.f16(half %a, half %b) + ret half %r +} + +; CHECK-LABEL: test_exp: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: bl {{_?}}expf +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_exp(half %a) #0 { + %r = call half @llvm.exp.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_exp2: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: bl {{_?}}exp2f +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_exp2(half %a) #0 { + %r = call half @llvm.exp2.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_log: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: bl {{_?}}logf +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_log(half %a) #0 { + %r = call half @llvm.log.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_log10: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: bl {{_?}}log10f +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_log10(half %a) #0 { + %r = call half @llvm.log10.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_log2: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: bl {{_?}}log2f +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_log2(half %a) #0 { + %r = call half @llvm.log2.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_fma: +; CHECK-NEXT: fcvt s2, h2 +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fmadd s0, s0, s1, s2 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_fma(half %a, half %b, half %c) #0 { + %r = call half @llvm.fma.f16(half %a, half %b, half %c) + ret half %r +} + +; CHECK-LABEL: test_fabs: +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fabs s0, s0 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_fabs(half %a) #0 { + %r = call half @llvm.fabs.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_minnum: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: bl {{_?}}fminf +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_minnum(half %a, half %b) #0 { + %r = call half @llvm.minnum.f16(half %a, half %b) + ret half %r +} + +; CHECK-LABEL: test_maxnum: +; CHECK-NEXT: stp x29, x30, [sp, #-16]! +; CHECK-NEXT: mov x29, sp +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: bl {{_?}}fmaxf +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ret +define half @test_maxnum(half %a, half %b) #0 { + %r = call half @llvm.maxnum.f16(half %a, half %b) + ret half %r +} + +; CHECK-LABEL: test_copysign: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: movi.4s v2, #0x80, lsl #24 +; CHECK-NEXT: bit.16b v0, v1, v2 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_copysign(half %a, half %b) #0 { + %r = call half @llvm.copysign.f16(half %a, half %b) + ret half %r +} + +; CHECK-LABEL: test_floor: +; CHECK-NEXT: fcvt s1, h0 +; CHECK-NEXT: frintm s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: frintx s1, s1 +; CHECK-NEXT: ret +define half @test_floor(half %a) #0 { + %r = call half @llvm.floor.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_ceil: +; CHECK-NEXT: fcvt s1, h0 +; CHECK-NEXT: frintp s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: frintx s1, s1 +; CHECK-NEXT: ret +define half @test_ceil(half %a) #0 { + %r = call half @llvm.ceil.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_trunc: +; CHECK-NEXT: fcvt s1, h0 +; CHECK-NEXT: frintz s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: frintx s1, s1 +; CHECK-NEXT: ret +define half @test_trunc(half %a) #0 { + %r = call half @llvm.trunc.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_rint: +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: frintx s0, s0 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_rint(half %a) #0 { + %r = call half @llvm.rint.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_nearbyint: +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: frinti s0, s0 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_nearbyint(half %a) #0 { + %r = call half @llvm.nearbyint.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_round: +; CHECK-NEXT: fcvt s1, h0 +; CHECK-NEXT: frinta s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: frintx s1, s1 +; CHECK-NEXT: ret +define half @test_round(half %a) #0 { + %r = call half @llvm.round.f16(half %a) + ret half %r +} + +; CHECK-LABEL: test_fmuladd: +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fmul s0, s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvt s1, h2 +; CHECK-NEXT: fadd s0, s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_fmuladd(half %a, half %b, half %c) #0 { + %r = call half @llvm.fmuladd.f16(half %a, half %b, half %c) + ret half %r +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/fast-isel-int-ext5.ll b/test/CodeGen/AArch64/fast-isel-int-ext5.ll new file mode 100644 index 0000000..0f9ec62 --- /dev/null +++ b/test/CodeGen/AArch64/fast-isel-int-ext5.ll @@ -0,0 +1,19 @@ +; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s + +; CHECK-LABEL: int_ext_opt +define i64 @int_ext_opt(i8* %addr, i1 %c1, i1 %c2) { +entry: + %0 = load i8, i8* %addr + br i1 %c1, label %bb1, label %bb2 + +bb1: + %1 = zext i8 %0 to i64 + br i1 %c2, label %bb2, label %exit + +bb2: + %2 = phi i64 [1, %entry], [%1, %bb1] + ret i64 %2 + +exit: + ret i64 0 +} diff --git a/test/CodeGen/AArch64/fold-constants.ll b/test/CodeGen/AArch64/fold-constants.ll new file mode 100644 index 0000000..2dd0d12 --- /dev/null +++ b/test/CodeGen/AArch64/fold-constants.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s + +define i64 @dotests_616() { +; CHECK-LABEL: dotests_616 +; CHECK: movi d0, #0000000000000000 +; CHECK-NEXT: umov w8, v0.b[2] +; CHECK-NEXT: sbfx w8, w8, #0, #1 +; CHECK-NEXT: fmov s0, w8 +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret +entry: + %0 = bitcast <2 x i64> zeroinitializer to <8 x i16> + %1 = and <8 x i16> zeroinitializer, %0 + %2 = icmp ne <8 x i16> %1, zeroinitializer + %3 = extractelement <8 x i1> %2, i32 2 + %vgetq_lane285 = sext i1 %3 to i16 + %vset_lane = insertelement <4 x i16> undef, i16 %vgetq_lane285, i32 0 + %4 = bitcast <4 x i16> %vset_lane to <1 x i64> + %vget_lane = extractelement <1 x i64> %4, i32 0 + ret i64 %vget_lane +} diff --git a/test/CodeGen/AArch64/fp16-instructions.ll b/test/CodeGen/AArch64/fp16-instructions.ll deleted file mode 100644 index ba96694..0000000 --- a/test/CodeGen/AArch64/fp16-instructions.ll +++ /dev/null @@ -1,109 +0,0 @@ -; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s - -define half @add_h(half %a, half %b) { -entry: -; CHECK-LABEL: add_h: -; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0 -; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1 -; CHECK: fadd [[RES:s[0-9]+]], [[OP1]], [[OP2]] -; CHECK: fcvt h0, [[RES]] - %0 = fadd half %a, %b - ret half %0 -} - - -define half @sub_h(half %a, half %b) { -entry: -; CHECK-LABEL: sub_h: -; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0 -; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1 -; CHECK: fsub [[RES:s[0-9]+]], [[OP1]], [[OP2]] -; CHECK: fcvt h0, [[RES]] - %0 = fsub half %a, %b - ret half %0 -} - - -define half @mul_h(half %a, half %b) { -entry: -; CHECK-LABEL: mul_h: -; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0 -; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1 -; CHECK: fmul [[RES:s[0-9]+]], [[OP1]], [[OP2]] -; CHECK: fcvt h0, [[RES]] - %0 = fmul half %a, %b - ret half %0 -} - - -define half @div_h(half %a, half %b) { -entry: -; CHECK-LABEL: div_h: -; CHECK-DAG: fcvt [[OP1:s[0-9]+]], h0 -; CHECK-DAG: fcvt [[OP2:s[0-9]+]], h1 -; CHECK: fdiv [[RES:s[0-9]+]], [[OP1]], [[OP2]] -; CHECK: fcvt h0, [[RES]] - %0 = fdiv half %a, %b - ret half %0 -} - - -define half @load_h(half* %a) { -entry: -; CHECK-LABEL: load_h: -; CHECK: ldr h0, [x0] - %0 = load half, half* %a, align 4 - ret half %0 -} - - -define void @store_h(half* %a, half %b) { -entry: -; CHECK-LABEL: store_h: -; CHECK: str h0, [x0] - store half %b, half* %a, align 4 - ret void -} - -define half @s_to_h(float %a) { -; CHECK-LABEL: s_to_h: -; CHECK: fcvt h0, s0 - %1 = fptrunc float %a to half - ret half %1 -} - -define half @d_to_h(double %a) { -; CHECK-LABEL: d_to_h: -; CHECK: fcvt h0, d0 - %1 = fptrunc double %a to half - ret half %1 -} - -define float @h_to_s(half %a) { -; CHECK-LABEL: h_to_s: -; CHECK: fcvt s0, h0 - %1 = fpext half %a to float - ret float %1 -} - -define double @h_to_d(half %a) { -; CHECK-LABEL: h_to_d: -; CHECK: fcvt d0, h0 - %1 = fpext half %a to double - ret double %1 -} - -define half @bitcast_i_to_h(i16 %a) { -; CHECK-LABEL: bitcast_i_to_h: -; CHECK: fmov s0, w0 - %1 = bitcast i16 %a to half - ret half %1 -} - - -define i16 @bitcast_h_to_i(half %a) { -; CHECK-LABEL: bitcast_h_to_i: -; CHECK: fmov w0, s0 - %1 = bitcast half %a to i16 - ret i16 %1 -} diff --git a/test/CodeGen/AArch64/global-merge-1.ll b/test/CodeGen/AArch64/global-merge-1.ll index b404389..14b0430 100644 --- a/test/CodeGen/AArch64/global-merge-1.ll +++ b/test/CodeGen/AArch64/global-merge-1.ll @@ -1,11 +1,11 @@ -; RUN: llc %s -mtriple=aarch64-none-linux-gnu -O3 -enable-global-merge -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-none-linux-gnu -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-apple-ios -O3 -enable-global-merge -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS -; RUN: llc %s -mtriple=aarch64-apple-ios -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS +; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS +; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS @m = internal global i32 0, align 4 @n = internal global i32 0, align 4 diff --git a/test/CodeGen/AArch64/global-merge-2.ll b/test/CodeGen/AArch64/global-merge-2.ll index d5967b9..af68403 100644 --- a/test/CodeGen/AArch64/global-merge-2.ll +++ b/test/CodeGen/AArch64/global-merge-2.ll @@ -1,6 +1,6 @@ -; RUN: llc %s -mtriple=aarch64-none-linux-gnu -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-apple-ios -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS +; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS @x = global i32 0, align 4 @y = global i32 0, align 4 diff --git a/test/CodeGen/AArch64/global-merge-3.ll b/test/CodeGen/AArch64/global-merge-3.ll index 15035c0..9251083 100644 --- a/test/CodeGen/AArch64/global-merge-3.ll +++ b/test/CodeGen/AArch64/global-merge-3.ll @@ -1,6 +1,6 @@ -; RUN: llc %s -mtriple=aarch64-none-linux-gnu -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s -; RUN: llc %s -mtriple=aarch64-apple-ios -O3 -enable-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS +; RUN: llc %s -mtriple=aarch64-none-linux-gnu -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-apple-ios -aarch64-global-merge -global-merge-on-external -o - | FileCheck %s --check-prefix=CHECK-APPLE-IOS @x = global [1000 x i32] zeroinitializer, align 1 @y = global [1000 x i32] zeroinitializer, align 1 diff --git a/test/CodeGen/AArch64/global-merge-4.ll b/test/CodeGen/AArch64/global-merge-4.ll index 8fb7747..bc6b68a 100644 --- a/test/CodeGen/AArch64/global-merge-4.ll +++ b/test/CodeGen/AArch64/global-merge-4.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -mtriple=aarch64-linux-gnuabi -O3 -enable-global-merge -o - | FileCheck %s +; RUN: llc %s -mtriple=aarch64-linux-gnuabi -aarch64-global-merge -o - | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64-S128" target triple = "arm64-apple-ios7.0.0" diff --git a/test/CodeGen/AArch64/merge-store.ll b/test/CodeGen/AArch64/merge-store.ll new file mode 100644 index 0000000..18dbad4 --- /dev/null +++ b/test/CodeGen/AArch64/merge-store.ll @@ -0,0 +1,20 @@ +; RUN: llc -march aarch64 %s -o - | FileCheck %s + +@g0 = external global <3 x float>, align 16 +@g1 = external global <3 x float>, align 4 + +; CHECK: ldr s[[R0:[0-9]+]], {{\[}}[[R1:x[0-9]+]]{{\]}}, #4 +; CHECK: ld1{{\.?s?}} { v[[R0]]{{\.?s?}} }[1], {{\[}}[[R1]]{{\]}} +; CHECK: str d[[R0]] + +define void @blam() { + %tmp4 = getelementptr inbounds <3 x float>, <3 x float>* @g1, i64 0, i64 0 + %tmp5 = load <3 x float>, <3 x float>* @g0, align 16 + %tmp6 = extractelement <3 x float> %tmp5, i64 0 + store float %tmp6, float* %tmp4 + %tmp7 = getelementptr inbounds float, float* %tmp4, i64 1 + %tmp8 = load <3 x float>, <3 x float>* @g0, align 16 + %tmp9 = extractelement <3 x float> %tmp8, i64 1 + store float %tmp9, float* %tmp7 + ret void; +} diff --git a/test/CodeGen/AArch64/print-mrs-system-register.ll b/test/CodeGen/AArch64/print-mrs-system-register.ll new file mode 100644 index 0000000..3411ed6 --- /dev/null +++ b/test/CodeGen/AArch64/print-mrs-system-register.ll @@ -0,0 +1,11 @@ +; RUN: llc -mtriple=arm64-apple-darwin %s -o - | FileCheck %s + +; CHECK: mrs x0, CPM_IOACC_CTL_EL3 + +define void @foo1() #0 { +entry: + tail call void asm sideeffect "mrs x0, cpm_ioacc_ctl_el3", ""() + ret void +} + +attributes #0 = { "target-cpu"="cyclone" } diff --git a/test/CodeGen/AArch64/sibling-call.ll b/test/CodeGen/AArch64/sibling-call.ll index 34d45d8..a68fdec 100644 --- a/test/CodeGen/AArch64/sibling-call.ll +++ b/test/CodeGen/AArch64/sibling-call.ll @@ -75,8 +75,8 @@ define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) { ; CHECK: ldr [[VAL0:x[0-9]+]], ; CHECK: ldr [[VAL1:x[0-9]+]], -; CHECK: str [[VAL1]], ; CHECK: str [[VAL0]], +; CHECK: str [[VAL1]], ; CHECK-NOT: add sp, sp, ; CHECK: b callee_stack16 diff --git a/test/CodeGen/AArch64/stackmap-liveness.ll b/test/CodeGen/AArch64/stackmap-liveness.ll new file mode 100644 index 0000000..6b37aac --- /dev/null +++ b/test/CodeGen/AArch64/stackmap-liveness.ll @@ -0,0 +1,47 @@ +; RUN: llc < %s -mtriple=aarch64-apple-darwin | FileCheck %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +; CHECK-LABEL: .section __LLVM_STACKMAPS,__llvm_stackmaps +; CHECK-NEXT: __LLVM_StackMaps: +; Header +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 0 +; Num Functions +; CHECK-NEXT: .long 1 +; Num LargeConstants +; CHECK-NEXT: .long 0 +; Num Callsites +; CHECK-NEXT: .long 1 + +; Functions and stack size +; CHECK-NEXT: .quad _stackmap_liveness +; CHECK-NEXT: .quad 16 + +; Test that the return register is recognized as an live-out. +define i64 @stackmap_liveness(i1 %c) { +; CHECK-LABEL: .long L{{.*}}-_stackmap_liveness +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; Padding +; CHECK-NEXT: .short 0 +; Num LiveOut Entries: 1 +; CHECK-NEXT: .short 2 +; LiveOut Entry 0: X0 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; LiveOut Entry 1: SP +; CHECK-NEXT: .short 31 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; Align +; CHECK-NEXT: .align 3 + %1 = select i1 %c, i64 1, i64 2 + call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 32, i8* null, i32 0) + ret i64 %1 +} + +declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) + diff --git a/test/CodeGen/AArch64/tailcall-explicit-sret.ll b/test/CodeGen/AArch64/tailcall-explicit-sret.ll new file mode 100644 index 0000000..4d80f2a --- /dev/null +++ b/test/CodeGen/AArch64/tailcall-explicit-sret.ll @@ -0,0 +1,106 @@ +; RUN: llc < %s -mtriple arm64-apple-darwin -aarch64-load-store-opt=false -asm-verbose=false | FileCheck %s +; Disable the load/store optimizer to avoid having LDP/STPs and simplify checks. + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +; Check that we don't try to tail-call with a non-forwarded sret parameter. +declare void @test_explicit_sret(i1024* sret) #0 + +; This is the only OK case, where we forward the explicit sret pointer. + +; CHECK-LABEL: _test_tailcall_explicit_sret: +; CHECK-NEXT: b _test_explicit_sret +define void @test_tailcall_explicit_sret(i1024* sret %arg) #0 { + tail call void @test_explicit_sret(i1024* %arg) + ret void +} + +; CHECK-LABEL: _test_call_explicit_sret: +; CHECK-NOT: mov x8 +; CHECK: bl _test_explicit_sret +; CHECK: ret +define void @test_call_explicit_sret(i1024* sret %arg) #0 { + call void @test_explicit_sret(i1024* %arg) + ret void +} + +; CHECK-LABEL: _test_tailcall_explicit_sret_alloca_unused: +; CHECK: mov x8, sp +; CHECK-NEXT: bl _test_explicit_sret +; CHECK: ret +define void @test_tailcall_explicit_sret_alloca_unused() #0 { + %l = alloca i1024, align 8 + tail call void @test_explicit_sret(i1024* %l) + ret void +} + +; CHECK-LABEL: _test_tailcall_explicit_sret_alloca_dummyusers: +; CHECK: ldr [[PTRLOAD1:x[0-9]+]], [x0] +; CHECK: str [[PTRLOAD1]], [sp] +; CHECK: mov x8, sp +; CHECK-NEXT: bl _test_explicit_sret +; CHECK: ret +define void @test_tailcall_explicit_sret_alloca_dummyusers(i1024* %ptr) #0 { + %l = alloca i1024, align 8 + %r = load i1024, i1024* %ptr, align 8 + store i1024 %r, i1024* %l, align 8 + tail call void @test_explicit_sret(i1024* %l) + ret void +} + +; This is too conservative, but doesn't really happen in practice. + +; CHECK-LABEL: _test_tailcall_explicit_sret_gep: +; CHECK: add x8, x0, #128 +; CHECK-NEXT: bl _test_explicit_sret +; CHECK: ret +define void @test_tailcall_explicit_sret_gep(i1024* %ptr) #0 { + %ptr2 = getelementptr i1024, i1024* %ptr, i32 1 + tail call void @test_explicit_sret(i1024* %ptr2) + ret void +} + +; CHECK-LABEL: _test_tailcall_explicit_sret_alloca_returned: +; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 +; CHECK: mov x8, sp +; CHECK-NEXT: bl _test_explicit_sret +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK: ret +define i1024 @test_tailcall_explicit_sret_alloca_returned() #0 { + %l = alloca i1024, align 8 + tail call void @test_explicit_sret(i1024* %l) + %r = load i1024, i1024* %l, align 8 + ret i1024 %r +} + +; CHECK-LABEL: _test_indirect_tailcall_explicit_sret_nosret_arg: +; CHECK-DAG: mov x[[CALLERX8NUM:[0-9]+]], x8 +; CHECK-DAG: mov [[FPTR:x[0-9]+]], x0 +; CHECK: mov x0, sp +; CHECK-NEXT: blr [[FPTR]] +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK: ret +define void @test_indirect_tailcall_explicit_sret_nosret_arg(i1024* sret %arg, void (i1024*)* %f) #0 { + %l = alloca i1024, align 8 + tail call void %f(i1024* %l) + %r = load i1024, i1024* %l, align 8 + store i1024 %r, i1024* %arg, align 8 + ret void +} + +; CHECK-LABEL: _test_indirect_tailcall_explicit_sret_: +; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 +; CHECK: mov x8, sp +; CHECK-NEXT: blr x0 +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK: ret +define void @test_indirect_tailcall_explicit_sret_(i1024* sret %arg, i1024 ()* %f) #0 { + %ret = tail call i1024 %f() + store i1024 %ret, i1024* %arg, align 8 + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/tailcall-implicit-sret.ll b/test/CodeGen/AArch64/tailcall-implicit-sret.ll new file mode 100644 index 0000000..5d68059 --- /dev/null +++ b/test/CodeGen/AArch64/tailcall-implicit-sret.ll @@ -0,0 +1,46 @@ +; RUN: llc < %s -mtriple arm64-apple-darwin -aarch64-load-store-opt=false -asm-verbose=false | FileCheck %s +; Disable the load/store optimizer to avoid having LDP/STPs and simplify checks. + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +; Check that we don't try to tail-call with an sret-demoted return. + +declare i1024 @test_sret() #0 + +; CHECK-LABEL: _test_call_sret: +; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 +; CHECK: mov x8, sp +; CHECK-NEXT: bl _test_sret +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK: ret +define i1024 @test_call_sret() #0 { + %a = call i1024 @test_sret() + ret i1024 %a +} + +; CHECK-LABEL: _test_tailcall_sret: +; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 +; CHECK: mov x8, sp +; CHECK-NEXT: bl _test_sret +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK: ret +define i1024 @test_tailcall_sret() #0 { + %a = tail call i1024 @test_sret() + ret i1024 %a +} + +; CHECK-LABEL: _test_indirect_tailcall_sret: +; CHECK: mov x[[CALLERX8NUM:[0-9]+]], x8 +; CHECK: mov x8, sp +; CHECK-NEXT: blr x0 +; CHECK-NEXT: ldr [[CALLERSRET1:x[0-9]+]], [sp] +; CHECK: str [[CALLERSRET1:x[0-9]+]], [x[[CALLERX8NUM]]] +; CHECK: ret +define i1024 @test_indirect_tailcall_sret(i1024 ()* %f) #0 { + %a = tail call i1024 %f() + ret i1024 %a +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/tailcall-mem-intrinsics.ll b/test/CodeGen/AArch64/tailcall-mem-intrinsics.ll new file mode 100644 index 0000000..b970fb1 --- /dev/null +++ b/test/CodeGen/AArch64/tailcall-mem-intrinsics.ll @@ -0,0 +1,31 @@ +; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s + +; CHECK-LABEL: tail_memcpy: +; CHECK: b memcpy +define void @tail_memcpy(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 { +entry: + tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false) + ret void +} + +; CHECK-LABEL: tail_memmove: +; CHECK: b memmove +define void @tail_memmove(i8* nocapture %p, i8* nocapture readonly %q, i32 %n) #0 { +entry: + tail call void @llvm.memmove.p0i8.p0i8.i32(i8* %p, i8* %q, i32 %n, i32 1, i1 false) + ret void +} + +; CHECK-LABEL: tail_memset: +; CHECK: b memset +define void @tail_memset(i8* nocapture %p, i8 %c, i32 %n) #0 { +entry: + tail call void @llvm.memset.p0i8.i32(i8* %p, i8 %c, i32 %n, i32 1, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0 +declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #0 +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/vcvt-oversize.ll b/test/CodeGen/AArch64/vcvt-oversize.ll new file mode 100644 index 0000000..066a4b6 --- /dev/null +++ b/test/CodeGen/AArch64/vcvt-oversize.ll @@ -0,0 +1,16 @@ +; RUN: llc -mtriple=aarch64 < %s | FileCheck %s + +define <8 x i8> @float_to_i8(<8 x float>* %in) { +; CHECK-LABEL: float_to_i8: +; CHECK-DAG: fadd v[[LSB:[0-9]+]].4s, v0.4s, v0.4s +; CHECK-DAG: fadd v[[MSB:[0-9]+]].4s, v1.4s, v1.4s +; CHECK-DAG: fcvtzu v[[LSB2:[0-9]+]].4s, v[[LSB]].4s +; CHECK-DAG: fcvtzu v[[MSB2:[0-9]+]].4s, v[[MSB]].4s +; CHECK-DAG: xtn v[[TMP:[0-9]+]].4h, v[[LSB]].4s +; CHECK-DAG: xtn2 v[[TMP]].8h, v[[MSB]].4s +; CHECK-DAG: xtn v0.8b, v[[TMP]].8h + %l = load <8 x float>, <8 x float>* %in + %scale = fmul <8 x float> %l, + %conv = fptoui <8 x float> %scale to <8 x i8> + ret <8 x i8> %conv +} diff --git a/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll b/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll index 0162d7f..7c42596 100644 --- a/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll +++ b/test/CodeGen/ARM/2007-03-21-JoinIntervalsCrash.ll @@ -83,7 +83,7 @@ cond_next881: ; preds = %bb866 %tmp884885 = inttoptr i64 %tmp10959 to %struct.tree_identifier* ; <%struct.tree_identifier*> [#uses=1] %tmp887 = getelementptr %struct.tree_identifier, %struct.tree_identifier* %tmp884885, i32 0, i32 1, i32 0 ; [#uses=1] %tmp888 = load i8*, i8** %tmp887 ; [#uses=1] - tail call void (i32, ...)* @error( i32 undef, i8* %tmp888 ) + tail call void (i32, ...) @error( i32 undef, i8* %tmp888 ) ret void cond_true918: ; preds = %cond_false841 diff --git a/test/CodeGen/ARM/2007-04-03-PEIBug.ll b/test/CodeGen/ARM/2007-04-03-PEIBug.ll index cf5094f..87863bd 100644 --- a/test/CodeGen/ARM/2007-04-03-PEIBug.ll +++ b/test/CodeGen/ARM/2007-04-03-PEIBug.ll @@ -5,7 +5,7 @@ entry: %A = alloca [1123 x i32], align 16 ; <[1123 x i32]*> [#uses=1] %B = alloca [3123 x i32], align 16 ; <[3123 x i32]*> [#uses=1] %C = alloca [12312 x i32], align 16 ; <[12312 x i32]*> [#uses=1] - %tmp = call i32 (...)* @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C ) ; [#uses=0] + %tmp = call i32 (...) @bar( [3123 x i32]* %B, [1123 x i32]* %A, [12312 x i32]* %C ) ; [#uses=0] ret i32 undef } diff --git a/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll b/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll index b687029..11f3003 100644 --- a/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll +++ b/test/CodeGen/ARM/2007-04-03-UndefinedSymbol.ll @@ -10,7 +10,7 @@ define internal void @_ZN1B1iEv(%struct.B* %this) { entry: %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0 ; [#uses=1] %tmp2 = load i32, i32* %tmp1 ; [#uses=1] - %tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8], [7 x i8]* @str, i32 0, i32 0), i32 %tmp2 ) ; [#uses=0] + %tmp4 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([7 x i8], [7 x i8]* @str, i32 0, i32 0), i32 %tmp2 ) ; [#uses=0] ret void } @@ -20,7 +20,7 @@ define internal void @_ZN1B1jEv(%struct.B* %this) { entry: %tmp1 = getelementptr %struct.B, %struct.B* %this, i32 0, i32 0 ; [#uses=1] %tmp2 = load i32, i32* %tmp1 ; [#uses=1] - %tmp4 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([7 x i8], [7 x i8]* @str1, i32 0, i32 0), i32 %tmp2 ) ; [#uses=0] + %tmp4 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([7 x i8], [7 x i8]* @str1, i32 0, i32 0), i32 %tmp2 ) ; [#uses=0] ret void } diff --git a/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll index ca168b6..50573b4 100644 --- a/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll +++ b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll @@ -93,7 +93,7 @@ cond_true1272: ; preds = %cond_next1267 %tmp42.i348 = sub i32 0, %tmp2930.i ; [#uses=1] %tmp45.i = getelementptr %struct.TestObj, %struct.TestObj* %tmp1273, i32 0, i32 0 ; [#uses=2] %tmp48.i = load i8*, i8** %tmp45.i ; [#uses=1] - %tmp50.i350 = call i32 (i8*, i8*, ...)* @sprintf( i8* getelementptr ([256 x i8], [256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8], [48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i ) ; [#uses=0] + %tmp50.i350 = call i32 (i8*, i8*, ...) @sprintf( i8* getelementptr ([256 x i8], [256 x i8]* @Msg, i32 0, i32 0), i8* getelementptr ([48 x i8], [48 x i8]* @.str53615, i32 0, i32 0), i8* null, i8** %tmp45.i, i8* %tmp48.i ) ; [#uses=0] br i1 false, label %cond_true.i632.i, label %Ut_TraceMsg.exit648.i cond_true.i632.i: ; preds = %cond_true1272 diff --git a/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll index 5895a32..f49c805 100644 --- a/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll +++ b/test/CodeGen/ARM/2007-05-07-tailmerge-1.ll @@ -24,13 +24,13 @@ entry: br i1 %toBool, label %cond_true, label %cond_false cond_true: ; preds = %entry - %tmp3 = call i32 (...)* @bar( ) ; [#uses=0] - %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] + %tmp3 = call i32 (...) @bar( ) ; [#uses=0] + %tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] br label %cond_next cond_false: ; preds = %entry - %tmp5 = call i32 (...)* @foo( ) ; [#uses=0] - %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] + %tmp5 = call i32 (...) @foo( ) ; [#uses=0] + %tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] br label %cond_next cond_next: ; preds = %cond_false, %cond_true @@ -41,17 +41,17 @@ cond_next: ; preds = %cond_false, %cond_true br i1 %toBool10, label %cond_true11, label %cond_false15 cond_true11: ; preds = %cond_next - %tmp13 = call i32 (...)* @foo( ) ; [#uses=0] - %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0] + %tmp13 = call i32 (...) @foo( ) ; [#uses=0] + %tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; [#uses=0] br label %cond_next18 cond_false15: ; preds = %cond_next - %tmp16 = call i32 (...)* @bar( ) ; [#uses=0] - %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0] + %tmp16 = call i32 (...) @bar( ) ; [#uses=0] + %tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; [#uses=0] br label %cond_next18 cond_next18: ; preds = %cond_false15, %cond_true11 - %tmp19 = call i32 (...)* @bar( ) ; [#uses=0] + %tmp19 = call i32 (...) @bar( ) ; [#uses=0] br label %return return: ; preds = %cond_next18 diff --git a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll index abb6a33f..421d501 100644 --- a/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll +++ b/test/CodeGen/ARM/2007-05-09-tailmerge-2.ll @@ -26,8 +26,8 @@ entry: br i1 %toBool, label %cond_true, label %cond_false cond_true: ; preds = %entry - %tmp3 = call i32 (...)* @bar( ) ; [#uses=0] - %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] + %tmp3 = call i32 (...) @bar( ) ; [#uses=0] + %tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] %tmp7 = load i32, i32* %q_addr ; [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1] @@ -35,8 +35,8 @@ cond_true: ; preds = %entry br i1 %toBool10, label %cond_true11, label %cond_false15 cond_false: ; preds = %entry - %tmp5 = call i32 (...)* @foo( ) ; [#uses=0] - %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] + %tmp5 = call i32 (...) @foo( ) ; [#uses=0] + %tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] %tmp27 = load i32, i32* %q_addr ; [#uses=1] %tmp28 = icmp ne i32 %tmp27, 0 ; [#uses=1] %tmp289 = zext i1 %tmp28 to i8 ; [#uses=1] @@ -44,17 +44,17 @@ cond_false: ; preds = %entry br i1 %toBool210, label %cond_true11, label %cond_false15 cond_true11: ; preds = %cond_next - %tmp13 = call i32 (...)* @foo( ) ; [#uses=0] - %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0] + %tmp13 = call i32 (...) @foo( ) ; [#uses=0] + %tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; [#uses=0] br label %cond_next18 cond_false15: ; preds = %cond_next - %tmp16 = call i32 (...)* @bar( ) ; [#uses=0] - %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0] + %tmp16 = call i32 (...) @bar( ) ; [#uses=0] + %tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; [#uses=0] br label %cond_next18 cond_next18: ; preds = %cond_false15, %cond_true11 - %tmp19 = call i32 (...)* @bar( ) ; [#uses=0] + %tmp19 = call i32 (...) @bar( ) ; [#uses=0] br label %return return: ; preds = %cond_next18 diff --git a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll index 1edaefb..52cc37e 100644 --- a/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll +++ b/test/CodeGen/ARM/2007-05-22-tailmerge-3.ll @@ -36,8 +36,8 @@ entry: br i1 %toBool, label %cond_true, label %cond_false cond_true: ; preds = %entry - %tmp3 = call i32 (...)* @bar( ) ; [#uses=0] - %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] + %tmp3 = call i32 (...) @bar( ) ; [#uses=0] + %tmp4 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] %tmp7 = load i32, i32* %q_addr ; [#uses=1] %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1] %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1] @@ -45,8 +45,8 @@ cond_true: ; preds = %entry br i1 %toBool10, label %cond_true11, label %cond_false15 cond_false: ; preds = %entry - %tmp5 = call i32 (...)* @foo( ) ; [#uses=0] - %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0] + %tmp5 = call i32 (...) @foo( ) ; [#uses=0] + %tmp6 = call i32 (...) @baz( i32 5, i32 6 ) ; [#uses=0] %tmp27 = load i32, i32* %q_addr ; [#uses=1] %tmp28 = icmp ne i32 %tmp27, 0 ; [#uses=1] %tmp289 = zext i1 %tmp28 to i8 ; [#uses=1] @@ -54,17 +54,17 @@ cond_false: ; preds = %entry br i1 %toBool210, label %cond_true11, label %cond_false15 cond_true11: ; preds = %cond_next - %tmp13 = call i32 (...)* @foo( ) ; [#uses=0] - %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0] + %tmp13 = call i32 (...) @foo( ) ; [#uses=0] + %tmp14 = call i32 (...) @quux( i32 3, i32 4 ) ; [#uses=0] br label %cond_next18 cond_false15: ; preds = %cond_next - %tmp16 = call i32 (...)* @bar( ) ; [#uses=0] - %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0] + %tmp16 = call i32 (...) @bar( ) ; [#uses=0] + %tmp17 = call i32 (...) @quux( i32 3, i32 4 ) ; [#uses=0] br label %cond_next18 cond_next18: ; preds = %cond_false15, %cond_true11 - %tmp19 = call i32 (...)* @bar( ) ; [#uses=0] + %tmp19 = call i32 (...) @bar( ) ; [#uses=0] br label %return return: ; preds = %cond_next18 diff --git a/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll index 5ee8b46..753f9e3 100644 --- a/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll @@ -13,7 +13,7 @@ bb88.i: ; preds = %bb74.i mandel.exit: ; preds = %bb88.i %tmp2 = load volatile double, double* getelementptr ({ double, double }, { double, double }* @accum, i32 0, i32 0), align 8 ; [#uses=1] %tmp23 = fptosi double %tmp2 to i32 ; [#uses=1] - %tmp5 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 ) ; [#uses=0] + %tmp5 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %tmp23 ) ; [#uses=0] ret i32 0 } diff --git a/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll b/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll index bd1f174..1ededa3 100644 --- a/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2008-04-10-ScavengerAssert.ll @@ -73,10 +73,10 @@ bb609.i.i: ; preds = %cond_next602.i.i br label %bb620.i.i bb620.i.i: ; preds = %bb620.i.i, %bb609.i.i %indvar166.i465.i = phi i32 [ %indvar.next167.i.i, %bb620.i.i ], [ 0, %bb609.i.i ] ; [#uses=1] - %tmp640.i.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; [#uses=0] + %tmp640.i.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; [#uses=0] %tmp648.i.i = load i32, i32* null, align 4 ; [#uses=1] %tmp650.i468.i = icmp sgt i32 0, %tmp648.i.i ; [#uses=1] - %tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...)* @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; [#uses=0] + %tmp624.i469.i = call i32 (%struct.FILE*, i8*, ...) @fscanf( %struct.FILE* %tmp61, i8* getelementptr ([5 x i8], [5 x i8]* @.str584, i32 0, i32 0), [1024 x i8]* null ) ; [#uses=0] %indvar.next167.i.i = add i32 %indvar166.i465.i, 1 ; [#uses=1] br i1 %tmp650.i468.i, label %bb653.i.i.loopexit, label %bb620.i.i bb653.i.i.loopexit: ; preds = %bb620.i.i diff --git a/test/CodeGen/ARM/2009-02-16-SpillerBug.ll b/test/CodeGen/ARM/2009-02-16-SpillerBug.ll index d090da0..cad5440 100644 --- a/test/CodeGen/ARM/2009-02-16-SpillerBug.ll +++ b/test/CodeGen/ARM/2009-02-16-SpillerBug.ll @@ -81,7 +81,7 @@ bb244: ; preds = %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122, %bb122 br i1 %0, label %bb435, label %bb433 bb394: ; preds = %bb122 - call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...)* @Error(i32 1, i32 3, i8* getelementptr ([23 x i8], [23 x i8]* @"\01LC13423", i32 0, i32 0), i32 0, %struct.FILE_POS* @no_file_pos, i8* getelementptr ([13 x i8], [13 x i8]* @"\01LC18972", i32 0, i32 0), i8* null) nounwind + call void (i32, i32, i8*, i32, %struct.FILE_POS*, ...) @Error(i32 1, i32 3, i8* getelementptr ([23 x i8], [23 x i8]* @"\01LC13423", i32 0, i32 0), i32 0, %struct.FILE_POS* @no_file_pos, i8* getelementptr ([13 x i8], [13 x i8]* @"\01LC18972", i32 0, i32 0), i8* null) nounwind br label %bb396 bb396: ; preds = %bb394, %bb131, %bb122, %bb122, %bb122, %bb122, %RESUME diff --git a/test/CodeGen/ARM/2009-04-08-FREM.ll b/test/CodeGen/ARM/2009-04-08-FREM.ll index 606c6b1..e0f9485 100644 --- a/test/CodeGen/ARM/2009-04-08-FREM.ll +++ b/test/CodeGen/ARM/2009-04-08-FREM.ll @@ -4,6 +4,6 @@ declare i32 @printf(i8*, ...) define i32 @main() { %rem_r = frem double 0.000000e+00, 0.000000e+00 ; [#uses=1] - %1 = call i32 (i8*, ...)* @printf(i8* null, double %rem_r) ; [#uses=0] + %1 = call i32 (i8*, ...) @printf(i8* null, double %rem_r) ; [#uses=0] ret i32 0 } diff --git a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll index 887fb0b..ac641f9 100644 --- a/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll +++ b/test/CodeGen/ARM/2009-05-07-RegAllocLocal.ll @@ -5,7 +5,7 @@ define i16 @fn16(i16 %arg0.0, <2 x i16> %arg1, i16 %arg2.0) nounwind { entry: store <2 x i16> %arg1, <2 x i16>* null - %0 = call i32 (i8*, ...)* @printf(i8* getelementptr ([30 x i8], [30 x i8]* @.str, i32 0, i32 0), i32 0) nounwind ; [#uses=0] + %0 = call i32 (i8*, ...) @printf(i8* getelementptr ([30 x i8], [30 x i8]* @.str, i32 0, i32 0), i32 0) nounwind ; [#uses=0] ret i16 0 } diff --git a/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll b/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll index b616cb3..ae005db 100644 --- a/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll +++ b/test/CodeGen/ARM/2009-05-11-CodePlacementCrash.ll @@ -19,7 +19,7 @@ bb1: ; preds = %bb bb3: ; preds = %bb1, %bb %iftmp.0.0 = phi i32 [ 0, %bb1 ], [ -1, %bb ] ; [#uses=1] - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind ; [#uses=0] + %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([7 x i8], [7 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 %iftmp.0.0) nounwind ; [#uses=0] %2 = load %struct.List*, %struct.List** null, align 4 ; <%struct.List*> [#uses=2] %phitmp = icmp eq %struct.List* %2, null ; [#uses=1] br i1 %phitmp, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-06-02-ISelCrash.ll b/test/CodeGen/ARM/2009-06-02-ISelCrash.ll index 0612d51..7bbb809 100644 --- a/test/CodeGen/ARM/2009-06-02-ISelCrash.ll +++ b/test/CodeGen/ARM/2009-06-02-ISelCrash.ll @@ -57,6 +57,6 @@ Fft.exit.i: ; preds = %bb7.i.i br i1 undef, label %bb5.i, label %bb1.outer2.i.i.outer bb5.i: ; preds = %Fft.exit.i - %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([15 x i8], [15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind ; [#uses=0] + %0 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([15 x i8], [15 x i8]* @"\01LC", i32 0, i32 0), double undef, double undef) nounwind ; [#uses=0] unreachable } diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll index 72a41f9..e9c4b03 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -47,14 +47,14 @@ bb11: ; preds = %bb9 tail call void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind %4 = sitofp i32 undef to double ; [#uses=1] %5 = fdiv double %4, 1.000000e+01 ; [#uses=1] - %6 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8], [29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; [#uses=0] + %6 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([29 x i8], [29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; [#uses=0] %7 = load i32, i32* @al_len, align 4 ; [#uses=1] %8 = load i32, i32* @no_mat, align 4 ; [#uses=1] %9 = load i32, i32* @no_mis, align 4 ; [#uses=1] %10 = sub i32 %7, %8 ; [#uses=1] %11 = sub i32 %10, %9 ; [#uses=1] - %12 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; [#uses=0] - %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; [#uses=0] + %12 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; [#uses=0] + %13 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll index 92b1869..08291e6 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -42,10 +42,10 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mis, align 4 %4 = getelementptr i8, i8* %B, i32 %0 ; [#uses=1] tail call void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind - %5 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; [#uses=0] + %5 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; [#uses=0] %6 = load i32, i32* @no_mis, align 4 ; [#uses=1] - %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; [#uses=0] - %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; [#uses=0] + %7 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([33 x i8], [33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; [#uses=0] + %8 = tail call i32 (i8*, ...) @printf(i8* getelementptr ([47 x i8], [47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll index 9caa785..b2b3bbe 100644 --- a/test/CodeGen/ARM/2009-10-16-Scope.ll +++ b/test/CodeGen/ARM/2009-10-16-Scope.ll @@ -9,7 +9,7 @@ entry: br label %do.body, !dbg !0 do.body: ; preds = %entry - call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !MDExpression()) + call void @llvm.dbg.declare(metadata i32* %count_, metadata !4, metadata !MDExpression()), !dbg !MDLocation(scope: !5) %conv = ptrtoint i32* %count_ to i32, !dbg !0 ; [#uses=1] %call = call i32 @foo(i32 %conv) ssp, !dbg !0 ; [#uses=0] br label %do.end, !dbg !0 diff --git a/test/CodeGen/ARM/2009-10-27-double-align.ll b/test/CodeGen/ARM/2009-10-27-double-align.ll index b43f2a6..39f3292 100644 --- a/test/CodeGen/ARM/2009-10-27-double-align.ll +++ b/test/CodeGen/ARM/2009-10-27-double-align.ll @@ -8,7 +8,7 @@ entry: ;CHECK: [sp, #8] ;CHECK: [sp, #12] ;CHECK: [sp] - tail call void (i8*, ...)* @f(i8* getelementptr ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) + tail call void (i8*, ...) @f(i8* getelementptr ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 1, double 2.000000e+00, i32 3, double 4.000000e+00) ret void } diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll index 8df3aaf..312cccd 100644 --- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -5,7 +5,7 @@ target triple = "armv4t-apple-darwin10" define hidden i32 @__addvsi3(i32 %a, i32 %b) nounwind { entry: - tail call void @llvm.dbg.value(metadata i32 %b, i64 0, metadata !0, metadata !MDExpression()) + tail call void @llvm.dbg.value(metadata i32 %b, i64 0, metadata !0, metadata !MDExpression()), !dbg !MDLocation(scope: !1) %0 = add nsw i32 %b, %a, !dbg !9 ; [#uses=1] ret i32 %0, !dbg !11 } @@ -27,6 +27,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !9 = !MDLocation(line: 95, scope: !10) !10 = distinct !MDLexicalBlock(line: 94, column: 0, file: !12, scope: !1) !11 = !MDLocation(line: 100, scope: !10) -!13 = !{i32 0} +!13 = !{} !14 = !{!1} !15 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll index 89ad5f5..deb5884 100644 --- a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll +++ b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -19,12 +19,12 @@ entry: %tmp21 = load i32, i32* undef ; [#uses=1] %0 = mul i32 1, %tmp21 ; [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; [#uses=1] - call void (...)* @zz(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) + call void (...) @zz(i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) br i1 undef, label %if.then, label %if.end36 if.then: ; preds = %entry - %call = call i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; [#uses=0] - %call35 = call i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; [#uses=0] + %call = call i32 (...) @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; [#uses=0] + %call35 = call i32 (...) @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; [#uses=0] unreachable if.end36: ; preds = %entry diff --git a/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll index 9cd61d3..6f55ac0 100644 --- a/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll +++ b/test/CodeGen/ARM/2010-06-21-LdStMultipleBug.ll @@ -13,7 +13,7 @@ define void @TW_oldinput(%struct.FILE* nocapture %fp) nounwind { entry: %xcenter = alloca i32, align 4 ; [#uses=2] - %0 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; [#uses=1] + %0 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; [#uses=1] %1 = icmp eq i32 %0, 4 ; [#uses=1] br i1 %1, label %bb, label %return @@ -137,7 +137,7 @@ bb322: ; preds = %bb248 br i1 undef, label %bb248, label %bb445 bb445: ; preds = %bb322, %bb10, %bb - %49 = call i32 (%struct.FILE*, i8*, ...)* @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; [#uses=1] + %49 = call i32 (%struct.FILE*, i8*, ...) @fscanf(%struct.FILE* %fp, i8* getelementptr inbounds ([14 x i8], [14 x i8]* @.str2708, i32 0, i32 0), i32* undef, i32* undef, i32* %xcenter, i32* null) nounwind ; [#uses=1] %50 = icmp eq i32 %49, 4 ; [#uses=1] br i1 %50, label %bb, label %return diff --git a/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll b/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll index 4c5d8d9..b02efea 100644 --- a/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll +++ b/test/CodeGen/ARM/2010-07-26-GlobalMerge.ll @@ -31,7 +31,7 @@ define internal void @_ZN1AD1Ev(%struct.A* nocapture %this) nounwind ssp align 2 entry: %tmp.i = getelementptr inbounds %struct.A, %struct.A* %this, i32 0, i32 0 ; [#uses=1] %tmp2.i = load i32, i32* %tmp.i ; [#uses=1] - %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 %tmp2.i) nounwind ; [#uses=0] + %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 %tmp2.i) nounwind ; [#uses=0] %tmp3.i = load i32, i32* @d ; [#uses=1] %inc.i = add nsw i32 %tmp3.i, 1 ; [#uses=1] store i32 %inc.i, i32* @d @@ -46,7 +46,7 @@ entry: %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind ; [#uses=2] %tmp2.i.i.i = bitcast i8* %exception.i to i32* ; [#uses=1] store i32 1, i32* %tmp2.i.i.i - %call.i.i.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str5, i32 0, i32 0), i32 1) nounwind ; [#uses=0] + %call.i.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @.str5, i32 0, i32 0), i32 1) nounwind ; [#uses=0] invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (%0* @_ZTI1A to i8*), i8* bitcast (void (%struct.A*)* @_ZN1AD1Ev to i8*)) noreturn to label %.noexc unwind label %lpad @@ -55,16 +55,16 @@ entry: try.cont: ; preds = %lpad %0 = tail call i8* @__cxa_get_exception_ptr(i8* %exn) nounwind ; [#uses=0] - %call.i.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str3, i32 0, i32 0), i32 2) nounwind ; [#uses=0] + %call.i.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str3, i32 0, i32 0), i32 2) nounwind ; [#uses=0] %1 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind ; [#uses=0] %puts = tail call i32 @puts(i8* getelementptr inbounds ([8 x i8], [8 x i8]* @str1, i32 0, i32 0)) ; [#uses=0] - %call.i.i3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 2) nounwind ; [#uses=0] + %call.i.i3 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str4, i32 0, i32 0), i32 2) nounwind ; [#uses=0] %tmp3.i.i = load i32, i32* @d ; [#uses=1] %inc.i.i4 = add nsw i32 %tmp3.i.i, 1 ; [#uses=1] store i32 %inc.i.i4, i32* @d tail call void @__cxa_end_catch() %tmp13 = load i32, i32* @d ; [#uses=1] - %call14 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str2, i32 0, i32 0), i32 2, i32 %tmp13) ; [#uses=0] + %call14 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str2, i32 0, i32 0), i32 2, i32 %tmp13) ; [#uses=0] %tmp16 = load i32, i32* @d ; [#uses=1] %cmp = icmp ne i32 %tmp16, 2 ; [#uses=1] %conv = zext i1 %cmp to i32 ; [#uses=1] diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index d3c0fee..cb91890 100644 --- a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -15,11 +15,6 @@ ; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals -; OBJ: Sections [ -; OBJ: Section { -; OBJ: Index: 4 -; OBJ-NEXT: Name: .bss - ; OBJ: Symbols [ ; OBJ: Symbol { ; OBJ: Name: array00 diff --git a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll index e712e08..f17884e 100644 --- a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll +++ b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll @@ -12,7 +12,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - tail call void (...)* @g(i32 %a, i32 %b) nounwind + tail call void (...) @g(i32 %a, i32 %b) nounwind br label %if.end if.end: ; preds = %if.then, %entry diff --git a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll index 5404cf5..864e291 100644 --- a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll +++ b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll @@ -12,7 +12,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - tail call void (...)* @h(i32 %a, i32 %b) nounwind + tail call void (...) @h(i32 %a, i32 %b) nounwind br label %if.end if.end: ; preds = %if.then, %entry @@ -31,7 +31,7 @@ entry: br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry - tail call void (...)* @h(i32 %a, i32 %b) nounwind + tail call void (...) @h(i32 %a, i32 %b) nounwind br label %if.end if.end: ; preds = %if.then, %entry diff --git a/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll b/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll index 9f2fa63..86596d6 100644 --- a/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll +++ b/test/CodeGen/ARM/2011-10-26-ExpandUnalignedLoadCrash.ll @@ -4,7 +4,7 @@ target triple = "armv6-none-linux-gnueabi" define void @sample_test(i8* %.T0348, i16* nocapture %sourceA, i16* nocapture %destValues) { L.entry: - %0 = call i32 (...)* @get_index(i8* %.T0348, i32 0) + %0 = call i32 (...) @get_index(i8* %.T0348, i32 0) %1 = bitcast i16* %destValues to i8* %2 = mul i32 %0, 6 %3 = getelementptr i8, i8* %1, i32 %2 diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll index b64b1bf..4a1341c 100644 --- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll +++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll @@ -33,7 +33,7 @@ entry: ; CHECK: movw r0, #555 define i32 @main() { entry: - call void (i32, ...)* @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val) + call void (i32, ...) @test_byval_8_bytes_alignment(i32 555, %struct_t* byval @static_val) ret i32 0 } @@ -48,7 +48,7 @@ define void @test_byval_8_bytes_alignment_fixed_arg(i32 %n1, %struct_t* byval %v entry: %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 %0 = load double, double* %a - call void (double)* @f(double %0) + call void (double) @f(double %0) ret void } @@ -60,6 +60,6 @@ entry: ; CHECK: movw r0, #555 define i32 @main_fixed_arg() { entry: - call void (i32, %struct_t*)* @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val) + call void (i32, %struct_t*) @test_byval_8_bytes_alignment_fixed_arg(i32 555, %struct_t* byval @static_val) ret i32 0 } diff --git a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll index ef06f59..34af902 100644 --- a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll +++ b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll @@ -14,6 +14,6 @@ define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val entry: %a = getelementptr inbounds %struct_t, %struct_t* %val, i32 0, i32 0 %0 = load double, double* %a - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), double %0) + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str, i32 0, i32 0), double %0) ret void } diff --git a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll index 427519f..d18dbd2 100644 --- a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll +++ b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll @@ -14,7 +14,7 @@ define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) { entry: %conv = sext i16 %b to i32 %conv1 = sext i8 %E to i32 - %call = tail call i32 (i8*, ...)* @printf( + %call = tail call i32 (i8*, ...) @printf( i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), ; --> R0 i32 %a, ; --> R1 i32 %conv, ; --> R2 diff --git a/test/CodeGen/ARM/2013-10-11-select-stalls.ll b/test/CodeGen/ARM/2013-10-11-select-stalls.ll index 33c0587..d6045c7 100644 --- a/test/CodeGen/ARM/2013-10-11-select-stalls.ll +++ b/test/CodeGen/ARM/2013-10-11-select-stalls.ll @@ -7,7 +7,7 @@ define <16 x i8> @multiselect(i32 %avail, i8* %foo, i8* %bar) { entry: %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %foo, i32 1) %vld2 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1) - %and = and i32 %avail, 1 + %and = and i32 %avail, 3 %tobool = icmp eq i32 %and, 0 %retv = select i1 %tobool, <16 x i8> %vld1, <16 x i8> %vld2 ret <16 x i8> %retv diff --git a/test/CodeGen/ARM/aliases.ll b/test/CodeGen/ARM/aliases.ll index c24d0d2..04ca3e8 100644 --- a/test/CodeGen/ARM/aliases.ll +++ b/test/CodeGen/ARM/aliases.ll @@ -38,7 +38,7 @@ entry: %tmp0 = load i32, i32* @bar_i %tmp2 = call i32 @foo_f() %tmp3 = add i32 %tmp, %tmp2 - %tmp4 = call %FunTy* @bar_f() + %tmp4 = call i32 @bar_f() %tmp5 = add i32 %tmp3, %tmp4 %tmp6 = add i32 %tmp1, %tmp5 %tmp7 = add i32 %tmp6, %tmp0 diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll index e7fbf9f..3b1d8dd 100644 --- a/test/CodeGen/ARM/arguments.ll +++ b/test/CodeGen/ARM/arguments.ll @@ -18,7 +18,7 @@ define i32 @f2() nounwind optsize { ; DARWIN-LABEL: f2: ; DARWIN: mov r3, #128 entry: - %0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; [#uses=1] + %0 = tail call i32 (i32, ...) @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; [#uses=1] %not. = icmp ne i32 %0, 128 ; [#uses=1] %.0 = zext i1 %not. to i32 ; [#uses=1] ret i32 %.0 diff --git a/test/CodeGen/ARM/arm-asm.ll b/test/CodeGen/ARM/arm-asm.ll index e869abe..f9199ff 100644 --- a/test/CodeGen/ARM/arm-asm.ll +++ b/test/CodeGen/ARM/arm-asm.ll @@ -2,6 +2,6 @@ define void @frame_dummy() { entry: - %tmp1 = tail call void (i8*)* (void (i8*)*)* asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null ) ; [#uses=0] + %tmp1 = tail call void (i8*)* (void (i8*)*) asm "", "=r,0,~{dirflag},~{fpsr},~{flags}"( void (i8*)* null ) ; [#uses=0] ret void } diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll index 8540833..1982fa9 100644 --- a/test/CodeGen/ARM/build-attributes.ll +++ b/test/CodeGen/ARM/build-attributes.ll @@ -81,6 +81,8 @@ ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-FAST ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7-DOUBLE ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4 | FileCheck %s --check-prefix=CORTEX-R4 +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r4f | FileCheck %s --check-prefix=CORTEX-R4F ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R5-FAST ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING @@ -1012,6 +1014,49 @@ ; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 22 ; CORTEX-M7-NOFPU-FAST: .eabi_attribute 23, 1 +; CORTEX-R4: .cpu cortex-r4 +; CORTEX-R4: .eabi_attribute 6, 10 +; CORTEX-R4: .eabi_attribute 7, 82 +; CORTEX-R4: .eabi_attribute 8, 1 +; CORTEX-R4: .eabi_attribute 9, 2 +; CORTEX-R4-NOT: .fpu vfpv3-d16 +; CORTEX-R4-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-R4: .eabi_attribute 20, 1 +; CORTEX-R4: .eabi_attribute 21, 1 +; CORTEX-R4-NOT: .eabi_attribute 22 +; CORTEX-R4: .eabi_attribute 23, 3 +; CORTEX-R4: .eabi_attribute 24, 1 +; CORTEX-R4: .eabi_attribute 25, 1 +; CORTEX-R4-NOT: .eabi_attribute 28 +; CORTEX-R4-NOT: .eabi_attribute 36 +; CORTEX-R4: .eabi_attribute 38, 1 +; CORTEX-R4-NOT: .eabi_attribute 42 +; CORTEX-R4-NOT: .eabi_attribute 44 +; CORTEX-R4-NOT: .eabi_attribute 68 + +; CORTEX-R4F: .cpu cortex-r4f +; CORTEX-R4F: .eabi_attribute 6, 10 +; CORTEX-R4F: .eabi_attribute 7, 82 +; CORTEX-R4F: .eabi_attribute 8, 1 +; CORTEX-R4F: .eabi_attribute 9, 2 +; CORTEX-R4F: .fpu vfpv3-d16 +; CORTEX-R4F-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-R4F: .eabi_attribute 20, 1 +; CORTEX-R4F: .eabi_attribute 21, 1 +; CORTEX-R4F-NOT: .eabi_attribute 22 +; CORTEX-R4F: .eabi_attribute 23, 3 +; CORTEX-R4F: .eabi_attribute 24, 1 +; CORTEX-R4F: .eabi_attribute 25, 1 +; CORTEX-R4F: .eabi_attribute 27, 1 +; CORTEX-R4F-NOT: .eabi_attribute 28 +; CORTEX-R4F-NOT: .eabi_attribute 36 +; CORTEX-R4F: .eabi_attribute 38, 1 +; CORTEX-R4F-NOT: .eabi_attribute 42 +; CORTEX-R4F-NOT: .eabi_attribute 44 +; CORTEX-R4F-NOT: .eabi_attribute 68 + ; CORTEX-R5: .cpu cortex-r5 ; CORTEX-R5: .eabi_attribute 6, 10 ; CORTEX-R5: .eabi_attribute 7, 82 diff --git a/test/CodeGen/ARM/bx_fold.ll b/test/CodeGen/ARM/bx_fold.ll index c1aac44..f6651ae 100644 --- a/test/CodeGen/ARM/bx_fold.ll +++ b/test/CodeGen/ARM/bx_fold.ll @@ -14,7 +14,7 @@ bb: ; preds = %bb1 bb1: ; preds = %bb, %entry %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; [#uses=3] %i.0 = bitcast i32 %indvar to i32 ; [#uses=2] - %tmp = tail call i32 (...)* @bar( ) ; [#uses=1] + %tmp = tail call i32 (...) @bar( ) ; [#uses=1] %tmp2 = add i32 %i.0, %tmp ; [#uses=1] %Ptr_addr.0 = sub i32 %Ptr, %tmp2 ; [#uses=0] %tmp12 = icmp eq i32 %i.0, %Ptr ; [#uses=1] diff --git a/test/CodeGen/ARM/cache-intrinsic.ll b/test/CodeGen/ARM/cache-intrinsic.ll index a041d075..12b55c7 100644 --- a/test/CodeGen/ARM/cache-intrinsic.ll +++ b/test/CodeGen/ARM/cache-intrinsic.ll @@ -10,10 +10,10 @@ define i32 @main() { entry: %retval = alloca i32, align 4 store i32 0, i32* %retval - %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0)) + %call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0)) %call1 = call i8* @strcpy(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds ([25 x i8], [25 x i8]* @.str1, i32 0, i32 0)) #3 call void @llvm.clear_cache(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i8* getelementptr inbounds (i8, i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0), i32 32)) #3 - %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0)) + %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([32 x i8], [32 x i8]* @buffer, i32 0, i32 0)) ret i32 0 } diff --git a/test/CodeGen/ARM/compare-call.ll b/test/CodeGen/ARM/compare-call.ll index d4bd92b..f45ed73 100644 --- a/test/CodeGen/ARM/compare-call.ll +++ b/test/CodeGen/ARM/compare-call.ll @@ -9,7 +9,7 @@ entry: br i1 %tmp.upgrd.1, label %cond_true, label %UnifiedReturnBlock cond_true: ; preds = %entry - %tmp.upgrd.2 = tail call i32 (...)* @bar( ) ; [#uses=0] + %tmp.upgrd.2 = tail call i32 (...) @bar( ) ; [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll index cb9520e..c75c630 100644 --- a/test/CodeGen/ARM/debug-info-arg.ll +++ b/test/CodeGen/ARM/debug-info-arg.ll @@ -32,7 +32,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} -!0 = !MDCompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 1, file: !32, enums: !4, retainedTypes: !4, subprograms: !30, imports: null) +!0 = !MDCompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 1, file: !32, enums: !{}, retainedTypes: !{}, subprograms: !30, imports: null) !1 = !MDSubprogram(name: "foo", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !2, scope: !2, type: !3, function: void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, variables: !31) !2 = !MDFile(filename: "one.c", directory: "/Volumes/Athwagate/R10048772") !3 = !MDSubroutineType(types: !4) diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll index 96876b1..4e499c6 100644 --- a/test/CodeGen/ARM/debug-info-blocks.ll +++ b/test/CodeGen/ARM/debug-info-blocks.ll @@ -95,7 +95,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!162} -!0 = !MDCompileUnit(language: DW_LANG_ObjC, producer: "Apple clang version 2.1", isOptimized: false, runtimeVersion: 2, emissionKind: 1, file: !153, enums: !147, retainedTypes: !26, subprograms: !148) +!0 = !MDCompileUnit(language: DW_LANG_ObjC, producer: "Apple clang version 2.1", isOptimized: false, runtimeVersion: 2, emissionKind: 1, file: !153, enums: !147, retainedTypes: !{}, subprograms: !148) !1 = !MDCompositeType(tag: DW_TAG_enumeration_type, line: 248, size: 32, align: 32, file: !160, scope: !0, elements: !3) !2 = !MDFile(filename: "header.h", directory: "/Volumes/Sandbox/llvm") !3 = !{!4} @@ -158,7 +158,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !60 = !MDCompositeType(tag: DW_TAG_structure_type, name: "UIMydata", line: 26, size: 128, align: 32, runtimeLang: DW_LANG_ObjC, file: !154, scope: !24, elements: !62) !61 = !MDFile(filename: "header11.h", directory: "/Volumes/Sandbox/llvm") !62 = !{!63, !71, !75, !79} -!63 = !MDDerivedType(tag: DW_TAG_inheritance, file: !60, baseType: !64) +!63 = !MDDerivedType(tag: DW_TAG_inheritance, file: !61, baseType: !64) !64 = !MDCompositeType(tag: DW_TAG_structure_type, name: "NSO", line: 66, size: 32, align: 32, runtimeLang: DW_LANG_ObjC, file: !155, scope: !40, elements: !66) !65 = !MDFile(filename: "NSO.h", directory: "/Volumes/Sandbox/llvm") !66 = !{!67} @@ -192,7 +192,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !94 = !MDCompositeType(tag: DW_TAG_structure_type, name: "twork", line: 43, size: 32, align: 32, runtimeLang: DW_LANG_ObjC, file: !157, scope: !40, elements: !96) !95 = !MDFile(filename: "header13.h", directory: "/Volumes/Sandbox/llvm") !96 = !{!97} -!97 = !MDDerivedType(tag: DW_TAG_inheritance, file: !94, baseType: !64) +!97 = !MDDerivedType(tag: DW_TAG_inheritance, file: !95, baseType: !64) !98 = !MDDerivedType(tag: DW_TAG_member, name: "_itemID", line: 38, size: 64, align: 32, offset: 32, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !99, extraData: !"") !99 = !MDDerivedType(tag: DW_TAG_typedef, name: "uint64_t", line: 55, file: !153, scope: !0, baseType: !100) !100 = !MDBasicType(tag: DW_TAG_base_type, name: "long long unsigned int", size: 64, align: 32, encoding: DW_ATE_unsigned) @@ -201,7 +201,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !103 = !MDCompositeType(tag: DW_TAG_structure_type, name: "MyLibrary2", line: 22, size: 32, align: 32, runtimeLang: DW_LANG_ObjC, file: !158, scope: !40, elements: !105) !104 = !MDFile(filename: "header14.h", directory: "/Volumes/Sandbox/llvm") !105 = !{!106} -!106 = !MDDerivedType(tag: DW_TAG_inheritance, file: !103, baseType: !64) +!106 = !MDDerivedType(tag: DW_TAG_inheritance, file: !104, baseType: !64) !107 = !MDDerivedType(tag: DW_TAG_member, name: "_bounds", line: 40, size: 128, align: 32, offset: 128, flags: DIFlagPrivate, file: !152, scope: !24, baseType: !108, extraData: !"") !108 = !MDDerivedType(tag: DW_TAG_typedef, name: "CR", line: 33, file: !153, scope: !0, baseType: !109) !109 = !MDCompositeType(tag: DW_TAG_structure_type, name: "CR", line: 29, size: 128, align: 32, file: !156, scope: !0, elements: !110) diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll index bd2ae80..cb57efa 100644 --- a/test/CodeGen/ARM/debug-info-branch-folding.ll +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -28,10 +28,10 @@ for.body9: ; preds = %for.body9, %entry for.end54: ; preds = %for.body9 %tmp115 = extractelement <4 x float> %add19, i32 1 %conv6.i75 = fpext float %tmp115 to double, !dbg !45 - %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 + %call.i82 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 %tmp116 = extractelement <4 x float> %add20, i32 1 %conv6.i76 = fpext float %tmp116 to double, !dbg !45 - %call.i83 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i76, double undef, double undef) nounwind, !dbg !45 + %call.i83 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i76, double undef, double undef) nounwind, !dbg !45 ret i32 0, !dbg !49 } @@ -44,7 +44,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !0 = !MDSubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !3, function: <4 x float> (float)* @test0001, variables: !51) !1 = !MDFile(filename: "build2.c", directory: "/private/tmp") -!2 = !MDCompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !17, retainedTypes: !17, subprograms: !50, imports: null) +!2 = !MDCompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) !3 = !MDSubroutineType(types: !4) !4 = !{!5} !5 = !MDDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6) diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll index 0667e0f..034d0f4 100644 --- a/test/CodeGen/ARM/debug-info-d16-reg.ll +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -16,7 +16,7 @@ entry: tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !20, metadata !MDExpression()), !dbg !26 tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !21, metadata !MDExpression()), !dbg !26 %0 = zext i8 %c to i32, !dbg !27 - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27 + %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27 ret i32 0, !dbg !29 } @@ -26,7 +26,7 @@ entry: tail call void @llvm.dbg.value(metadata double %val, i64 0, metadata !17, metadata !MDExpression()), !dbg !30 tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !18, metadata !MDExpression()), !dbg !30 %0 = zext i8 %c to i32, !dbg !31 - %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31 + %1 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31 ret i32 0, !dbg !33 } @@ -45,11 +45,11 @@ entry: %3 = getelementptr inbounds i8, i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !37 %4 = trunc i32 %argc to i8, !dbg !37 %5 = add i8 %4, 97, !dbg !37 - tail call void @llvm.dbg.value(metadata i8* %3, i64 0, metadata !19, metadata !MDExpression()) nounwind, !dbg !38 - tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !20, metadata !MDExpression()) nounwind, !dbg !38 - tail call void @llvm.dbg.value(metadata i8 %5, i64 0, metadata !21, metadata !MDExpression()) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata i8* %3, i64 0, metadata !49, metadata !MDExpression()) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata double %1, i64 0, metadata !50, metadata !MDExpression()) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata i8 %5, i64 0, metadata !51, metadata !MDExpression()) nounwind, !dbg !38 %6 = zext i8 %5 to i32, !dbg !39 - %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39 + %7 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39 %8 = tail call i32 @printer(i8* %3, double %1, i8 zeroext %5) nounwind, !dbg !40 ret i32 0, !dbg !41 } @@ -75,12 +75,17 @@ declare i32 @puts(i8* nocapture) nounwind !13 = !MDDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: !14) !14 = !MDDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: !15) !15 = !MDBasicType(tag: DW_TAG_base_type, name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) -!16 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 11, arg: 0, scope: !0, file: !1, type: !6) -!17 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 11, arg: 0, scope: !0, file: !1, type: !7) -!18 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 0, scope: !0, file: !1, type: !8) -!19 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 0, scope: !9, file: !1, type: !6) -!20 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 0, scope: !9, file: !1, type: !7) -!21 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 0, scope: !9, file: !1, type: !8) +!16 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 11, arg: 1, scope: !0, file: !1, type: !6) +!17 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 11, arg: 2, scope: !0, file: !1, type: !7) +!18 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 3, scope: !0, file: !1, type: !8) +!19 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6) +!20 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7) +!21 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !9, file: !1, type: !8) + +!49 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !9, file: !1, type: !6) +!50 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !9, file: !1, type: !7) +!51 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 2, scope: !9, file: !1, type: !8) + !22 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "argc", line: 17, arg: 0, scope: !10, file: !1, type: !5) !23 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "argv", line: 17, arg: 0, scope: !10, file: !1, type: !13) !24 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "dval", line: 19, scope: !25, file: !1, type: !7) @@ -106,5 +111,5 @@ declare i32 @puts(i8* nocapture) nounwind !44 = !{!19, !20, !21} !45 = !{!22, !23, !24} !46 = !MDFile(filename: "a.c", directory: "/tmp/") -!47 = !{i32 0} +!47 = !{} !48 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/debug-info-no-frame.ll b/test/CodeGen/ARM/debug-info-no-frame.ll new file mode 100644 index 0000000..418a074 --- /dev/null +++ b/test/CodeGen/ARM/debug-info-no-frame.ll @@ -0,0 +1,36 @@ +; RUN: llc -mtriple=armv7-none-linux-gnueabihf < %s -o - | FileCheck %s + +; Function Attrs: nounwind +define void @need_cfi_def_cfa_offset() #0 { +; CHECK-LABEL: need_cfi_def_cfa_offset: +; CHECK: sub sp, sp, #4 +; CHECK: .cfi_def_cfa_offset 4 +entry: + %Depth = alloca i32, align 4 + call void @llvm.dbg.declare(metadata i32* %Depth, metadata !9, metadata !10), !dbg !11 + store i32 2, i32* %Depth, align 4, !dbg !11 + ret void, !dbg !12 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!7, !8} + +!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false) +!1 = !MDFile(filename: "file.c", directory: "/dir") +!2 = !{} +!3 = !MDSubprogram(name: "need_cfi_def_cfa_offset", scope: !1, file: !1, line: 1, type: !4, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, function: void ()* @need_cfi_def_cfa_offset, variables: !2) +!4 = !MDSubroutineType(types: !5) +!5 = !{null} +!6 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!7 = !{i32 2, !"Dwarf Version", i32 4} +!8 = !{i32 2, !"Debug Info Version", i32 3} +!9 = !MDLocalVariable(tag: DW_TAG_auto_variable, name: "Depth", scope: !3, file: !1, line: 3, type: !6) +!10 = !MDExpression() +!11 = !MDLocation(line: 3, column: 9, scope: !3) +!12 = !MDLocation(line: 7, column: 5, scope: !3) diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll index 398f652..9cfd67d 100644 --- a/test/CodeGen/ARM/debug-info-qreg.ll +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -27,7 +27,7 @@ for.end54: ; preds = %for.body9 tail call void @llvm.dbg.value(metadata <4 x float> %add19, i64 0, metadata !27, metadata !MDExpression()), !dbg !39 %tmp115 = extractelement <4 x float> %add19, i32 1 %conv6.i75 = fpext float %tmp115 to double, !dbg !45 - %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 + %call.i82 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 ret i32 0, !dbg !49 } @@ -40,11 +40,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !0 = !MDSubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !54, scope: !1, type: !3, function: <4 x float> (float)* @test0001, variables: !51) !1 = !MDFile(filename: "build2.c", directory: "/private/tmp") -!2 = !MDCompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !17, retainedTypes: !17, subprograms: !50, imports: null) +!2 = !MDCompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) !3 = !MDSubroutineType(types: !4) !4 = !{!5} !5 = !MDDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6) -!6 = !MDCompositeType(tag: DW_TAG_array_type, size: 128, align: 128, file: !2, baseType: !7, elements: !8) +!6 = !MDCompositeType(tag: DW_TAG_array_type, size: 128, align: 128, file: !1, baseType: !7, elements: !8) !7 = !MDBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) !8 = !{!9} !9 = !MDSubrange(count: 4) diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll index d08ec03..3cd2837 100644 --- a/test/CodeGen/ARM/debug-info-s16-reg.ll +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -19,7 +19,7 @@ entry: tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !12, metadata !MDExpression()), !dbg !26 %conv = fpext float %val to double, !dbg !27 %conv3 = zext i8 %c to i32, !dbg !27 - %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27 + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27 ret i32 0, !dbg !29 } @@ -32,7 +32,7 @@ entry: tail call void @llvm.dbg.value(metadata i8 %c, i64 0, metadata !16, metadata !MDExpression()), !dbg !32 %conv = fpext float %val to double, !dbg !33 %conv3 = zext i8 %c to i32, !dbg !33 - %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33 + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33 ret i32 0, !dbg !35 } @@ -48,12 +48,12 @@ entry: %add.ptr = getelementptr i8, i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !40 %add5 = add nsw i32 %argc, 97, !dbg !40 %conv6 = trunc i32 %add5 to i8, !dbg !40 - tail call void @llvm.dbg.value(metadata i8* %add.ptr, i64 0, metadata !8, metadata !MDExpression()) nounwind, !dbg !41 - tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !10, metadata !MDExpression()) nounwind, !dbg !42 - tail call void @llvm.dbg.value(metadata i8 %conv6, i64 0, metadata !12, metadata !MDExpression()) nounwind, !dbg !43 + tail call void @llvm.dbg.value(metadata i8* %add.ptr, i64 0, metadata !58, metadata !MDExpression()) nounwind, !dbg !41 + tail call void @llvm.dbg.value(metadata float %conv1, i64 0, metadata !60, metadata !MDExpression()) nounwind, !dbg !42 + tail call void @llvm.dbg.value(metadata i8 %conv6, i64 0, metadata !62, metadata !MDExpression()) nounwind, !dbg !43 %conv.i = fpext float %conv1 to double, !dbg !44 %conv3.i = and i32 %add5, 255, !dbg !44 - %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44 + %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([11 x i8], [11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44 %call14 = tail call i32 @printer(i8* %add.ptr, float %conv1, i8 zeroext %conv6) optsize, !dbg !45 ret i32 0, !dbg !46 } @@ -79,6 +79,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !11 = !MDBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) !12 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13) !13 = !MDBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) + +!58 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9) +!60 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11) +!62 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 4, arg: 3, scope: !0, file: !1, type: !13) + !14 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "ptr", line: 11, arg: 1, scope: !6, file: !1, type: !9) !15 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "val", line: 11, arg: 2, scope: !6, file: !1, type: !11) !16 = !MDLocalVariable(tag: DW_TAG_arg_variable, name: "c", line: 11, arg: 3, scope: !6, file: !1, type: !13) @@ -117,5 +122,5 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !49 = !{!14, !15, !16} !50 = !{!17, !18, !22} !51 = !MDFile(filename: "a.c", directory: "/private/tmp") -!52 = !{i32 0} +!52 = !{} !53 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll index df578fd..e5f7a27 100644 --- a/test/CodeGen/ARM/debug-info-sreg2.ll +++ b/test/CodeGen/ARM/debug-info-sreg2.ll @@ -62,5 +62,5 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !16 = !{!1} !17 = !{!5, !8} !18 = !MDFile(filename: "k.cc", directory: "/private/tmp") -!19 = !{i32 0} +!19 = !{} !20 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/div.ll b/test/CodeGen/ARM/div.ll index a339c81..7b298fe 100644 --- a/test/CodeGen/ARM/div.ll +++ b/test/CodeGen/ARM/div.ll @@ -1,11 +1,13 @@ -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-ARM -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV -; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift | FileCheck %s -check-prefix=CHECK-HWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4 | FileCheck %s -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f | FileCheck %s -check-prefix=CHECK-SWDIV +; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5 | FileCheck %s -check-prefix=CHECK-HWDIV define i32 @f1(i32 %a, i32 %b) { entry: -; CHECK-ARM: f1 -; CHECK-ARM: __divsi3 +; CHECK-SWDIV: f1 +; CHECK-SWDIV: __divsi3 ; CHECK-HWDIV: f1 ; CHECK-HWDIV: sdiv @@ -15,8 +17,8 @@ entry: define i32 @f2(i32 %a, i32 %b) { entry: -; CHECK-ARM: f2 -; CHECK-ARM: __udivsi3 +; CHECK-SWDIV: f2 +; CHECK-SWDIV: __udivsi3 ; CHECK-HWDIV: f2 ; CHECK-HWDIV: udiv @@ -26,8 +28,8 @@ entry: define i32 @f3(i32 %a, i32 %b) { entry: -; CHECK-ARM: f3 -; CHECK-ARM: __modsi3 +; CHECK-SWDIV: f3 +; CHECK-SWDIV: __modsi3 ; CHECK-HWDIV: f3 ; CHECK-HWDIV: sdiv @@ -38,8 +40,8 @@ entry: define i32 @f4(i32 %a, i32 %b) { entry: -; CHECK-ARM: f4 -; CHECK-ARM: __umodsi3 +; CHECK-SWDIV: f4 +; CHECK-SWDIV: __umodsi3 ; CHECK-HWDIV: f4 ; CHECK-HWDIV: udiv diff --git a/test/CodeGen/ARM/fast-isel-vararg.ll b/test/CodeGen/ARM/fast-isel-vararg.ll index aa37e7d..35442ee 100644 --- a/test/CodeGen/ARM/fast-isel-vararg.ll +++ b/test/CodeGen/ARM/fast-isel-vararg.ll @@ -37,7 +37,7 @@ entry: ; THUMB: str.w {{[a-z0-9]+}}, [sp] ; THUMB: str.w {{[a-z0-9]+}}, [sp, #4] ; THUMB: bl {{_?}}CallVariadic - %call = call i32 (i32, ...)* @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) + %call = call i32 (i32, ...) @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4) store i32 %call, i32* %tmp, align 4 %5 = load i32, i32* %tmp, align 4 ret i32 %5 diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll index 1de0572..d013fbf 100644 --- a/test/CodeGen/ARM/fcopysign.ll +++ b/test/CodeGen/ARM/fcopysign.ll @@ -48,7 +48,7 @@ entry: ; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000 ; SOFT: vshr.u64 [[REG7]], [[REG7]], #32 ; SOFT: vbsl [[REG6]], [[REG7]], - %0 = tail call double (...)* @bar() nounwind + %0 = tail call double (...) @bar() nounwind %1 = fptrunc double %0 to float %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone %3 = fadd float %1, %2 diff --git a/test/CodeGen/ARM/ghc-tcreturn-lowered.ll b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll index 9731b3d..f34f8f1 100644 --- a/test/CodeGen/ARM/ghc-tcreturn-lowered.ll +++ b/test/CodeGen/ARM/ghc-tcreturn-lowered.ll @@ -16,6 +16,6 @@ define ghccc void @test_indirect_tail() { ; CHECK-LABEL: test_indirect_tail: ; CHECK: bx {{r[0-9]+}} %func = load void()*, void()** @ind_func - tail call ghccc void()* %func() + tail call ghccc void() %func() ret void } diff --git a/test/CodeGen/ARM/global-merge-1.ll b/test/CodeGen/ARM/global-merge-1.ll index 03a9d33..d4d9b0f 100644 --- a/test/CodeGen/ARM/global-merge-1.ll +++ b/test/CodeGen/ARM/global-merge-1.ll @@ -1,10 +1,12 @@ ; RUN: llc %s -O0 -o - | FileCheck -check-prefix=NO-MERGE %s +; RUN: llc %s -O0 -o - -arm-global-merge=false | FileCheck -check-prefix=NO-MERGE %s +; RUN: llc %s -O0 -o - -arm-global-merge=true | FileCheck -check-prefix=MERGE %s ; RUN: llc %s -O1 -o - | FileCheck -check-prefix=NO-MERGE %s -; RUN: llc %s -O1 -o - -enable-global-merge=false | FileCheck -check-prefix=NO-MERGE %s -; RUN: llc %s -O1 -o - -enable-global-merge=true | FileCheck -check-prefix=NO-MERGE %s +; RUN: llc %s -O1 -o - -arm-global-merge=false | FileCheck -check-prefix=NO-MERGE %s +; RUN: llc %s -O1 -o - -arm-global-merge=true | FileCheck -check-prefix=MERGE %s ; RUN: llc %s -O3 -o - | FileCheck -check-prefix=MERGE %s -; RUN: llc %s -O3 -o - -enable-global-merge=false | FileCheck -check-prefix=NO-MERGE %s -; RUN: llc %s -O3 -o - -enable-global-merge=true | FileCheck -check-prefix=MERGE %s +; RUN: llc %s -O3 -o - -arm-global-merge=false | FileCheck -check-prefix=NO-MERGE %s +; RUN: llc %s -O3 -o - -arm-global-merge=true | FileCheck -check-prefix=MERGE %s ; MERGE-NOT: .zerofill __DATA,__bss,_bar,20,2 ; MERGE-NOT: .zerofill __DATA,__bss,_baz,20,2 diff --git a/test/CodeGen/ARM/ifcvt6.ll b/test/CodeGen/ARM/ifcvt6.ll index a00deda..7890193 100644 --- a/test/CodeGen/ARM/ifcvt6.ll +++ b/test/CodeGen/ARM/ifcvt6.ll @@ -10,7 +10,7 @@ entry: br i1 %tmp7, label %cond_true, label %UnifiedReturnBlock cond_true: ; preds = %entry - %tmp10 = call i32 (...)* @bar( ) ; [#uses=0] + %tmp10 = call i32 (...) @bar( ) ; [#uses=0] ret void UnifiedReturnBlock: ; preds = %entry diff --git a/test/CodeGen/ARM/indirectbr-2.ll b/test/CodeGen/ARM/indirectbr-2.ll index 044fb56..ca068db 100644 --- a/test/CodeGen/ARM/indirectbr-2.ll +++ b/test/CodeGen/ARM/indirectbr-2.ll @@ -27,7 +27,7 @@ define i32 @func() nounwind ssp { %9 = load i32, i32* %8 %10 = add i32 %9, ptrtoint (i8* blockaddress(@func, %4) to i32) %11 = inttoptr i32 %10 to i8* - %12 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @0, i32 0, i32 0)) + %12 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([45 x i8], [45 x i8]* @0, i32 0, i32 0)) indirectbr i8* %11, [label %13, label %14] ;