From 33d73eb2bc94ca1dcc02c1afbd56200d46560310 Mon Sep 17 00:00:00 2001
From: Scott Michel <scottm@aero.org>
Date: Fri, 21 Nov 2008 02:56:16 +0000
Subject: CellSPU: (a) Fix bgs 3052, 3057 (b) Incorporate Duncan's suggestions
 re: i1 promotion (c) Indentation updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59790 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/CellSPU/loads.ll  | 20 ++++++++++++++++++++
 test/CodeGen/CellSPU/stores.ll | 22 ++++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 test/CodeGen/CellSPU/loads.ll
 create mode 100644 test/CodeGen/CellSPU/stores.ll

(limited to 'test')

diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll
new file mode 100644
index 0000000..3b9746c
--- /dev/null
+++ b/test/CodeGen/CellSPU/loads.ll
@@ -0,0 +1,20 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep {lqd.*0(\$3)}   %t1.s | count 1
+; RUN: grep {lqd.*16(\$3)}  %t1.s | count 1
+
+; ModuleID = 'loads.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define <4 x float> @load_v4f32_1(<4 x float>* %a) nounwind readonly {
+entry:
+	%tmp1 = load <4 x float>* %a
+	ret <4 x float> %tmp1
+}
+
+define <4 x float> @load_v4f32_2(<4 x float>* %a) nounwind readonly {
+entry:
+	%arrayidx = getelementptr <4 x float>* %a, i32 1		; <<4 x float>*> [#uses=1]
+	%tmp1 = load <4 x float>* %arrayidx		; <<4 x float>> [#uses=1]
+	ret <4 x float> %tmp1
+}
diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll
new file mode 100644
index 0000000..b9534ab
--- /dev/null
+++ b/test/CodeGen/CellSPU/stores.ll
@@ -0,0 +1,22 @@
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep {stqd.*0(\$3)}   %t1.s | count 1
+; RUN: grep {stqd.*16(\$3)}  %t1.s | count 1
+; RUN: grep 16256            %t1.s | count 1
+; RUN: grep 16384            %t1.s | count 1
+
+; ModuleID = 'stores.bc'
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
+target triple = "spu"
+
+define void @store_v4f32_1(<4 x float>* %a) nounwind {
+entry:
+	store <4 x float> < float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00 >, <4 x float>* %a
+	ret void
+}
+
+define void @store_v4f32_2(<4 x float>* %a) nounwind {
+entry:
+	%arrayidx = getelementptr <4 x float>* %a, i32 1
+	store <4 x float> < float 2.000000e+00, float 2.000000e+00, float 2.000000e+00, float 2.000000e+00 >, <4 x float>* %arrayidx
+	ret void
+}
-- 
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