From 433194a604682fd84a49bc9305cbbd472e31d04e Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Thu, 15 Apr 2010 22:20:34 +0000 Subject: Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101410 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'test') diff --git a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll index 329494b..fea2dca 100644 --- a/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll +++ b/test/CodeGen/Thumb2/2010-04-15-DynAllocBug.ll @@ -7,15 +7,15 @@ define arm_apcscc void @t() nounwind ssp { entry: ; CHECK: t: -; CHECK: mvn r0, #7 -; CHECK: ands sp, r0 -; CHECK: mov r1, sp -; CHECK: mov sp, r1 +; CHECK: mov r0, sp +; CHECK: bfc r0, #0, #3 +; CHECK: subs r0, #16 +; CHECK: mov sp, r0 ; Yes, this is stupid codegen, but it's correct. -; CHECK: sub sp, #16 -; CHECK: mov r1, sp -; CHECK: mov sp, r1 -; CHECK: ands sp, r0 +; CHECK: mov r0, sp +; CHECK: bfc r0, #0, #3 +; CHECK: subs r0, #16 +; CHECK: mov sp, r0 %size = mul i32 8, 2 %vla_a = alloca i8, i32 %size, align 8 %vla_b = alloca i8, i32 %size, align 8 -- cgit v1.1