From 47e9fab1584a3fc9311fdecdbb87124e0a0b39e8 Mon Sep 17 00:00:00 2001
From: Evan Cheng <evan.cheng@apple.com>
Date: Fri, 17 Jul 2009 22:13:25 +0000
Subject: Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just
 like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r
 registers. Yeah, that makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76248 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/X86/inline-asm-q-regs.ll | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 test/CodeGen/X86/inline-asm-q-regs.ll

(limited to 'test')

diff --git a/test/CodeGen/X86/inline-asm-q-regs.ll b/test/CodeGen/X86/inline-asm-q-regs.ll
new file mode 100644
index 0000000..19df81b
--- /dev/null
+++ b/test/CodeGen/X86/inline-asm-q-regs.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -march=x86-64
+; rdar://7066579
+
+	type { i64, i64, i64, i64, i64 }		; type %0
+
+define void @t() nounwind {
+entry:
+	%asmtmp = call %0 asm sideeffect "mov    %cr0, $0       \0Amov    %cr2, $1       \0Amov    %cr3, $2       \0Amov    %cr4, $3       \0Amov    %cr8, $0       \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind		; <%0> [#uses=0]
+	ret void
+}
-- 
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