From 61de70d98e1f752d5482b775f08827f799f4a53b Mon Sep 17 00:00:00 2001
From: Jack Carter <jcarter@mips.com>
Date: Mon, 6 Aug 2012 23:29:06 +0000
Subject: The Mips64InstrInfo.td definitions DynAlloc64 LEA_ADDiu64 were using
 a class defined for 32 bit instructions and thus the instruction was for
 addiu instead of daddiu.

This was corrected by adding the instruction opcode as a
field in the  base class to be filled in by the defs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161359 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/MC/Mips/lea_64.ll | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)
 create mode 100644 test/MC/Mips/lea_64.ll

(limited to 'test')

diff --git a/test/MC/Mips/lea_64.ll b/test/MC/Mips/lea_64.ll
new file mode 100644
index 0000000..2e7a37b
--- /dev/null
+++ b/test/MC/Mips/lea_64.ll
@@ -0,0 +1,18 @@
+; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
+; RUN:  | llvm-objdump -disassemble -triple mips64el - \
+; RUN:  | FileCheck %s
+
+@p = external global i32*
+
+define void @f1() nounwind {
+entry:
+; CHECK: .text:
+; CHECK-NOT: addiu {{[0-9,a-f]+}}, {{[0-9,a-f]+}}, {{[0-9]+}}
+
+  %a = alloca [10 x i32], align 4
+  %arraydecay = getelementptr inbounds [10 x i32]* %a, i64 0, i64 0
+  store i32* %arraydecay, i32** @p, align 8
+  ret void
+
+; CHECK: jr $ra
+}
-- 
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