From 7d9c02dc620ea5f5cdf2dc0bd0f03d9370f845d3 Mon Sep 17 00:00:00 2001 From: Bill Wendling Date: Mon, 9 Dec 2013 08:56:18 +0000 Subject: Merging r196751: ------------------------------------------------------------------------ r196751 | venkatra | 2013-12-08 20:02:15 -0800 (Sun, 08 Dec 2013) | 3 lines [Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196766 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/SPARC/64cond.ll | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'test') diff --git a/test/CodeGen/SPARC/64cond.ll b/test/CodeGen/SPARC/64cond.ll index bdc5e70..7451b04 100644 --- a/test/CodeGen/SPARC/64cond.ll +++ b/test/CodeGen/SPARC/64cond.ll @@ -109,3 +109,17 @@ entry: %rv = select i1 %tobool, i64 123, i64 0 ret i64 %rv } + +; CHECK-LABEL: setcc_resultty +; CHECK: cmp +; CHECK: movne %xcc, 1, [[R:%[gilo][0-7]]] +; CHECK: or [[R]], %i1, %i0 + +define i1 @setcc_resultty(i64 %a, i1 %b) { + %a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32) + %a1 = extractvalue { i64, i1 } %a0, 1 + %a4 = or i1 %a1, %b + ret i1 %a4 +} + +declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) -- cgit v1.1