From 97fdff1d3f0d931247aa300a02679681d684b87d Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Fri, 8 Apr 2011 00:29:09 +0000 Subject: Add sanity checking for bad register specifier(s) for the DPFrm instructions. Add more test cases to exercise the logical branches related to the above change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/Disassembler/ARM/arm-tests.txt | 18 ++++++++++++++++++ test/MC/Disassembler/ARM/invalid-BFI-arm.txt | 10 ++++++++++ test/MC/Disassembler/ARM/invalid-SBFX-arm.txt | 10 ++++++++++ test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt | 12 ++++++++++++ 4 files changed, 50 insertions(+) create mode 100644 test/MC/Disassembler/ARM/invalid-BFI-arm.txt create mode 100644 test/MC/Disassembler/ARM/invalid-SBFX-arm.txt create mode 100644 test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt (limited to 'test') diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 3bed28e..86d4f34 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -254,3 +254,21 @@ # CHECK: sxtb r9, r5, ror #8 0x75 0x94 0xaf 0xe6 + +# CHECK: bfc r5, #0, #16 +0x1f 0x50 0xcf 0xe7 + +# CHECK: bfi r5, r6, #0, #16 +0x16 0x50 0xcf 0xe7 + +# CHECK: sbfx r5, r6, #8, #8 +0x56 0x54 0xa7 0xe7 + +# CHECK: rsb pc, r5, r0 +0x00 0xf0 0x65 0xe0 + +# CHECK: uqadd8 r5, r6, r7 +0x97 0x5f 0x66 0xe6 + +# CHECK: uqsax r5, r6, r7 +0x57 0x5f 0x66 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt new file mode 100644 index 0000000..ca0c1ab --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 then UNPREDICTABLE; +0x16 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt new file mode 100644 index 0000000..1ecd87d --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 || n == 15 then UNPREDICTABLE; +0x5f 0x54 0xa7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt b/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt new file mode 100644 index 0000000..d3f508a --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 0: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# DPFrm with bad reg specifier(s) +# +# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; +0x9f 0x5f 0x66 0xe6 -- cgit v1.1