From 9d2b1aef1b5bc8926c66b38f03583a77d015e921 Mon Sep 17 00:00:00 2001 From: Richard Osborne Date: Sun, 27 Jan 2013 20:46:21 +0000 Subject: [XCore] Add missing 1r instructions. These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/Disassembler/XCore/xcore.txt | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'test') diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt index c620587..03b2c9a 100644 --- a/test/MC/Disassembler/XCore/xcore.txt +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -110,6 +110,33 @@ # CHECK: eeu res[r11] 0xfb 0x07 +# CHECK: set dp, r5 +0xe5 0x37 + +# CHECK: set cp, r0 +0xf0 0x37 + +# CHECK: dgetreg r11 +0xeb 0x3f + +# CHECK: edu res[r8] +0xe8 0x07 + +# CHECK: kcall r2 +0xe2 0x47 + +# CHECK: waitef r10 +0xfa 0x0f + +# CHECK: waitet r7 +0xe7 0x0f + +# CHECK: start t[r4] +0xe4 0x1f + +# CHECK: clrpt res[r9] +0xe9 0x87 + # 2r instructions # CHECK: not r1, r8 -- cgit v1.1