From c147c1b994e1187cb471cdb7ee05f5f875eff4e0 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Tue, 30 Apr 2013 23:22:09 +0000 Subject: [mips] Fix handling of instructions which copy to/from accumulator registers. Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/Mips/spill-copy-acreg.ll | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 test/CodeGen/Mips/spill-copy-acreg.ll (limited to 'test') diff --git a/test/CodeGen/Mips/spill-copy-acreg.ll b/test/CodeGen/Mips/spill-copy-acreg.ll new file mode 100644 index 0000000..2ca031a --- /dev/null +++ b/test/CodeGen/Mips/spill-copy-acreg.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mipsel -mattr=+dsp < %s + +@g1 = common global i64 0, align 8 +@g2 = common global i64 0, align 8 +@g3 = common global i64 0, align 8 + +define i64 @test_acreg_copy(i32 %a0, i32 %a1, i32 %a2, i32 %a3) { +entry: + %0 = load i64* @g1, align 8 + %1 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a0, i32 %a1) + %2 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a2, i32 %a3) + store i64 %1, i64* @g1, align 8 + store i64 %2, i64* @g2, align 8 + tail call void @foo1() + store i64 %2, i64* @g3, align 8 + ret i64 %1 +} + +declare i64 @llvm.mips.maddu(i64, i32, i32) + +declare void @foo1() -- cgit v1.1