From ce392eb3ea16b781de89b7ff8f42c39f8b3df30e Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Sat, 22 Aug 2009 03:13:10 +0000 Subject: Make x86 test actually test x86 code generation. Fix the construct on ARM, which was breaking by coincidence, and add a similar testcase for ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/CodeGen/ARM/vshift_split.ll | 8 ++++++++ test/CodeGen/X86/vshift_split.ll | 4 ++-- 2 files changed, 10 insertions(+), 2 deletions(-) create mode 100644 test/CodeGen/ARM/vshift_split.ll (limited to 'test') diff --git a/test/CodeGen/ARM/vshift_split.ll b/test/CodeGen/ARM/vshift_split.ll new file mode 100644 index 0000000..a44db66 --- /dev/null +++ b/test/CodeGen/ARM/vshift_split.ll @@ -0,0 +1,8 @@ +; RUN: llvm-as < %s | llc -march=arm -mattr=-neon + +; Example that requires splitting and expanding a vector shift. +define <2 x i64> @update(<2 x i64> %val) nounwind readnone { +entry: + %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1] + ret <2 x i64> %shr +} diff --git a/test/CodeGen/X86/vshift_split.ll b/test/CodeGen/X86/vshift_split.ll index 8f485dd..a1376e5 100644 --- a/test/CodeGen/X86/vshift_split.ll +++ b/test/CodeGen/X86/vshift_split.ll @@ -1,8 +1,8 @@ -; RUN: llvm-as < %s | llc +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 ; Example that requires splitting and expanding a vector shift. define <2 x i64> @update(<2 x i64> %val) nounwind readnone { entry: - %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1] + %shr = lshr <2 x i64> %val, < i64 2, i64 3 > ret <2 x i64> %shr } -- cgit v1.1