From ebc3938ae717d7352de800344c3ad5a1bceb74e5 Mon Sep 17 00:00:00 2001 From: Amaury de la Vieuville Date: Mon, 24 Jun 2013 09:15:01 +0000 Subject: ARM: check predicate bits for thumb instructions When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and core registers, must have their predicate bit to 0b1110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184707 91177308-0d34-0410-b5e6-96231b3b80d8 --- test/MC/Disassembler/ARM/invalid-NEON-thumb.txt | 9 +++++++++ test/MC/Disassembler/ARM/invalid-VFP-thumb.txt | 9 +++++++++ 2 files changed, 18 insertions(+) create mode 100644 test/MC/Disassembler/ARM/invalid-NEON-thumb.txt create mode 100644 test/MC/Disassembler/ARM/invalid-VFP-thumb.txt (limited to 'test') diff --git a/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt b/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt new file mode 100644 index 0000000..a191d9e --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt @@ -0,0 +1,9 @@ +# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) + +# VMOV +# RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# VDUP +# RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt b/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt new file mode 100644 index 0000000..7a4ddaa --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt @@ -0,0 +1,9 @@ +# VFP instructions with invalid predicate bits (pred != 0b1110) + +# VABS +# RUN: echo "0x40 0xde 0x00 0x0a" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# VMLA +# RUN: echo "0xf0 0xde 0xe0 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding -- cgit v1.1