From ae9f3a3b7c915f725aef5a7250e88eaeddda03c6 Mon Sep 17 00:00:00 2001 From: Anton Korobeynikov Date: Wed, 20 Feb 2008 11:08:44 +0000 Subject: Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47367 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/PerfectShuffle/PerfectShuffle.cpp | 2 +- utils/TableGen/AsmWriterEmitter.cpp | 3 ++- utils/TableGen/CodeGenDAGPatterns.cpp | 4 ++-- utils/TableGen/CodeGenRegisters.h | 3 ++- utils/TableGen/DAGISelEmitter.cpp | 3 ++- utils/TableGen/TGLexer.cpp | 2 ++ 6 files changed, 11 insertions(+), 6 deletions(-) (limited to 'utils') diff --git a/utils/PerfectShuffle/PerfectShuffle.cpp b/utils/PerfectShuffle/PerfectShuffle.cpp index e7b9421..26c4cf44 100644 --- a/utils/PerfectShuffle/PerfectShuffle.cpp +++ b/utils/PerfectShuffle/PerfectShuffle.cpp @@ -17,7 +17,7 @@ #include #include #include - +#include struct Operator; // Masks are 4-nibble hex numbers. Values 0-7 in any nibble means that it takes diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 07ef2e5..5a24b26 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -242,11 +242,12 @@ unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{ unsigned MismatchOperand = ~0U; for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i] != Other.Operands[i]) + if (Operands[i] != Other.Operands[i]) { if (MismatchOperand != ~0U) // Already have one mismatch? return ~1U; else MismatchOperand = i; + } } return MismatchOperand; } diff --git a/utils/TableGen/CodeGenDAGPatterns.cpp b/utils/TableGen/CodeGenDAGPatterns.cpp index ddfaaac..0faaa72 100644 --- a/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/utils/TableGen/CodeGenDAGPatterns.cpp @@ -1342,14 +1342,14 @@ void CodeGenDAGPatterns::ParseDefaultOperands() { while (TPN->ApplyTypeConstraints(P, false)) /* Resolve all types */; - if (TPN->ContainsUnresolvedType()) + if (TPN->ContainsUnresolvedType()) { if (iter == 0) throw "Value #" + utostr(i) + " of PredicateOperand '" + DefaultOps[iter][i]->getName() + "' doesn't have a concrete type!"; else throw "Value #" + utostr(i) + " of OptionalDefOperand '" + DefaultOps[iter][i]->getName() + "' doesn't have a concrete type!"; - + } DefaultOpInfo.DefaultOps.push_back(TPN); } diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index 4efae78..0f1b501 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -15,9 +15,10 @@ #ifndef CODEGEN_REGISTERS_H #define CODEGEN_REGISTERS_H +#include "llvm/CodeGen/ValueTypes.h" #include #include -#include "llvm/CodeGen/ValueTypes.h" +#include namespace llvm { class Record; diff --git a/utils/TableGen/DAGISelEmitter.cpp b/utils/TableGen/DAGISelEmitter.cpp index bdf6b64..6f562fa 100644 --- a/utils/TableGen/DAGISelEmitter.cpp +++ b/utils/TableGen/DAGISelEmitter.cpp @@ -1123,7 +1123,7 @@ public: Code += "), 0"; emitCode(Code2 + Code + ");"); - if (NodeHasChain) + if (NodeHasChain) { // Remember which op produces the chain. if (!isRoot) emitCode(ChainName + " = SDOperand(" + NodeName + @@ -1131,6 +1131,7 @@ public: else emitCode(ChainName + " = SDOperand(" + NodeName + ", " + utostr(NumResults+NumDstRegs) + ");"); + } if (!isRoot) { NodeOps.push_back("Tmp" + utostr(ResNo)); diff --git a/utils/TableGen/TGLexer.cpp b/utils/TableGen/TGLexer.cpp index 9fa696e..2af35b0 100644 --- a/utils/TableGen/TGLexer.cpp +++ b/utils/TableGen/TGLexer.cpp @@ -17,6 +17,8 @@ #include #include "llvm/Config/config.h" #include +#include +#include using namespace llvm; TGLexer::TGLexer(MemoryBuffer *StartBuf) : CurLineNo(1), CurBuf(StartBuf) { -- cgit v1.1