//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // This file was originally auto-generated from a GPU register header file and // all the instruction definitions were originally commented out. Instructions // that are not yet supported remain commented out. //===----------------------------------------------------------------------===// class InterpSlots { int P0 = 2; int P10 = 0; int P20 = 1; } def INTERP : InterpSlots; def InterpSlot : Operand { let PrintMethod = "printInterpSlot"; } def SendMsgImm : Operand { let PrintMethod = "printSendMsg"; } def isGCN : Predicate<"Subtarget->getGeneration() " ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; def isSI : Predicate<"Subtarget->getGeneration() " "== AMDGPUSubtarget::SOUTHERN_ISLANDS">; def isSICI : Predicate< "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS" >; def isCI : Predicate<"Subtarget->getGeneration() " ">= AMDGPUSubtarget::SEA_ISLANDS">; def isVI : Predicate < "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS" >; def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">; def SWaitMatchClass : AsmOperandClass { let Name = "SWaitCnt"; let RenderMethod = "addImmOperands"; let ParserMethod = "parseSWaitCntOps"; } def WAIT_FLAG : InstFlag<"printWaitFlag"> { let ParserMatchClass = SWaitMatchClass; } let SubtargetPredicate = isGCN in { //===----------------------------------------------------------------------===// // EXP Instructions //===----------------------------------------------------------------------===// defm EXP : EXP_m; //===----------------------------------------------------------------------===// // SMRD Instructions //===----------------------------------------------------------------------===// let mayLoad = 1 in { // We are using the SGPR_32 and not the SReg_32 register class for 32-bit // SMRD instructions, because the SGPR_32 register class does not include M0 // and writing to M0 from an SMRD instruction will hang the GPU. defm S_LOAD_DWORD : SMRD_Helper <0x00, "s_load_dword", SReg_64, SGPR_32>; defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "s_load_dwordx2", SReg_64, SReg_64>; defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "s_load_dwordx4", SReg_64, SReg_128>; defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "s_load_dwordx8", SReg_64, SReg_256>; defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "s_load_dwordx16", SReg_64, SReg_512>; defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 0x08, "s_buffer_load_dword", SReg_128, SGPR_32 >; defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 0x09, "s_buffer_load_dwordx2", SReg_128, SReg_64 >; defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 0x0a, "s_buffer_load_dwordx4", SReg_128, SReg_128 >; defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 0x0b, "s_buffer_load_dwordx8", SReg_128, SReg_256 >; defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 0x0c, "s_buffer_load_dwordx16", SReg_128, SReg_512 >; } // mayLoad = 1 //def S_MEMTIME : SMRD_ <0x0000001e, "s_memtime", []>; //def S_DCACHE_INV : SMRD_ <0x0000001f, "s_dcache_inv", []>; //===----------------------------------------------------------------------===// // SOP1 Instructions //===----------------------------------------------------------------------===// let isMoveImm = 1 in { let isReMaterializable = 1 in { defm S_MOV_B32 : SOP1_32 , "s_mov_b32", []>; defm S_MOV_B64 : SOP1_64 , "s_mov_b64", []>; } // let isRematerializeable = 1 let Uses = [SCC] in { defm S_CMOV_B32 : SOP1_32 , "s_cmov_b32", []>; defm S_CMOV_B64 : SOP1_64 , "s_cmov_b64", []>; } // End Uses = [SCC] } // End isMoveImm = 1 let Defs = [SCC] in { defm S_NOT_B32 : SOP1_32 , "s_not_b32", [(set i32:$dst, (not i32:$src0))] >; defm S_NOT_B64 : SOP1_64 , "s_not_b64", [(set i64:$dst, (not i64:$src0))] >; defm S_WQM_B32 : SOP1_32 , "s_wqm_b32", []>; defm S_WQM_B64 : SOP1_64 , "s_wqm_b64", []>; } // End Defs = [SCC] defm S_BREV_B32 : SOP1_32 , "s_brev_b32", [(set i32:$dst, (AMDGPUbrev i32:$src0))] >; defm S_BREV_B64 : SOP1_64 , "s_brev_b64", []>; let Defs = [SCC] in { defm S_BCNT0_I32_B32 : SOP1_32 , "s_bcnt0_i32_b32", []>; defm S_BCNT0_I32_B64 : SOP1_32_64 , "s_bcnt0_i32_b64", []>; defm S_BCNT1_I32_B32 : SOP1_32 , "s_bcnt1_i32_b32", [(set i32:$dst, (ctpop i32:$src0))] >; defm S_BCNT1_I32_B64 : SOP1_32_64 , "s_bcnt1_i32_b64", []>; } // End Defs = [SCC] defm S_FF0_I32_B32 : SOP1_32 , "s_ff0_i32_b32", []>; defm S_FF0_I32_B64 : SOP1_32_64 , "s_ff0_i32_b64", []>; defm S_FF1_I32_B32 : SOP1_32 , "s_ff1_i32_b32", [(set i32:$dst, (cttz_zero_undef i32:$src0))] >; defm S_FF1_I32_B64 : SOP1_32_64 , "s_ff1_i32_b64", []>; defm S_FLBIT_I32_B32 : SOP1_32 , "s_flbit_i32_b32", [(set i32:$dst, (ctlz_zero_undef i32:$src0))] >; defm S_FLBIT_I32_B64 : SOP1_32_64 , "s_flbit_i32_b64", []>; defm S_FLBIT_I32 : SOP1_32 , "s_flbit_i32", [(set i32:$dst, (int_AMDGPU_flbit_i32 i32:$src0))] >; defm S_FLBIT_I32_I64 : SOP1_32_64 , "s_flbit_i32_i64", []>; defm S_SEXT_I32_I8 : SOP1_32 , "s_sext_i32_i8", [(set i32:$dst, (sext_inreg i32:$src0, i8))] >; defm S_SEXT_I32_I16 : SOP1_32 , "s_sext_i32_i16", [(set i32:$dst, (sext_inreg i32:$src0, i16))] >; defm S_BITSET0_B32 : SOP1_32 , "s_bitset0_b32", []>; defm S_BITSET0_B64 : SOP1_64 , "s_bitset0_b64", []>; defm S_BITSET1_B32 : SOP1_32 , "s_bitset1_b32", []>; defm S_BITSET1_B64 : SOP1_64 , "s_bitset1_b64", []>; defm S_GETPC_B64 : SOP1_64_0 , "s_getpc_b64", []>; defm S_SETPC_B64 : SOP1_64 , "s_setpc_b64", []>; defm S_SWAPPC_B64 : SOP1_64 , "s_swappc_b64", []>; defm S_RFE_B64 : SOP1_64 , "s_rfe_b64", []>; let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in { defm S_AND_SAVEEXEC_B64 : SOP1_64 , "s_and_saveexec_b64", []>; defm S_OR_SAVEEXEC_B64 : SOP1_64 , "s_or_saveexec_b64", []>; defm S_XOR_SAVEEXEC_B64 : SOP1_64 , "s_xor_saveexec_b64", []>; defm S_ANDN2_SAVEEXEC_B64 : SOP1_64 , "s_andn2_saveexec_b64", []>; defm S_ORN2_SAVEEXEC_B64 : SOP1_64 , "s_orn2_saveexec_b64", []>; defm S_NAND_SAVEEXEC_B64 : SOP1_64 , "s_nand_saveexec_b64", []>; defm S_NOR_SAVEEXEC_B64 : SOP1_64 , "s_nor_saveexec_b64", []>; defm S_XNOR_SAVEEXEC_B64 : SOP1_64 , "s_xnor_saveexec_b64", []>; } // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] defm S_QUADMASK_B32 : SOP1_32 , "s_quadmask_b32", []>; defm S_QUADMASK_B64 : SOP1_64 , "s_quadmask_b64", []>; defm S_MOVRELS_B32 : SOP1_32 , "s_movrels_b32", []>; defm S_MOVRELS_B64 : SOP1_64 , "s_movrels_b64", []>; defm S_MOVRELD_B32 : SOP1_32 , "s_movreld_b32", []>; defm S_MOVRELD_B64 : SOP1_64 , "s_movreld_b64", []>; defm S_CBRANCH_JOIN : SOP1_1 , "s_cbranch_join", []>; defm S_MOV_REGRD_B32 : SOP1_32 , "s_mov_regrd_b32", []>; let Defs = [SCC] in { defm S_ABS_I32 : SOP1_32 , "s_abs_i32", []>; } // End Defs = [SCC] defm S_MOV_FED_B32 : SOP1_32 , "s_mov_fed_b32", []>; //===----------------------------------------------------------------------===// // SOP2 Instructions //===----------------------------------------------------------------------===// let Defs = [SCC] in { // Carry out goes to SCC let isCommutable = 1 in { defm S_ADD_U32 : SOP2_32 , "s_add_u32", []>; defm S_ADD_I32 : SOP2_32 , "s_add_i32", [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] >; } // End isCommutable = 1 defm S_SUB_U32 : SOP2_32 , "s_sub_u32", []>; defm S_SUB_I32 : SOP2_32 , "s_sub_i32", [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] >; let Uses = [SCC] in { // Carry in comes from SCC let isCommutable = 1 in { defm S_ADDC_U32 : SOP2_32 , "s_addc_u32", [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; } // End isCommutable = 1 defm S_SUBB_U32 : SOP2_32 , "s_subb_u32", [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; } // End Uses = [SCC] defm S_MIN_I32 : SOP2_32 , "s_min_i32", [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] >; defm S_MIN_U32 : SOP2_32 , "s_min_u32", [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] >; defm S_MAX_I32 : SOP2_32 , "s_max_i32", [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] >; defm S_MAX_U32 : SOP2_32 , "s_max_u32", [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] >; } // End Defs = [SCC] defm S_CSELECT_B32 : SOP2_SELECT_32 , "s_cselect_b32", []>; let Uses = [SCC] in { defm S_CSELECT_B64 : SOP2_64 , "s_cselect_b64", []>; } // End Uses = [SCC] let Defs = [SCC] in { defm S_AND_B32 : SOP2_32 , "s_and_b32", [(set i32:$dst, (and i32:$src0, i32:$src1))] >; defm S_AND_B64 : SOP2_64 , "s_and_b64", [(set i64:$dst, (and i64:$src0, i64:$src1))] >; defm S_OR_B32 : SOP2_32 , "s_or_b32", [(set i32:$dst, (or i32:$src0, i32:$src1))] >; defm S_OR_B64 : SOP2_64 , "s_or_b64", [(set i64:$dst, (or i64:$src0, i64:$src1))] >; defm S_XOR_B32 : SOP2_32 , "s_xor_b32", [(set i32:$dst, (xor i32:$src0, i32:$src1))] >; defm S_XOR_B64 : SOP2_64 , "s_xor_b64", [(set i64:$dst, (xor i64:$src0, i64:$src1))] >; defm S_ANDN2_B32 : SOP2_32 , "s_andn2_b32", []>; defm S_ANDN2_B64 : SOP2_64 , "s_andn2_b64", []>; defm S_ORN2_B32 : SOP2_32 , "s_orn2_b32", []>; defm S_ORN2_B64 : SOP2_64 , "s_orn2_b64", []>; defm S_NAND_B32 : SOP2_32 , "s_nand_b32", []>; defm S_NAND_B64 : SOP2_64 , "s_nand_b64", []>; defm S_NOR_B32 : SOP2_32 , "s_nor_b32", []>; defm S_NOR_B64 : SOP2_64 , "s_nor_b64", []>; defm S_XNOR_B32 : SOP2_32 , "s_xnor_b32", []>; defm S_XNOR_B64 : SOP2_64 , "s_xnor_b64", []>; } // End Defs = [SCC] // Use added complexity so these patterns are preferred to the VALU patterns. let AddedComplexity = 1 in { let Defs = [SCC] in { defm S_LSHL_B32 : SOP2_32 , "s_lshl_b32", [(set i32:$dst, (shl i32:$src0, i32:$src1))] >; defm S_LSHL_B64 : SOP2_64_32 , "s_lshl_b64", [(set i64:$dst, (shl i64:$src0, i32:$src1))] >; defm S_LSHR_B32 : SOP2_32 , "s_lshr_b32", [(set i32:$dst, (srl i32:$src0, i32:$src1))] >; defm S_LSHR_B64 : SOP2_64_32 , "s_lshr_b64", [(set i64:$dst, (srl i64:$src0, i32:$src1))] >; defm S_ASHR_I32 : SOP2_32 , "s_ashr_i32", [(set i32:$dst, (sra i32:$src0, i32:$src1))] >; defm S_ASHR_I64 : SOP2_64_32 , "s_ashr_i64", [(set i64:$dst, (sra i64:$src0, i32:$src1))] >; } // End Defs = [SCC] defm S_BFM_B32 : SOP2_32 , "s_bfm_b32", [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>; defm S_BFM_B64 : SOP2_64 , "s_bfm_b64", []>; defm S_MUL_I32 : SOP2_32 , "s_mul_i32", [(set i32:$dst, (mul i32:$src0, i32:$src1))] >; } // End AddedComplexity = 1 let Defs = [SCC] in { defm S_BFE_U32 : SOP2_32 , "s_bfe_u32", []>; defm S_BFE_I32 : SOP2_32 , "s_bfe_i32", []>; defm S_BFE_U64 : SOP2_64 , "s_bfe_u64", []>; defm S_BFE_I64 : SOP2_64_32 , "s_bfe_i64", []>; } // End Defs = [SCC] let sdst = 0 in { defm S_CBRANCH_G_FORK : SOP2_m < sop2<0x2b, 0x29>, "s_cbranch_g_fork", (outs), (ins SReg_64:$src0, SReg_64:$src1), "s_cbranch_g_fork $src0, $src1", [] >; } let Defs = [SCC] in { defm S_ABSDIFF_I32 : SOP2_32 , "s_absdiff_i32", []>; } // End Defs = [SCC] //===----------------------------------------------------------------------===// // SOPC Instructions //===----------------------------------------------------------------------===// def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32">; def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32">; def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32">; def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32">; def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32">; def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32">; def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32">; def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32">; def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32">; def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32">; def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32">; def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32">; ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>; ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>; ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>; ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>; //def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>; //===----------------------------------------------------------------------===// // SOPK Instructions //===----------------------------------------------------------------------===// let isReMaterializable = 1 in { defm S_MOVK_I32 : SOPK_32 , "s_movk_i32", []>; } // End isReMaterializable = 1 let Uses = [SCC] in { defm S_CMOVK_I32 : SOPK_32 , "s_cmovk_i32", []>; } let isCompare = 1 in { /* This instruction is disabled for now until we can figure out how to teach the instruction selector to correctly use the S_CMP* vs V_CMP* instructions. When this instruction is enabled the code generator sometimes produces this invalid sequence: SCC = S_CMPK_EQ_I32 SGPR0, imm VCC = COPY SCC VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 defm S_CMPK_EQ_I32 : SOPK_SCC , "s_cmpk_eq_i32", [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] >; */ defm S_CMPK_LG_I32 : SOPK_SCC , "s_cmpk_lg_i32", []>; defm S_CMPK_GT_I32 : SOPK_SCC , "s_cmpk_gt_i32", []>; defm S_CMPK_GE_I32 : SOPK_SCC , "s_cmpk_ge_i32", []>; defm S_CMPK_LT_I32 : SOPK_SCC , "s_cmpk_lt_i32", []>; defm S_CMPK_LE_I32 : SOPK_SCC , "s_cmpk_le_i32", []>; defm S_CMPK_EQ_U32 : SOPK_SCC , "s_cmpk_eq_u32", []>; defm S_CMPK_LG_U32 : SOPK_SCC , "s_cmpk_lg_u32", []>; defm S_CMPK_GT_U32 : SOPK_SCC , "s_cmpk_gt_u32", []>; defm S_CMPK_GE_U32 : SOPK_SCC , "s_cmpk_ge_u32", []>; defm S_CMPK_LT_U32 : SOPK_SCC , "s_cmpk_lt_u32", []>; defm S_CMPK_LE_U32 : SOPK_SCC , "s_cmpk_le_u32", []>; } // End isCompare = 1 let isCommutable = 1 in { let Defs = [SCC], isCommutable = 1 in { defm S_ADDK_I32 : SOPK_32 , "s_addk_i32", []>; } defm S_MULK_I32 : SOPK_32 , "s_mulk_i32", []>; } //defm S_CBRANCH_I_FORK : SOPK_ , "s_cbranch_i_fork", []>; defm S_GETREG_B32 : SOPK_32 , "s_getreg_b32", []>; defm S_SETREG_B32 : SOPK_32 , "s_setreg_b32", []>; defm S_GETREG_REGRD_B32 : SOPK_32 , "s_getreg_regrd_b32", []>; //defm S_SETREG_IMM32_B32 : SOPK_32 , "s_setreg_imm32_b32", []>; //===----------------------------------------------------------------------===// // SOPP Instructions //===----------------------------------------------------------------------===// def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">; let isTerminator = 1 in { def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm", [(IL_retflag)]> { let simm16 = 0; let isBarrier = 1; let hasCtrlDep = 1; } let isBranch = 1 in { def S_BRANCH : SOPP < 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16", [(br bb:$simm16)]> { let isBarrier = 1; } let DisableEncoding = "$scc" in { def S_CBRANCH_SCC0 : SOPP < 0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc), "s_cbranch_scc0 $simm16" >; def S_CBRANCH_SCC1 : SOPP < 0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc), "s_cbranch_scc1 $simm16" >; } // End DisableEncoding = "$scc" def S_CBRANCH_VCCZ : SOPP < 0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc), "s_cbranch_vccz $simm16" >; def S_CBRANCH_VCCNZ : SOPP < 0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc), "s_cbranch_vccnz $simm16" >; let DisableEncoding = "$exec" in { def S_CBRANCH_EXECZ : SOPP < 0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec), "s_cbranch_execz $simm16" >; def S_CBRANCH_EXECNZ : SOPP < 0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec), "s_cbranch_execnz $simm16" >; } // End DisableEncoding = "$exec" } // End isBranch = 1 } // End isTerminator = 1 let hasSideEffects = 1 in { def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier", [(int_AMDGPU_barrier_local)] > { let simm16 = 0; let isBarrier = 1; let hasCtrlDep = 1; let mayLoad = 1; let mayStore = 1; } def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">; def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">; def S_SLEEP : SOPP <0x0000000e, (ins i16imm:$simm16), "s_sleep $simm16">; def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$sim16), "s_setprio $sim16">; let Uses = [EXEC] in { def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "s_sendmsg $simm16", [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)] > { let DisableEncoding = "$m0"; } } // End Uses = [EXEC] def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">; def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">; def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> { let simm16 = 0; } def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">; def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">; def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> { let simm16 = 0; } } // End hasSideEffects //===----------------------------------------------------------------------===// // VOPC Instructions //===----------------------------------------------------------------------===// let isCompare = 1, isCommutable = 1 in { defm V_CMP_F_F32 : VOPC_F32 , "v_cmp_f_f32">; defm V_CMP_LT_F32 : VOPC_F32 , "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; defm V_CMP_EQ_F32 : VOPC_F32 , "v_cmp_eq_f32", COND_OEQ>; defm V_CMP_LE_F32 : VOPC_F32 , "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">; defm V_CMP_GT_F32 : VOPC_F32 , "v_cmp_gt_f32", COND_OGT>; defm V_CMP_LG_F32 : VOPC_F32 , "v_cmp_lg_f32", COND_ONE>; defm V_CMP_GE_F32 : VOPC_F32 , "v_cmp_ge_f32", COND_OGE>; defm V_CMP_O_F32 : VOPC_F32 , "v_cmp_o_f32", COND_O>; defm V_CMP_U_F32 : VOPC_F32 , "v_cmp_u_f32", COND_UO>; defm V_CMP_NGE_F32 : VOPC_F32 , "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">; defm V_CMP_NLG_F32 : VOPC_F32 , "v_cmp_nlg_f32", COND_UEQ>; defm V_CMP_NGT_F32 : VOPC_F32 , "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">; defm V_CMP_NLE_F32 : VOPC_F32 , "v_cmp_nle_f32", COND_UGT>; defm V_CMP_NEQ_F32 : VOPC_F32 , "v_cmp_neq_f32", COND_UNE>; defm V_CMP_NLT_F32 : VOPC_F32 , "v_cmp_nlt_f32", COND_UGE>; defm V_CMP_TRU_F32 : VOPC_F32 , "v_cmp_tru_f32">; defm V_CMPX_F_F32 : VOPCX_F32 , "v_cmpx_f_f32">; defm V_CMPX_LT_F32 : VOPCX_F32 , "v_cmpx_lt_f32", "v_cmpx_gt_f32">; defm V_CMPX_EQ_F32 : VOPCX_F32 , "v_cmpx_eq_f32">; defm V_CMPX_LE_F32 : VOPCX_F32 , "v_cmpx_le_f32", "v_cmpx_ge_f32">; defm V_CMPX_GT_F32 : VOPCX_F32 , "v_cmpx_gt_f32">; defm V_CMPX_LG_F32 : VOPCX_F32 , "v_cmpx_lg_f32">; defm V_CMPX_GE_F32 : VOPCX_F32 , "v_cmpx_ge_f32">; defm V_CMPX_O_F32 : VOPCX_F32 , "v_cmpx_o_f32">; defm V_CMPX_U_F32 : VOPCX_F32 , "v_cmpx_u_f32">; defm V_CMPX_NGE_F32 : VOPCX_F32 , "v_cmpx_nge_f32">; defm V_CMPX_NLG_F32 : VOPCX_F32 , "v_cmpx_nlg_f32">; defm V_CMPX_NGT_F32 : VOPCX_F32 , "v_cmpx_ngt_f32">; defm V_CMPX_NLE_F32 : VOPCX_F32 , "v_cmpx_nle_f32">; defm V_CMPX_NEQ_F32 : VOPCX_F32 , "v_cmpx_neq_f32">; defm V_CMPX_NLT_F32 : VOPCX_F32 , "v_cmpx_nlt_f32">; defm V_CMPX_TRU_F32 : VOPCX_F32 , "v_cmpx_tru_f32">; defm V_CMP_F_F64 : VOPC_F64 , "v_cmp_f_f64">; defm V_CMP_LT_F64 : VOPC_F64 , "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">; defm V_CMP_EQ_F64 : VOPC_F64 , "v_cmp_eq_f64", COND_OEQ>; defm V_CMP_LE_F64 : VOPC_F64 , "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">; defm V_CMP_GT_F64 : VOPC_F64 , "v_cmp_gt_f64", COND_OGT>; defm V_CMP_LG_F64 : VOPC_F64 , "v_cmp_lg_f64", COND_ONE>; defm V_CMP_GE_F64 : VOPC_F64 , "v_cmp_ge_f64", COND_OGE>; defm V_CMP_O_F64 : VOPC_F64 , "v_cmp_o_f64", COND_O>; defm V_CMP_U_F64 : VOPC_F64 , "v_cmp_u_f64", COND_UO>; defm V_CMP_NGE_F64 : VOPC_F64 , "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">; defm V_CMP_NLG_F64 : VOPC_F64 , "v_cmp_nlg_f64", COND_UEQ>; defm V_CMP_NGT_F64 : VOPC_F64 , "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">; defm V_CMP_NLE_F64 : VOPC_F64 , "v_cmp_nle_f64", COND_UGT>; defm V_CMP_NEQ_F64 : VOPC_F64 , "v_cmp_neq_f64", COND_UNE>; defm V_CMP_NLT_F64 : VOPC_F64 , "v_cmp_nlt_f64", COND_UGE>; defm V_CMP_TRU_F64 : VOPC_F64 , "v_cmp_tru_f64">; defm V_CMPX_F_F64 : VOPCX_F64 , "v_cmpx_f_f64">; defm V_CMPX_LT_F64 : VOPCX_F64 , "v_cmpx_lt_f64", "v_cmpx_gt_f64">; defm V_CMPX_EQ_F64 : VOPCX_F64 , "v_cmpx_eq_f64">; defm V_CMPX_LE_F64 : VOPCX_F64 , "v_cmpx_le_f64", "v_cmpx_ge_f64">; defm V_CMPX_GT_F64 : VOPCX_F64 , "v_cmpx_gt_f64">; defm V_CMPX_LG_F64 : VOPCX_F64 , "v_cmpx_lg_f64">; defm V_CMPX_GE_F64 : VOPCX_F64 , "v_cmpx_ge_f64">; defm V_CMPX_O_F64 : VOPCX_F64 , "v_cmpx_o_f64">; defm V_CMPX_U_F64 : VOPCX_F64 , "v_cmpx_u_f64">; defm V_CMPX_NGE_F64 : VOPCX_F64 , "v_cmpx_nge_f64", "v_cmpx_nle_f64">; defm V_CMPX_NLG_F64 : VOPCX_F64 , "v_cmpx_nlg_f64">; defm V_CMPX_NGT_F64 : VOPCX_F64 , "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">; defm V_CMPX_NLE_F64 : VOPCX_F64 , "v_cmpx_nle_f64">; defm V_CMPX_NEQ_F64 : VOPCX_F64 , "v_cmpx_neq_f64">; defm V_CMPX_NLT_F64 : VOPCX_F64 , "v_cmpx_nlt_f64">; defm V_CMPX_TRU_F64 : VOPCX_F64 , "v_cmpx_tru_f64">; let SubtargetPredicate = isSICI in { defm V_CMPS_F_F32 : VOPC_F32 , "v_cmps_f_f32">; defm V_CMPS_LT_F32 : VOPC_F32 , "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">; defm V_CMPS_EQ_F32 : VOPC_F32 , "v_cmps_eq_f32">; defm V_CMPS_LE_F32 : VOPC_F32 , "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">; defm V_CMPS_GT_F32 : VOPC_F32 , "v_cmps_gt_f32">; defm V_CMPS_LG_F32 : VOPC_F32 , "v_cmps_lg_f32">; defm V_CMPS_GE_F32 : VOPC_F32 , "v_cmps_ge_f32">; defm V_CMPS_O_F32 : VOPC_F32 , "v_cmps_o_f32">; defm V_CMPS_U_F32 : VOPC_F32 , "v_cmps_u_f32">; defm V_CMPS_NGE_F32 : VOPC_F32 , "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">; defm V_CMPS_NLG_F32 : VOPC_F32 , "v_cmps_nlg_f32">; defm V_CMPS_NGT_F32 : VOPC_F32 , "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">; defm V_CMPS_NLE_F32 : VOPC_F32 , "v_cmps_nle_f32">; defm V_CMPS_NEQ_F32 : VOPC_F32 , "v_cmps_neq_f32">; defm V_CMPS_NLT_F32 : VOPC_F32 , "v_cmps_nlt_f32">; defm V_CMPS_TRU_F32 : VOPC_F32 , "v_cmps_tru_f32">; defm V_CMPSX_F_F32 : VOPCX_F32 , "v_cmpsx_f_f32">; defm V_CMPSX_LT_F32 : VOPCX_F32 , "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">; defm V_CMPSX_EQ_F32 : VOPCX_F32 , "v_cmpsx_eq_f32">; defm V_CMPSX_LE_F32 : VOPCX_F32 , "v_cmpsx_le_f32", "v_cmpsx_ge_f32">; defm V_CMPSX_GT_F32 : VOPCX_F32 , "v_cmpsx_gt_f32">; defm V_CMPSX_LG_F32 : VOPCX_F32 , "v_cmpsx_lg_f32">; defm V_CMPSX_GE_F32 : VOPCX_F32 , "v_cmpsx_ge_f32">; defm V_CMPSX_O_F32 : VOPCX_F32 , "v_cmpsx_o_f32">; defm V_CMPSX_U_F32 : VOPCX_F32 , "v_cmpsx_u_f32">; defm V_CMPSX_NGE_F32 : VOPCX_F32 , "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">; defm V_CMPSX_NLG_F32 : VOPCX_F32 , "v_cmpsx_nlg_f32">; defm V_CMPSX_NGT_F32 : VOPCX_F32 , "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">; defm V_CMPSX_NLE_F32 : VOPCX_F32 , "v_cmpsx_nle_f32">; defm V_CMPSX_NEQ_F32 : VOPCX_F32 , "v_cmpsx_neq_f32">; defm V_CMPSX_NLT_F32 : VOPCX_F32 , "v_cmpsx_nlt_f32">; defm V_CMPSX_TRU_F32 : VOPCX_F32 , "v_cmpsx_tru_f32">; defm V_CMPS_F_F64 : VOPC_F64 , "v_cmps_f_f64">; defm V_CMPS_LT_F64 : VOPC_F64 , "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">; defm V_CMPS_EQ_F64 : VOPC_F64 , "v_cmps_eq_f64">; defm V_CMPS_LE_F64 : VOPC_F64 , "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">; defm V_CMPS_GT_F64 : VOPC_F64 , "v_cmps_gt_f64">; defm V_CMPS_LG_F64 : VOPC_F64 , "v_cmps_lg_f64">; defm V_CMPS_GE_F64 : VOPC_F64 , "v_cmps_ge_f64">; defm V_CMPS_O_F64 : VOPC_F64 , "v_cmps_o_f64">; defm V_CMPS_U_F64 : VOPC_F64 , "v_cmps_u_f64">; defm V_CMPS_NGE_F64 : VOPC_F64 , "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">; defm V_CMPS_NLG_F64 : VOPC_F64 , "v_cmps_nlg_f64">; defm V_CMPS_NGT_F64 : VOPC_F64 , "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">; defm V_CMPS_NLE_F64 : VOPC_F64 , "v_cmps_nle_f64">; defm V_CMPS_NEQ_F64 : VOPC_F64 , "v_cmps_neq_f64">; defm V_CMPS_NLT_F64 : VOPC_F64 , "v_cmps_nlt_f64">; defm V_CMPS_TRU_F64 : VOPC_F64 , "v_cmps_tru_f64">; defm V_CMPSX_F_F64 : VOPCX_F64 , "v_cmpsx_f_f64">; defm V_CMPSX_LT_F64 : VOPCX_F64 , "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">; defm V_CMPSX_EQ_F64 : VOPCX_F64 , "v_cmpsx_eq_f64">; defm V_CMPSX_LE_F64 : VOPCX_F64 , "v_cmpsx_le_f64", "v_cmpsx_ge_f64">; defm V_CMPSX_GT_F64 : VOPCX_F64 , "v_cmpsx_gt_f64">; defm V_CMPSX_LG_F64 : VOPCX_F64 , "v_cmpsx_lg_f64">; defm V_CMPSX_GE_F64 : VOPCX_F64 , "v_cmpsx_ge_f64">; defm V_CMPSX_O_F64 : VOPCX_F64 , "v_cmpsx_o_f64">; defm V_CMPSX_U_F64 : VOPCX_F64 , "v_cmpsx_u_f64">; defm V_CMPSX_NGE_F64 : VOPCX_F64 , "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">; defm V_CMPSX_NLG_F64 : VOPCX_F64 , "v_cmpsx_nlg_f64">; defm V_CMPSX_NGT_F64 : VOPCX_F64 , "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">; defm V_CMPSX_NLE_F64 : VOPCX_F64 , "v_cmpsx_nle_f64">; defm V_CMPSX_NEQ_F64 : VOPCX_F64 , "v_cmpsx_neq_f64">; defm V_CMPSX_NLT_F64 : VOPCX_F64 , "v_cmpsx_nlt_f64">; defm V_CMPSX_TRU_F64 : VOPCX_F64 , "v_cmpsx_tru_f64">; } // End SubtargetPredicate = isSICI defm V_CMP_F_I32 : VOPC_I32 , "v_cmp_f_i32">; defm V_CMP_LT_I32 : VOPC_I32 , "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">; defm V_CMP_EQ_I32 : VOPC_I32 , "v_cmp_eq_i32", COND_EQ>; defm V_CMP_LE_I32 : VOPC_I32 , "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">; defm V_CMP_GT_I32 : VOPC_I32 , "v_cmp_gt_i32", COND_SGT>; defm V_CMP_NE_I32 : VOPC_I32 , "v_cmp_ne_i32", COND_NE>; defm V_CMP_GE_I32 : VOPC_I32 , "v_cmp_ge_i32", COND_SGE>; defm V_CMP_T_I32 : VOPC_I32 , "v_cmp_t_i32">; defm V_CMPX_F_I32 : VOPCX_I32 , "v_cmpx_f_i32">; defm V_CMPX_LT_I32 : VOPCX_I32 , "v_cmpx_lt_i32", "v_cmpx_gt_i32">; defm V_CMPX_EQ_I32 : VOPCX_I32 , "v_cmpx_eq_i32">; defm V_CMPX_LE_I32 : VOPCX_I32 , "v_cmpx_le_i32", "v_cmpx_ge_i32">; defm V_CMPX_GT_I32 : VOPCX_I32 , "v_cmpx_gt_i32">; defm V_CMPX_NE_I32 : VOPCX_I32 , "v_cmpx_ne_i32">; defm V_CMPX_GE_I32 : VOPCX_I32 , "v_cmpx_ge_i32">; defm V_CMPX_T_I32 : VOPCX_I32 , "v_cmpx_t_i32">; defm V_CMP_F_I64 : VOPC_I64 , "v_cmp_f_i64">; defm V_CMP_LT_I64 : VOPC_I64 , "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">; defm V_CMP_EQ_I64 : VOPC_I64 , "v_cmp_eq_i64", COND_EQ>; defm V_CMP_LE_I64 : VOPC_I64 , "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">; defm V_CMP_GT_I64 : VOPC_I64 , "v_cmp_gt_i64", COND_SGT>; defm V_CMP_NE_I64 : VOPC_I64 , "v_cmp_ne_i64", COND_NE>; defm V_CMP_GE_I64 : VOPC_I64 , "v_cmp_ge_i64", COND_SGE>; defm V_CMP_T_I64 : VOPC_I64 , "v_cmp_t_i64">; defm V_CMPX_F_I64 : VOPCX_I64 , "v_cmpx_f_i64">; defm V_CMPX_LT_I64 : VOPCX_I64 , "v_cmpx_lt_i64", "v_cmpx_gt_i64">; defm V_CMPX_EQ_I64 : VOPCX_I64 , "v_cmpx_eq_i64">; defm V_CMPX_LE_I64 : VOPCX_I64 , "v_cmpx_le_i64", "v_cmpx_ge_i64">; defm V_CMPX_GT_I64 : VOPCX_I64 , "v_cmpx_gt_i64">; defm V_CMPX_NE_I64 : VOPCX_I64 , "v_cmpx_ne_i64">; defm V_CMPX_GE_I64 : VOPCX_I64 , "v_cmpx_ge_i64">; defm V_CMPX_T_I64 : VOPCX_I64 , "v_cmpx_t_i64">; defm V_CMP_F_U32 : VOPC_I32 , "v_cmp_f_u32">; defm V_CMP_LT_U32 : VOPC_I32 , "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">; defm V_CMP_EQ_U32 : VOPC_I32 , "v_cmp_eq_u32", COND_EQ>; defm V_CMP_LE_U32 : VOPC_I32 , "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">; defm V_CMP_GT_U32 : VOPC_I32 , "v_cmp_gt_u32", COND_UGT>; defm V_CMP_NE_U32 : VOPC_I32 , "v_cmp_ne_u32", COND_NE>; defm V_CMP_GE_U32 : VOPC_I32 , "v_cmp_ge_u32", COND_UGE>; defm V_CMP_T_U32 : VOPC_I32 , "v_cmp_t_u32">; defm V_CMPX_F_U32 : VOPCX_I32 , "v_cmpx_f_u32">; defm V_CMPX_LT_U32 : VOPCX_I32 , "v_cmpx_lt_u32", "v_cmpx_gt_u32">; defm V_CMPX_EQ_U32 : VOPCX_I32 , "v_cmpx_eq_u32">; defm V_CMPX_LE_U32 : VOPCX_I32 , "v_cmpx_le_u32", "v_cmpx_le_u32">; defm V_CMPX_GT_U32 : VOPCX_I32 , "v_cmpx_gt_u32">; defm V_CMPX_NE_U32 : VOPCX_I32 , "v_cmpx_ne_u32">; defm V_CMPX_GE_U32 : VOPCX_I32 , "v_cmpx_ge_u32">; defm V_CMPX_T_U32 : VOPCX_I32 , "v_cmpx_t_u32">; defm V_CMP_F_U64 : VOPC_I64 , "v_cmp_f_u64">; defm V_CMP_LT_U64 : VOPC_I64 , "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">; defm V_CMP_EQ_U64 : VOPC_I64 , "v_cmp_eq_u64", COND_EQ>; defm V_CMP_LE_U64 : VOPC_I64 , "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">; defm V_CMP_GT_U64 : VOPC_I64 , "v_cmp_gt_u64", COND_UGT>; defm V_CMP_NE_U64 : VOPC_I64 , "v_cmp_ne_u64", COND_NE>; defm V_CMP_GE_U64 : VOPC_I64 , "v_cmp_ge_u64", COND_UGE>; defm V_CMP_T_U64 : VOPC_I64 , "v_cmp_t_u64">; defm V_CMPX_F_U64 : VOPCX_I64 , "v_cmpx_f_u64">; defm V_CMPX_LT_U64 : VOPCX_I64 , "v_cmpx_lt_u64", "v_cmpx_gt_u64">; defm V_CMPX_EQ_U64 : VOPCX_I64 , "v_cmpx_eq_u64">; defm V_CMPX_LE_U64 : VOPCX_I64 , "v_cmpx_le_u64", "v_cmpx_ge_u64">; defm V_CMPX_GT_U64 : VOPCX_I64 , "v_cmpx_gt_u64">; defm V_CMPX_NE_U64 : VOPCX_I64 , "v_cmpx_ne_u64">; defm V_CMPX_GE_U64 : VOPCX_I64 , "v_cmpx_ge_u64">; defm V_CMPX_T_U64 : VOPCX_I64 , "v_cmpx_t_u64">; } // End isCompare = 1, isCommutable = 1 defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 , "v_cmp_class_f32">; defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 , "v_cmpx_class_f32">; defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 , "v_cmp_class_f64">; defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 , "v_cmpx_class_f64">; //===----------------------------------------------------------------------===// // DS Instructions //===----------------------------------------------------------------------===// defm DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>; defm DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>; defm DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>; defm DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>; defm DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>; defm DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>; defm DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>; defm DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>; defm DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>; defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>; defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>; defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>; defm DS_MSKOR_B32 : DS_1A2D_NORET <0xc, "ds_mskor_b32", VGPR_32>; let mayLoad = 0 in { defm DS_WRITE_B32 : DS_1A1D_NORET <0xd, "ds_write_b32", VGPR_32>; defm DS_WRITE2_B32 : DS_1A1D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>; defm DS_WRITE2ST64_B32 : DS_1A1D_Off8_NORET <0xf, "ds_write2st64_b32", VGPR_32>; } defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>; defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>; defm DS_MIN_F32 : DS_1A2D_NORET <0x12, "ds_min_f32", VGPR_32>; defm DS_MAX_F32 : DS_1A2D_NORET <0x13, "ds_max_f32", VGPR_32>; defm DS_GWS_INIT : DS_1A_GDS <0x19, "ds_gws_init">; defm DS_GWS_SEMA_V : DS_1A_GDS <0x1a, "ds_gws_sema_v">; defm DS_GWS_SEMA_BR : DS_1A_GDS <0x1b, "ds_gws_sema_br">; defm DS_GWS_SEMA_P : DS_1A_GDS <0x1c, "ds_gws_sema_p">; defm DS_GWS_BARRIER : DS_1A_GDS <0x1d, "ds_gws_barrier">; let mayLoad = 0 in { defm DS_WRITE_B8 : DS_1A1D_NORET <0x1e, "ds_write_b8", VGPR_32>; defm DS_WRITE_B16 : DS_1A1D_NORET <0x1f, "ds_write_b16", VGPR_32>; } defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">; defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">; defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">; defm DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">; defm DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">; defm DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">; defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">; defm DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">; defm DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">; defm DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">; defm DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">; defm DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">; defm DS_MSKOR_RTN_B32 : DS_1A2D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">; defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>; defm DS_WRXCHG2_RTN_B32 : DS_1A2D_RET < 0x2e, "ds_wrxchg2_rtn_b32", VReg_64, "", VGPR_32 >; defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET < 0x2f, "ds_wrxchg2st64_rtn_b32", VReg_64, "", VGPR_32 >; defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">; defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">; defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">; defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">; let SubtargetPredicate = isCI in { defm DS_WRAP_RTN_F32 : DS_1A1D_RET <0x34, "ds_wrap_rtn_f32", VGPR_32, "ds_wrap_f32">; } // End isCI defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>; let mayStore = 0 in { defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>; defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>; defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>; defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>; defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>; defm DS_READ_I16 : DS_1A_RET <0x3b, "ds_read_i16", VGPR_32>; defm DS_READ_U16 : DS_1A_RET <0x3c, "ds_read_u16", VGPR_32>; } defm DS_CONSUME : DS_0A_RET <0x3d, "ds_consume">; defm DS_APPEND : DS_0A_RET <0x3e, "ds_append">; defm DS_ORDERED_COUNT : DS_1A_RET_GDS <0x3f, "ds_ordered_count">; defm DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>; defm DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>; defm DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>; defm DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>; defm DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>; defm DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>; defm DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>; defm DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>; defm DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>; defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>; defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>; defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>; defm DS_MSKOR_B64 : DS_1A2D_NORET <0x4c, "ds_mskor_b64", VReg_64>; let mayLoad = 0 in { defm DS_WRITE_B64 : DS_1A1D_NORET <0x4d, "ds_write_b64", VReg_64>; defm DS_WRITE2_B64 : DS_1A1D_Off8_NORET <0x4E, "ds_write2_b64", VReg_64>; defm DS_WRITE2ST64_B64 : DS_1A1D_Off8_NORET <0x4f, "ds_write2st64_b64", VReg_64>; } defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>; defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>; defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>; defm DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>; defm DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">; defm DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">; defm DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">; defm DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">; defm DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">; defm DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">; defm DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">; defm DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">; defm DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">; defm DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">; defm DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">; defm DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">; defm DS_MSKOR_RTN_B64 : DS_1A2D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">; defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">; defm DS_WRXCHG2_RTN_B64 : DS_1A2D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_128, "ds_wrxchg2_b64", VReg_64>; defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET <0x6f, "ds_wrxchg2st64_rtn_b64", VReg_128, "ds_wrxchg2st64_b64", VReg_64>; defm DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">; defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">; defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">; defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">; let mayStore = 0 in { defm DS_READ_B64 : DS_1A_RET <0x76, "ds_read_b64", VReg_64>; defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>; defm DS_READ2ST64_B64 : DS_1A_Off8_RET <0x78, "ds_read2st64_b64", VReg_128>; } defm DS_ADD_SRC2_U32 : DS_1A <0x80, "ds_add_src2_u32">; defm DS_SUB_SRC2_U32 : DS_1A <0x81, "ds_sub_src2_u32">; defm DS_RSUB_SRC2_U32 : DS_1A <0x82, "ds_rsub_src2_u32">; defm DS_INC_SRC2_U32 : DS_1A <0x83, "ds_inc_src2_u32">; defm DS_DEC_SRC2_U32 : DS_1A <0x84, "ds_dec_src2_u32">; defm DS_MIN_SRC2_I32 : DS_1A <0x85, "ds_min_src2_i32">; defm DS_MAX_SRC2_I32 : DS_1A <0x86, "ds_max_src2_i32">; defm DS_MIN_SRC2_U32 : DS_1A <0x87, "ds_min_src2_u32">; defm DS_MAX_SRC2_U32 : DS_1A <0x88, "ds_max_src2_u32">; defm DS_AND_SRC2_B32 : DS_1A <0x89, "ds_and_src_b32">; defm DS_OR_SRC2_B32 : DS_1A <0x8a, "ds_or_src2_b32">; defm DS_XOR_SRC2_B32 : DS_1A <0x8b, "ds_xor_src2_b32">; defm DS_WRITE_SRC2_B32 : DS_1A <0x8c, "ds_write_src2_b32">; defm DS_MIN_SRC2_F32 : DS_1A <0x92, "ds_min_src2_f32">; defm DS_MAX_SRC2_F32 : DS_1A <0x93, "ds_max_src2_f32">; defm DS_ADD_SRC2_U64 : DS_1A <0xc0, "ds_add_src2_u64">; defm DS_SUB_SRC2_U64 : DS_1A <0xc1, "ds_sub_src2_u64">; defm DS_RSUB_SRC2_U64 : DS_1A <0xc2, "ds_rsub_src2_u64">; defm DS_INC_SRC2_U64 : DS_1A <0xc3, "ds_inc_src2_u64">; defm DS_DEC_SRC2_U64 : DS_1A <0xc4, "ds_dec_src2_u64">; defm DS_MIN_SRC2_I64 : DS_1A <0xc5, "ds_min_src2_i64">; defm DS_MAX_SRC2_I64 : DS_1A <0xc6, "ds_max_src2_i64">; defm DS_MIN_SRC2_U64 : DS_1A <0xc7, "ds_min_src2_u64">; defm DS_MAX_SRC2_U64 : DS_1A <0xc8, "ds_max_src2_u64">; defm DS_AND_SRC2_B64 : DS_1A <0xc9, "ds_and_src2_b64">; defm DS_OR_SRC2_B64 : DS_1A <0xca, "ds_or_src2_b64">; defm DS_XOR_SRC2_B64 : DS_1A <0xcb, "ds_xor_src2_b64">; defm DS_WRITE_SRC2_B64 : DS_1A <0xcc, "ds_write_src2_b64">; defm DS_MIN_SRC2_F64 : DS_1A <0xd2, "ds_min_src2_f64">; defm DS_MAX_SRC2_F64 : DS_1A <0xd3, "ds_max_src2_f64">; //let SubtargetPredicate = isCI in { // DS_CONDXCHG32_RTN_B64 // DS_CONDXCHG32_RTN_B128 //} // End isCI //===----------------------------------------------------------------------===// // MUBUF Instructions //===----------------------------------------------------------------------===// defm BUFFER_LOAD_FORMAT_X : MUBUF_Load_Helper < mubuf<0x00>, "buffer_load_format_x", VGPR_32 >; defm BUFFER_LOAD_FORMAT_XY : MUBUF_Load_Helper < mubuf<0x01>, "buffer_load_format_xy", VReg_64 >; defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Load_Helper < mubuf<0x02>, "buffer_load_format_xyz", VReg_96 >; defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper < mubuf<0x03>, "buffer_load_format_xyzw", VReg_128 >; defm BUFFER_STORE_FORMAT_X : MUBUF_Store_Helper < mubuf<0x04>, "buffer_store_format_x", VGPR_32 >; defm BUFFER_STORE_FORMAT_XY : MUBUF_Store_Helper < mubuf<0x05>, "buffer_store_format_xy", VReg_64 >; defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Store_Helper < mubuf<0x06>, "buffer_store_format_xyz", VReg_96 >; defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Store_Helper < mubuf<0x07>, "buffer_store_format_xyzw", VReg_128 >; defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper < mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global >; defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper < mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global >; defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper < mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global >; defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper < mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, sextloadi16_global >; defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper < mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, global_load >; defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper < mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, global_load >; defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper < mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, global_load >; defm BUFFER_STORE_BYTE : MUBUF_Store_Helper < mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global >; defm BUFFER_STORE_SHORT : MUBUF_Store_Helper < mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global >; defm BUFFER_STORE_DWORD : MUBUF_Store_Helper < mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store >; defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store >; defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store >; defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic < mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global >; //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ , "buffer_atomic_cmpswap", []>; defm BUFFER_ATOMIC_ADD : MUBUF_Atomic < mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global >; defm BUFFER_ATOMIC_SUB : MUBUF_Atomic < mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global >; //def BUFFER_ATOMIC_RSUB : MUBUF_ , "buffer_atomic_rsub", []>; // isn't on CI & VI defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic < mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global >; defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic < mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global >; defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic < mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global >; defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic < mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global >; defm BUFFER_ATOMIC_AND : MUBUF_Atomic < mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global >; defm BUFFER_ATOMIC_OR : MUBUF_Atomic < mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global >; defm BUFFER_ATOMIC_XOR : MUBUF_Atomic < mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global >; //def BUFFER_ATOMIC_INC : MUBUF_ , "buffer_atomic_inc", []>; //def BUFFER_ATOMIC_DEC : MUBUF_ , "buffer_atomic_dec", []>; //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ , "buffer_atomic_fcmpswap", []>; // isn't on VI //def BUFFER_ATOMIC_FMIN : MUBUF_ , "buffer_atomic_fmin", []>; // isn't on VI //def BUFFER_ATOMIC_FMAX : MUBUF_ , "buffer_atomic_fmax", []>; // isn't on VI //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 , "buffer_atomic_swap_x2", []>; //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 , "buffer_atomic_cmpswap_x2", []>; //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 , "buffer_atomic_add_x2", []>; //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 , "buffer_atomic_sub_x2", []>; //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 , "buffer_atomic_rsub_x2", []>; // isn't on CI & VI //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 , "buffer_atomic_smin_x2", []>; //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 , "buffer_atomic_umin_x2", []>; //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 , "buffer_atomic_smax_x2", []>; //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 , "buffer_atomic_umax_x2", []>; //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 , "buffer_atomic_and_x2", []>; //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 , "buffer_atomic_or_x2", []>; //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 , "buffer_atomic_xor_x2", []>; //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 , "buffer_atomic_inc_x2", []>; //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 , "buffer_atomic_dec_x2", []>; //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 , "buffer_atomic_fcmpswap_x2", []>; // isn't on VI //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 , "buffer_atomic_fmin_x2", []>; // isn't on VI //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 , "buffer_atomic_fmax_x2", []>; // isn't on VI //def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 , "buffer_wbinvl1_sc", []>; // isn't on CI & VI //def BUFFER_WBINVL1_VOL : MUBUF_WBINVL1 , "buffer_wbinvl1_vol", []>; // isn't on SI //def BUFFER_WBINVL1 : MUBUF_WBINVL1 , "buffer_wbinvl1", []>; //===----------------------------------------------------------------------===// // MTBUF Instructions //===----------------------------------------------------------------------===// //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>; //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>; //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>; defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>; defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>; defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>; defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>; defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>; //===----------------------------------------------------------------------===// // MIMG Instructions //===----------------------------------------------------------------------===// defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">; defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">; //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>; //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>; //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>; //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>; //def IMAGE_STORE : MIMG_NoPattern_ <"image_store", 0x00000008>; //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"image_store_mip", 0x00000009>; //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>; //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>; defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">; //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"image_atomic_swap", 0x0000000f>; //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"image_atomic_cmpswap", 0x00000010>; //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"image_atomic_add", 0x00000011>; //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"image_atomic_sub", 0x00000012>; //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"image_atomic_smin", 0x00000014>; //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"image_atomic_umin", 0x00000015>; //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"image_atomic_smax", 0x00000016>; //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"image_atomic_umax", 0x00000017>; //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"image_atomic_and", 0x00000018>; //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"image_atomic_or", 0x00000019>; //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"image_atomic_xor", 0x0000001a>; //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"image_atomic_inc", 0x0000001b>; //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"image_atomic_dec", 0x0000001c>; //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">; defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">; defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">; defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">; defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">; defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">; defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">; defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">; defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">; defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">; defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">; defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">; defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">; defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">; defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">; defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">; defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">; defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">; defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">; defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">; defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">; defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">; defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">; defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">; defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">; defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">; defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">; defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">; defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">; defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">; defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">; defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">; defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">; defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">; defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">; defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">; defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">; defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">; defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">; defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">; defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">; defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">; defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">; defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">; defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">; defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">; defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">; defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">; defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">; defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">; defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">; defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">; defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">; defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">; defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">; defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">; defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">; defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">; defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">; defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">; defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">; defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">; defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">; defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">; defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">; //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; //def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; //===----------------------------------------------------------------------===// // Flat Instructions //===----------------------------------------------------------------------===// let Predicates = [HasFlatAddressSpace] in { def FLAT_LOAD_UBYTE : FLAT_Load_Helper <0x00000008, "flat_load_ubyte", VGPR_32>; def FLAT_LOAD_SBYTE : FLAT_Load_Helper <0x00000009, "flat_load_sbyte", VGPR_32>; def FLAT_LOAD_USHORT : FLAT_Load_Helper <0x0000000a, "flat_load_ushort", VGPR_32>; def FLAT_LOAD_SSHORT : FLAT_Load_Helper <0x0000000b, "flat_load_sshort", VGPR_32>; def FLAT_LOAD_DWORD : FLAT_Load_Helper <0x0000000c, "flat_load_dword", VGPR_32>; def FLAT_LOAD_DWORDX2 : FLAT_Load_Helper <0x0000000d, "flat_load_dwordx2", VReg_64>; def FLAT_LOAD_DWORDX4 : FLAT_Load_Helper <0x0000000e, "flat_load_dwordx4", VReg_128>; def FLAT_LOAD_DWORDX3 : FLAT_Load_Helper <0x00000010, "flat_load_dwordx3", VReg_96>; def FLAT_STORE_BYTE : FLAT_Store_Helper < 0x00000018, "flat_store_byte", VGPR_32 >; def FLAT_STORE_SHORT : FLAT_Store_Helper < 0x0000001a, "flat_store_short", VGPR_32 >; def FLAT_STORE_DWORD : FLAT_Store_Helper < 0x0000001c, "flat_store_dword", VGPR_32 >; def FLAT_STORE_DWORDX2 : FLAT_Store_Helper < 0x0000001d, "flat_store_dwordx2", VReg_64 >; def FLAT_STORE_DWORDX4 : FLAT_Store_Helper < 0x0000001e, "flat_store_dwordx4", VReg_128 >; def FLAT_STORE_DWORDX3 : FLAT_Store_Helper < 0x0000001e, "flat_store_dwordx3", VReg_96 >; //def FLAT_ATOMIC_SWAP : FLAT_ <0x00000030, "flat_atomic_swap", []>; //def FLAT_ATOMIC_CMPSWAP : FLAT_ <0x00000031, "flat_atomic_cmpswap", []>; //def FLAT_ATOMIC_ADD : FLAT_ <0x00000032, "flat_atomic_add", []>; //def FLAT_ATOMIC_SUB : FLAT_ <0x00000033, "flat_atomic_sub", []>; //def FLAT_ATOMIC_RSUB : FLAT_ <0x00000034, "flat_atomic_rsub", []>; //def FLAT_ATOMIC_SMIN : FLAT_ <0x00000035, "flat_atomic_smin", []>; //def FLAT_ATOMIC_UMIN : FLAT_ <0x00000036, "flat_atomic_umin", []>; //def FLAT_ATOMIC_SMAX : FLAT_ <0x00000037, "flat_atomic_smax", []>; //def FLAT_ATOMIC_UMAX : FLAT_ <0x00000038, "flat_atomic_umax", []>; //def FLAT_ATOMIC_AND : FLAT_ <0x00000039, "flat_atomic_and", []>; //def FLAT_ATOMIC_OR : FLAT_ <0x0000003a, "flat_atomic_or", []>; //def FLAT_ATOMIC_XOR : FLAT_ <0x0000003b, "flat_atomic_xor", []>; //def FLAT_ATOMIC_INC : FLAT_ <0x0000003c, "flat_atomic_inc", []>; //def FLAT_ATOMIC_DEC : FLAT_ <0x0000003d, "flat_atomic_dec", []>; //def FLAT_ATOMIC_FCMPSWAP : FLAT_ <0x0000003e, "flat_atomic_fcmpswap", []>; //def FLAT_ATOMIC_FMIN : FLAT_ <0x0000003f, "flat_atomic_fmin", []>; //def FLAT_ATOMIC_FMAX : FLAT_ <0x00000040, "flat_atomic_fmax", []>; //def FLAT_ATOMIC_SWAP_X2 : FLAT_X2 <0x00000050, "flat_atomic_swap_x2", []>; //def FLAT_ATOMIC_CMPSWAP_X2 : FLAT_X2 <0x00000051, "flat_atomic_cmpswap_x2", []>; //def FLAT_ATOMIC_ADD_X2 : FLAT_X2 <0x00000052, "flat_atomic_add_x2", []>; //def FLAT_ATOMIC_SUB_X2 : FLAT_X2 <0x00000053, "flat_atomic_sub_x2", []>; //def FLAT_ATOMIC_RSUB_X2 : FLAT_X2 <0x00000054, "flat_atomic_rsub_x2", []>; //def FLAT_ATOMIC_SMIN_X2 : FLAT_X2 <0x00000055, "flat_atomic_smin_x2", []>; //def FLAT_ATOMIC_UMIN_X2 : FLAT_X2 <0x00000056, "flat_atomic_umin_x2", []>; //def FLAT_ATOMIC_SMAX_X2 : FLAT_X2 <0x00000057, "flat_atomic_smax_x2", []>; //def FLAT_ATOMIC_UMAX_X2 : FLAT_X2 <0x00000058, "flat_atomic_umax_x2", []>; //def FLAT_ATOMIC_AND_X2 : FLAT_X2 <0x00000059, "flat_atomic_and_x2", []>; //def FLAT_ATOMIC_OR_X2 : FLAT_X2 <0x0000005a, "flat_atomic_or_x2", []>; //def FLAT_ATOMIC_XOR_X2 : FLAT_X2 <0x0000005b, "flat_atomic_xor_x2", []>; //def FLAT_ATOMIC_INC_X2 : FLAT_X2 <0x0000005c, "flat_atomic_inc_x2", []>; //def FLAT_ATOMIC_DEC_X2 : FLAT_X2 <0x0000005d, "flat_atomic_dec_x2", []>; //def FLAT_ATOMIC_FCMPSWAP_X2 : FLAT_X2 <0x0000005e, "flat_atomic_fcmpswap_x2", []>; //def FLAT_ATOMIC_FMIN_X2 : FLAT_X2 <0x0000005f, "flat_atomic_fmin_x2", []>; //def FLAT_ATOMIC_FMAX_X2 : FLAT_X2 <0x00000060, "flat_atomic_fmax_x2", []>; } // End HasFlatAddressSpace predicate //===----------------------------------------------------------------------===// // VOP1 Instructions //===----------------------------------------------------------------------===// let vdst = 0, src0 = 0 in { defm V_NOP : VOP1_m , (outs), (ins), "v_nop", [], "v_nop">; } let isMoveImm = 1 in { defm V_MOV_B32 : VOP1Inst , "v_mov_b32", VOP_I32_I32>; } // End isMoveImm = 1 let Uses = [EXEC] in { // FIXME: Specify SchedRW for READFIRSTLANE_B32 def V_READFIRSTLANE_B32 : VOP1 < 0x00000002, (outs SReg_32:$vdst), (ins VGPR_32:$src0), "v_readfirstlane_b32 $vdst, $src0", [] >; } let SchedRW = [WriteQuarterRate32] in { defm V_CVT_I32_F64 : VOP1Inst , "v_cvt_i32_f64", VOP_I32_F64, fp_to_sint >; defm V_CVT_F64_I32 : VOP1Inst , "v_cvt_f64_i32", VOP_F64_I32, sint_to_fp >; defm V_CVT_F32_I32 : VOP1Inst , "v_cvt_f32_i32", VOP_F32_I32, sint_to_fp >; defm V_CVT_F32_U32 : VOP1Inst , "v_cvt_f32_u32", VOP_F32_I32, uint_to_fp >; defm V_CVT_U32_F32 : VOP1Inst , "v_cvt_u32_f32", VOP_I32_F32, fp_to_uint >; defm V_CVT_I32_F32 : VOP1Inst , "v_cvt_i32_f32", VOP_I32_F32, fp_to_sint >; defm V_MOV_FED_B32 : VOP1Inst , "v_mov_fed_b32", VOP_I32_I32>; defm V_CVT_F16_F32 : VOP1Inst , "v_cvt_f16_f32", VOP_I32_F32, fp_to_f16 >; defm V_CVT_F32_F16 : VOP1Inst , "v_cvt_f32_f16", VOP_F32_I32, f16_to_fp >; defm V_CVT_RPI_I32_F32 : VOP1Inst , "v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>; defm V_CVT_FLR_I32_F32 : VOP1Inst , "v_cvt_flr_i32_f32", VOP_I32_F32, cvt_flr_i32_f32>; defm V_CVT_OFF_F32_I4 : VOP1Inst , "v_cvt_off_f32_i4", VOP_F32_I32>; defm V_CVT_F32_F64 : VOP1Inst , "v_cvt_f32_f64", VOP_F32_F64, fround >; defm V_CVT_F64_F32 : VOP1Inst , "v_cvt_f64_f32", VOP_F64_F32, fextend >; defm V_CVT_F32_UBYTE0 : VOP1Inst , "v_cvt_f32_ubyte0", VOP_F32_I32, AMDGPUcvt_f32_ubyte0 >; defm V_CVT_F32_UBYTE1 : VOP1Inst , "v_cvt_f32_ubyte1", VOP_F32_I32, AMDGPUcvt_f32_ubyte1 >; defm V_CVT_F32_UBYTE2 : VOP1Inst , "v_cvt_f32_ubyte2", VOP_F32_I32, AMDGPUcvt_f32_ubyte2 >; defm V_CVT_F32_UBYTE3 : VOP1Inst , "v_cvt_f32_ubyte3", VOP_F32_I32, AMDGPUcvt_f32_ubyte3 >; defm V_CVT_U32_F64 : VOP1Inst , "v_cvt_u32_f64", VOP_I32_F64, fp_to_uint >; defm V_CVT_F64_U32 : VOP1Inst , "v_cvt_f64_u32", VOP_F64_I32, uint_to_fp >; } // let SchedRW = [WriteQuarterRate32] defm V_FRACT_F32 : VOP1Inst , "v_fract_f32", VOP_F32_F32, AMDGPUfract >; defm V_TRUNC_F32 : VOP1Inst , "v_trunc_f32", VOP_F32_F32, ftrunc >; defm V_CEIL_F32 : VOP1Inst , "v_ceil_f32", VOP_F32_F32, fceil >; defm V_RNDNE_F32 : VOP1Inst , "v_rndne_f32", VOP_F32_F32, frint >; defm V_FLOOR_F32 : VOP1Inst , "v_floor_f32", VOP_F32_F32, ffloor >; defm V_EXP_F32 : VOP1Inst , "v_exp_f32", VOP_F32_F32, fexp2 >; let SchedRW = [WriteQuarterRate32] in { defm V_LOG_F32 : VOP1Inst , "v_log_f32", VOP_F32_F32, flog2 >; defm V_RCP_F32 : VOP1Inst , "v_rcp_f32", VOP_F32_F32, AMDGPUrcp >; defm V_RCP_IFLAG_F32 : VOP1Inst , "v_rcp_iflag_f32", VOP_F32_F32 >; defm V_RSQ_F32 : VOP1Inst , "v_rsq_f32", VOP_F32_F32, AMDGPUrsq >; } //let SchedRW = [WriteQuarterRate32] let SchedRW = [WriteDouble] in { defm V_RCP_F64 : VOP1Inst , "v_rcp_f64", VOP_F64_F64, AMDGPUrcp >; defm V_RSQ_F64 : VOP1Inst , "v_rsq_f64", VOP_F64_F64, AMDGPUrsq >; } // let SchedRW = [WriteDouble]; defm V_SQRT_F32 : VOP1Inst , "v_sqrt_f32", VOP_F32_F32, fsqrt >; let SchedRW = [WriteDouble] in { defm V_SQRT_F64 : VOP1Inst , "v_sqrt_f64", VOP_F64_F64, fsqrt >; } // let SchedRW = [WriteDouble] defm V_SIN_F32 : VOP1Inst , "v_sin_f32", VOP_F32_F32, AMDGPUsin >; defm V_COS_F32 : VOP1Inst , "v_cos_f32", VOP_F32_F32, AMDGPUcos >; defm V_NOT_B32 : VOP1Inst , "v_not_b32", VOP_I32_I32>; defm V_BFREV_B32 : VOP1Inst , "v_bfrev_b32", VOP_I32_I32>; defm V_FFBH_U32 : VOP1Inst , "v_ffbh_u32", VOP_I32_I32>; defm V_FFBL_B32 : VOP1Inst , "v_ffbl_b32", VOP_I32_I32>; defm V_FFBH_I32 : VOP1Inst , "v_ffbh_i32", VOP_I32_I32>; defm V_FREXP_EXP_I32_F64 : VOP1Inst , "v_frexp_exp_i32_f64", VOP_I32_F64 >; defm V_FREXP_MANT_F64 : VOP1Inst , "v_frexp_mant_f64", VOP_F64_F64 >; defm V_FRACT_F64 : VOP1Inst , "v_fract_f64", VOP_F64_F64>; defm V_FREXP_EXP_I32_F32 : VOP1Inst , "v_frexp_exp_i32_f32", VOP_I32_F32 >; defm V_FREXP_MANT_F32 : VOP1Inst , "v_frexp_mant_f32", VOP_F32_F32 >; let vdst = 0, src0 = 0 in { defm V_CLREXCP : VOP1_m , (outs), (ins), "v_clrexcp", [], "v_clrexcp" >; } defm V_MOVRELD_B32 : VOP1Inst , "v_movreld_b32", VOP_I32_I32>; defm V_MOVRELS_B32 : VOP1Inst , "v_movrels_b32", VOP_I32_I32>; defm V_MOVRELSD_B32 : VOP1Inst , "v_movrelsd_b32", VOP_I32_I32>; // These instruction only exist on SI and CI let SubtargetPredicate = isSICI in { let SchedRW = [WriteQuarterRate32] in { defm V_LOG_CLAMP_F32 : VOP1InstSI , "v_log_clamp_f32", VOP_F32_F32>; defm V_RCP_CLAMP_F32 : VOP1InstSI , "v_rcp_clamp_f32", VOP_F32_F32>; defm V_RCP_LEGACY_F32 : VOP1InstSI , "v_rcp_legacy_f32", VOP_F32_F32>; defm V_RSQ_CLAMP_F32 : VOP1InstSI , "v_rsq_clamp_f32", VOP_F32_F32, AMDGPUrsq_clamped >; defm V_RSQ_LEGACY_F32 : VOP1InstSI , "v_rsq_legacy_f32", VOP_F32_F32, AMDGPUrsq_legacy >; } // End let SchedRW = [WriteQuarterRate32] let SchedRW = [WriteDouble] in { defm V_RCP_CLAMP_F64 : VOP1InstSI , "v_rcp_clamp_f64", VOP_F64_F64>; defm V_RSQ_CLAMP_F64 : VOP1InstSI , "v_rsq_clamp_f64", VOP_F64_F64, AMDGPUrsq_clamped >; } // End SchedRW = [WriteDouble] } // End SubtargetPredicate = isSICI //===----------------------------------------------------------------------===// // VINTRP Instructions //===----------------------------------------------------------------------===// // FIXME: Specify SchedRW for VINTRP insturctions. defm V_INTERP_P1_F32 : VINTRP_m < 0x00000000, "v_interp_p1_f32", (outs VGPR_32:$dst), (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [$m0]", "$m0">; defm V_INTERP_P2_F32 : VINTRP_m < 0x00000001, "v_interp_p2_f32", (outs VGPR_32:$dst), (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", "$src0,$m0", "$src0 = $dst">; defm V_INTERP_MOV_F32 : VINTRP_m < 0x00000002, "v_interp_mov_f32", (outs VGPR_32:$dst), (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [$m0]", "$m0">; //===----------------------------------------------------------------------===// // VOP2 Instructions //===----------------------------------------------------------------------===// multiclass V_CNDMASK { defm _e32 : VOP2_m < op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins32, VOP_CNDMASK.Asm32, [], name, name>; defm _e64 : VOP3_m < op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64, name#!cast(VOP_CNDMASK.Asm64), [], name, 3>; } defm V_CNDMASK_B32 : V_CNDMASK, "v_cndmask_b32">; let isCommutable = 1 in { defm V_ADD_F32 : VOP2Inst