//===-- SparcV9Instr.def - SparcV9 Instruction Information -------*- C++ -*-==//
// 
//                     The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
// 
//===----------------------------------------------------------------------===//
//
// This file describes all of the instructions that the sparc backend uses.  It
// relys on an external 'I' macro being defined that takes the arguments
// specified below, and is used to make all of the information relevant to an
// instruction be in one place.
//
//===----------------------------------------------------------------------===//

// NOTE: No include guards desired

#ifndef I
#errror "Must define I macro before including SparcInstr.def!"
#endif

// Constants for defining the maximum constant size field.
// One #define per bit size
//
#define B5  ((1 << 5) - 1)
#define B6  ((1 << 6) - 1)
#define B12 ((1 << 12) - 1)
#define B15 ((1 << 15) - 1)
#define B18 ((1 << 18) - 1)
#define B21 ((1 << 21) - 1)
#define B22 ((1 << 22) - 1)
#define B29 ((1 << 29) - 1)

// Arguments passed into the I macro
// enum name,
//     opCodeString,
//           numOperands,
//                resultPosition (0-based; -1 if no result),
//                     maxImmedConst,
//                         immedIsSignExtended,
//                                numDelaySlots (in cycles)
//					latency (in cycles)
//					    instr sched class (defined above)
//						instr class flags (defined in TargetInstrInfo.h)



I(NOP, "nop",		0,  -1,  0, false, 0,  1,  SPARC_NONE,  M_NOP_FLAG)

// Synthetic SPARC assembly opcodes for setting a register to a constant.
// Max immediate constant should be ignored for both these instructions.
// Use a latency > 1 since this may generate as many as 3 instructions.
I(SETSW, "setsw",	2,   1,  0, true , 0,  2,  SPARC_IEUN,  M_PSEUDO_FLAG )
I(SETUW, "setuw",	2,   1,  0, false, 0,  2,  SPARC_IEUN,  M_PSEUDO_FLAG )
I(SETX,  "setx",	3,   2,  0, true,  0,  2,  SPARC_IEUN,  M_PSEUDO_FLAG )

// Set high-order bits of register and clear low-order bits
I(SETHI, "sethi",	2,  1, B22, false, 0,  1,  SPARC_IEUN,  0)

// Add or add with carry.
I(ADDr  , "add",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ADDi  , "add",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ADDccr, "addcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_CC_FLAG )
I(ADDcci, "addcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_CC_FLAG )
I(ADDCr , "addc",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ADDCi , "addc",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ADDCccr, "addccc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_CC_FLAG )
I(ADDCcci, "addccc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_CC_FLAG )

// Subtract or subtract with carry.
I(SUBr   , "sub",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(SUBi   , "sub",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(SUBccr , "subcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_CC_FLAG )
I(SUBcci , "subcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_CC_FLAG )
I(SUBCr  , "subc",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(SUBCi  , "subc",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(SUBCccr, "subccc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_CC_FLAG )
I(SUBCcci, "subccc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  M_CC_FLAG )

// Integer multiply, signed divide, unsigned divide.
// Note that the deprecated 32-bit multiply and multiply-step are not used.
I(MULXr , "mulx",	3,  2, B12, true , 0, 3, SPARC_IEUN,  0)
I(MULXi , "mulx",	3,  2, B12, true , 0, 3, SPARC_IEUN,  0)
I(SDIVXr, "sdivx",	3,  2, B12, true , 0, 6, SPARC_IEUN,  0)
I(SDIVXi, "sdivx",	3,  2, B12, true , 0, 6, SPARC_IEUN,  0)
I(UDIVXr, "udivx",	3,  2, B12, true , 0, 6, SPARC_IEUN,  0)
I(UDIVXi, "udivx",	3,  2, B12, true , 0, 6, SPARC_IEUN,  0)

  // Floating point add, subtract, compare.
  // Note that destination of FCMP* instructions is operand 0, not operand 2.
I(FADDS, "fadds",	3,  2,   0, false, 0, 3,  SPARC_FPA,  0)
I(FADDD, "faddd",	3,  2,   0, false, 0, 3,  SPARC_FPA,  0)
I(FADDQ, "faddq",	3,  2,   0, false, 0, 3,  SPARC_FPA,  0)
I(FSUBS, "fsubs",	3,  2,   0, false, 0, 3,  SPARC_FPA,  0)
I(FSUBD, "fsubd",	3,  2,   0, false, 0, 3,  SPARC_FPA,  0)
I(FSUBQ, "fsubq",	3,  2,   0, false, 0, 3,  SPARC_FPA,  0)
I(FCMPS, "fcmps",	3,  0,   0, false, 0, 3,  SPARC_FPA,  M_CC_FLAG )
I(FCMPD, "fcmpd",	3,  0,   0, false, 0, 3,  SPARC_FPA,  M_CC_FLAG )
I(FCMPQ, "fcmpq",	3,  0,   0, false, 0, 3,  SPARC_FPA,  M_CC_FLAG )
// NOTE: FCMPE{S,D,Q}: FP Compare With Exception are currently unused!

// Floating point multiply or divide.
I(FMULS , "fmuls",	3,  2,   0, false, 0, 3,  SPARC_FPM,  0)
I(FMULD , "fmuld",	3,  2,   0, false, 0, 3,  SPARC_FPM,  0)
I(FMULQ , "fmulq",	3,  2,   0, false, 0, 0,  SPARC_FPM,  0)
I(FSMULD, "fsmuld",	3,  2,   0, false, 0, 3,  SPARC_FPM,  0)
I(FDMULQ, "fdmulq",	3,  2,   0, false, 0, 0,  SPARC_FPM,  0)
I(FDIVS , "fdivs",	3,  2,   0, false, 0, 12, SPARC_FPM,  0)
I(FDIVD , "fdivd",	3,  2,   0, false, 0, 22, SPARC_FPM,  0)
I(FDIVQ , "fdivq",	3,  2,   0, false, 0, 0,  SPARC_FPM,  0)
I(FSQRTS, "fsqrts",	3,  2,   0, false, 0, 12, SPARC_FPM,  0)
I(FSQRTD, "fsqrtd",	3,  2,   0, false, 0, 22, SPARC_FPM,  0)
I(FSQRTQ, "fsqrtq",	3,  2,   0, false, 0, 0,  SPARC_FPM,  0)

// Logical operations
I(ANDr   , "and",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ANDi   , "and",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ANDccr , "andcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)
I(ANDcci , "andcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)
I(ANDNr  , "andn",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ANDNi  , "andn",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ANDNccr, "andncc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)
I(ANDNcci, "andncc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)

I(ORr   , "or", 	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ORi   , "or", 	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ORccr , "orcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)
I(ORcci , "orcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)
I(ORNr  , "orn",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ORNi  , "orn",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(ORNccr, "orncc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)
I(ORNcci, "orncc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)

I(XORr   , "xor",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(XORi   , "xor",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(XORccr , "xorcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)
I(XORcci , "xorcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)
I(XNORr  , "xnor",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(XNORi  , "xnor",	3,  2, B12, true , 0, 1, SPARC_IEUN,  0)
I(XNORccr, "xnorcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)
I(XNORcci, "xnorcc",	4,  2, B12, true , 0, 1, SPARC_IEU1,  0)

// Shift operations
I(SLLr5 , "sll",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  0)
I(SLLi5 , "sll",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  0)
I(SRLr5 , "srl",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  0)
I(SRLi5 , "srl",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  0)
I(SRAr5 , "sra",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  0)
I(SRAi5 , "sra",  	3,  2,  B5, true , 0, 1, SPARC_IEU0,  0)
I(SLLXr6, "sllx", 	3,  2,  B6, true , 0, 1, SPARC_IEU0,  0)
I(SLLXi6, "sllx", 	3,  2,  B6, true , 0, 1, SPARC_IEU0,  0)
I(SRLXr6, "srlx", 	3,  2,  B6, true , 0, 1, SPARC_IEU0,  0)
I(SRLXi6, "srlx", 	3,  2,  B6, true , 0, 1, SPARC_IEU0,  0)
I(SRAXr6, "srax", 	3,  2,  B6, true , 0, 1, SPARC_IEU0,  0)
I(SRAXi6, "srax", 	3,  2,  B6, true , 0, 1, SPARC_IEU0,  0)

// Floating point move, negate, and abs instructions
I(FMOVS, "fmovs",	2,  1,   0, false, 0, 1,  SPARC_FPA,  0)
I(FMOVD, "fmovd",	2,  1,   0, false, 0, 1,  SPARC_FPA,  0)
//I(FMOVQ, "fmovq",	2,  1,   0, false, 0, ?,  SPARC_FPA,  0)
I(FNEGS, "fnegs",	2,  1,   0, false, 0, 1,  SPARC_FPA,  0)
I(FNEGD, "fnegd",	2,  1,   0, false, 0, 1,  SPARC_FPA,  0)
//I(FNEGQ, "fnegq",	2,  1,   0, false, 0, ?,  SPARC_FPA,  0)
I(FABSS, "fabss",	2,  1,   0, false, 0, 1,  SPARC_FPA,  0)
I(FABSD, "fabsd",	2,  1,   0, false, 0, 1,  SPARC_FPA,  0)
//I(FABSQ, "fabsq",	2,  1,   0, false, 0, ?,  SPARC_FPA,  0)

// Convert from floating point to floating point formats
I(FSTOD, "fstod",	2,  1,   0, false, 0, 3,  SPARC_FPA,  0)
I(FSTOQ, "fstoq",	2,  1,   0, false, 0, 0,  SPARC_FPA,  0)
I(FDTOS, "fdtos",	2,  1,   0, false, 0, 3,  SPARC_FPA,  0)
I(FDTOQ, "fdtoq",	2,  1,   0, false, 0, 0,  SPARC_FPA,  0)
I(FQTOS, "fqtos",	2,  1,   0, false, 0, 0,  SPARC_FPA,  0)
I(FQTOD, "fqtod",	2,  1,   0, false, 0, 0,  SPARC_FPA,  0)

// Convert from floating point to integer formats.
// Note that this accesses both integer and floating point registers.
I(FSTOX, "fstox",	2,  1,   0, false, 0, 3,  SPARC_FPA, 0)
I(FDTOX, "fdtox",	2,  1,   0, false, 0, 0,  SPARC_FPA, 0)
I(FQTOX, "fqtox",	2,  1,   0, false, 0, 2,  SPARC_FPA, 0)
I(FSTOI, "fstoi",	2,  1,   0, false, 0, 3,  SPARC_FPA, 0)
I(FDTOI, "fdtoi",	2,  1,   0, false, 0, 3,  SPARC_FPA, 0)
I(FQTOI, "fqtoi",	2,  1,   0, false, 0, 0,  SPARC_FPA, 0)

// Convert from integer to floating point formats
// Note that this accesses both integer and floating point registers.
I(FXTOS, "fxtos",	2,  1,   0, false, 0, 3,  SPARC_FPA, 0)
I(FXTOD, "fxtod",	2,  1,   0, false, 0, 3,  SPARC_FPA, 0)
I(FXTOQ, "fxtoq",	2,  1,   0, false, 0, 0,  SPARC_FPA, 0)
I(FITOS, "fitos",	2,  1,   0, false, 0, 3,  SPARC_FPA, 0)
I(FITOD, "fitod",	2,  1,   0, false, 0, 3,  SPARC_FPA, 0)
I(FITOQ, "fitoq",	2,  1,   0, false, 0, 0,  SPARC_FPA, 0)

// Branch on integer comparison with zero.
// Latency excludes the delay slot since it can be issued in same cycle.
I(BRZ  , "brz", 	2, -1, B15, true , 1, 1,  SPARC_CTI,   M_BRANCH_FLAG)
I(BRLEZ, "brlez",	2, -1, B15, true , 1, 1,  SPARC_CTI,   M_BRANCH_FLAG)
I(BRLZ , "brlz",	2, -1, B15, true , 1, 1,  SPARC_CTI,   M_BRANCH_FLAG)
I(BRNZ , "brnz",	2, -1, B15, true , 1, 1,  SPARC_CTI,   M_BRANCH_FLAG)
I(BRGZ , "brgz",	2, -1, B15, true , 1, 1,  SPARC_CTI,   M_BRANCH_FLAG)
I(BRGEZ, "brgez",	2, -1, B15, true , 1, 1,  SPARC_CTI,   M_BRANCH_FLAG)

// Branch on integer condition code.
// The first argument specifies the ICC register: %icc or %xcc
// Latency includes the delay slot.
I(BA  , "ba",		1, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BN  , "bn",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BNE , "bne",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BE  , "be",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BG  , "bg",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BLE , "ble",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BGE , "bge",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BL  , "bl",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BGU , "bgu",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BLEU, "bleu",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BCC , "bcc",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BCS , "bcs",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BPOS, "bpos",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BNEG, "bneg",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BVC , "bvc",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(BVS , "bvs",		2, -1, B21, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)

// Branch on floating point condition code.
// The first argument is the FCCn register (0 <= n <= 3).
// Latency includes the delay slot.
I(FBA  , "fba",		2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBN  , "fbn",		2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBU  , "fbu",		2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBG  , "fbg",		2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBUG , "fbug",	2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBL  , "fbl",		2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBUL , "fbul",	2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBLG , "fblg",	2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBNE , "fbne",	2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBE  , "fbe",		2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBUE , "fbue",	2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBGE , "fbge",	2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBUGE, "fbuge",	2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBLE , "fble",	2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBULE, "fbule",	2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)
I(FBO  , "fbo",		2, -1, B18, true , 1, 2,  SPARC_CTI,  M_CC_FLAG | M_BRANCH_FLAG)

// Conditional move on integer comparison with zero.
I(MOVRZr  , "movrz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRZi  , "movrz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRLEZr, "movrlez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRLEZi, "movrlez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRLZr , "movrlz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRLZi , "movrlz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRNZr , "movrnz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRNZi , "movrnz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRGZr , "movrgz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRGZi , "movrgz",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRGEZr, "movrgez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)
I(MOVRGEZi, "movrgez",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  0)

// Conditional move on integer condition code.
// The first argument specifies the ICC register: %icc or %xcc
I(MOVAr  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVAi  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVNr  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVNi  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVNEr , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVNEi , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVEr  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVEi  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVGr  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVGi  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVLEr , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVLEi , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVGEr , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVGEi , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVLr  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVLi  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVGUr , "movgu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVGUi , "movgu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVLEUr, "movleu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVLEUi, "movleu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVCCr , "movcc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVCCi , "movcc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVCSr , "movcs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVCSi , "movcs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVPOSr, "movpos",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVPOSi, "movpos",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVNEGr, "movneg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVNEGi, "movneg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVVCr , "movvc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVVCi , "movvc",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVVSr , "movvs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVVSi , "movvs",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )

// Conditional move (of integer register) on floating point condition code.
// The first argument is the FCCn register (0 <= n <= 3).
// Note that the enum name above is not the same as the assembly mnemonic
// because some of the assembly mnemonics are the same as the move on
// integer CC (e.g., MOVG), and we cannot have the same enum entry twice.
I(MOVFAr  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFAi  , "mova",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFNr  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFNi  , "movn",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFUr  , "movu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFUi  , "movu",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFGr  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFGi  , "movg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFUGr , "movug",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFUGi , "movug",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFLr  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFLi  , "movl",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFULr , "movul",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFULi , "movul",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFLGr , "movlg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFLGi , "movlg",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFNEr , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFNEi , "movne",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFEr  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFEi  , "move",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFUEr , "movue",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFUEi , "movue",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFGEr , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFGEi , "movge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFUGEr, "movuge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFUGEi, "movuge",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFLEr , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFLEi , "movle",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFULEr, "movule",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFULEi, "movule",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFOr  , "movo",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(MOVFOi  , "movo",	3,  2, B12, true , 0, 2,  SPARC_SINGLE,  M_CC_FLAG )

// Conditional move of floating point register on each of the above:
// i.   on integer comparison with zero.
// ii.  on integer condition code
// iii. on floating point condition code
// Note that the same set is repeated for S,D,Q register classes.
I(FMOVRSZ  ,"fmovrsz",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRSLEZ,"fmovrslez",3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRSLZ ,"fmovrslz",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRSNZ ,"fmovrsnz",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRSGZ ,"fmovrsgz",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRSGEZ,"fmovrsgez",3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)

I(FMOVSA  , "fmovsa",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSN  , "fmovsn",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSNE , "fmovsne",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSE  , "fmovse",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSG  , "fmovsg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSLE , "fmovsle",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSGE , "fmovsge",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSL  , "fmovsl",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSGU , "fmovsgu",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSLEU, "fmovsleu",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSCC , "fmovscc",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSCS , "fmovscs",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSPOS, "fmovspos",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSNEG, "fmovsneg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSVC , "fmovsvc",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSVS , "fmovsvs",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )

I(FMOVSFA  , "fmovsa",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFN  , "fmovsn",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFU  , "fmovsu",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFG  , "fmovsg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFUG , "fmovsug",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFL  , "fmovsl",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFUL , "fmovsul",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFLG , "fmovslg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFNE , "fmovsne",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFE  , "fmovse",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFUE , "fmovsue",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFGE , "fmovsge",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFUGE, "fmovsuge",3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFLE , "fmovsle",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFULE, "fmovslue",3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVSFO  , "fmovso",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )

I(FMOVRDZ  , "fmovrdz",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRDLEZ, "fmovrdlez",3, 2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRDLZ , "fmovrdlz",3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRDNZ , "fmovrdnz",3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRDGZ , "fmovrdgz",3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRDGEZ, "fmovrdgez",3, 2,   0, false, 0, 2,  SPARC_SINGLE,   0)

I(FMOVDA  , "fmovda",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDN  , "fmovdn",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDNE , "fmovdne",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDE  , "fmovde",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDG  , "fmovdg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDLE , "fmovdle",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDGE , "fmovdge",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDL  , "fmovdl",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDGU , "fmovdgu",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDLEU, "fmovdleu",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDCC , "fmovdcc",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDCS , "fmovdcs",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDPOS, "fmovdpos",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDNEG, "fmovdneg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDVC , "fmovdvc",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDVS , "fmovdvs",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )

I(FMOVDFA  , "fmovda",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFN  , "fmovdn",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFU  , "fmovdu",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFG  , "fmovdg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFUG , "fmovdug",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFL  , "fmovdl",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFUL , "fmovdul",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFLG , "fmovdlg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFNE , "fmovdne",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFE  , "fmovde",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFUE , "fmovdue",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFGE , "fmovdge",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFUGE, "fmovduge",3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFLE , "fmovdle",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFULE, "fmovdule",3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVDFO  , "fmovdo",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )

I(FMOVRQZ  , "fmovrqz",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRQLEZ, "fmovrqlez",3, 2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRQLZ , "fmovrqlz",3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRQNZ , "fmovrqnz",3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRQGZ , "fmovrqgz",3,  2,   0, false, 0, 2,  SPARC_SINGLE,   0)
I(FMOVRQGEZ, "fmovrqgez",3, 2,   0, false, 0, 2,  SPARC_SINGLE,   0)

I(FMOVQA  , "fmovqa",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQN  , "fmovqn",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQNE , "fmovqne",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQE  , "fmovqe",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQG  , "fmovqg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQLE , "fmovqle",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQGE , "fmovqge",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQL  , "fmovql",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQGU , "fmovqgu",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQLEU, "fmovqleu",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQCC , "fmovqcc",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQCS , "fmovqcs",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQPOS, "fmovqpos",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQNEG, "fmovqneg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQVC , "fmovqvc",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQVS , "fmovqvs",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )

I(FMOVQFA  , "fmovqa",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFN  , "fmovqn",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFU  , "fmovqu",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFG  , "fmovqg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFUG , "fmovqug",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFL  , "fmovql",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFUL , "fmovqul",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFLG , "fmovqlg",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFNE , "fmovqne",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFE  , "fmovqe",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFUE , "fmovque",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFGE , "fmovqge",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFUGE, "fmovquge",3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFLE , "fmovqle",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFULE, "fmovqule",3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG )
I(FMOVQFO  , "fmovqo",	3,  2,   0, false, 0, 2,  SPARC_SINGLE,  M_CC_FLAG)

// Load integer instructions
// Latency includes 1 cycle for address generation (Sparc IIi),
// plus 3 cycles assumed for average miss penalty (bias towards L1 hits).
// Signed loads of less than 64 bits need an extra cycle for sign-extension.
//
// Not reflected here: After a 3-cycle loads, all subsequent consecutive
// loads also require 3 cycles to avoid contention for the load return
// stage.  Latency returns to 2 cycles after the first cycle with no load.
I(LDSBr, "ldsb", 3,  2, B12, true , 0, 6,  SPARC_LD,   M_LOAD_FLAG)
I(LDSBi, "ldsb", 3,  2, B12, true , 0, 6,  SPARC_LD,   M_LOAD_FLAG)
I(LDSHr, "ldsh", 3,  2, B12, true , 0, 6,  SPARC_LD,   M_LOAD_FLAG)
I(LDSHi, "ldsh", 3,  2, B12, true , 0, 6,  SPARC_LD,   M_LOAD_FLAG)
I(LDSWr, "ldsw", 3,  2, B12, true , 0, 6,  SPARC_LD,   M_LOAD_FLAG)
I(LDSWi, "ldsw", 3,  2, B12, true , 0, 6,  SPARC_LD,   M_LOAD_FLAG)
I(LDUBr, "ldub", 3,  2, B12, true , 0, 5,  SPARC_LD,   M_LOAD_FLAG)
I(LDUBi, "ldub", 3,  2, B12, true , 0, 5,  SPARC_LD,   M_LOAD_FLAG)
I(LDUHr, "lduh", 3,  2, B12, true , 0, 5,  SPARC_LD,   M_LOAD_FLAG)
I(LDUHi, "lduh", 3,  2, B12, true , 0, 5,  SPARC_LD,   M_LOAD_FLAG)
I(LDUWr, "lduw", 3,  2, B12, true , 0, 5,  SPARC_LD,   M_LOAD_FLAG)
I(LDUWi, "lduw", 3,  2, B12, true , 0, 5,  SPARC_LD,   M_LOAD_FLAG)
I(LDXr , "ldx" , 3,  2, B12, true , 0, 5,  SPARC_LD,   M_LOAD_FLAG)
I(LDXi , "ldx" , 3,  2, B12, true , 0, 5,  SPARC_LD,   M_LOAD_FLAG)

// Load floating-point instructions
// Latency includes 1 cycle for address generation (Sparc IIi)
I(LDFr ,   "ld",  3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)
I(LDFi ,   "ld",  3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)
I(LDDFr,   "ldd", 3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)
I(LDDFi,   "ldd", 3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)
I(LDQFr,   "ldq", 3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)
I(LDQFi,   "ldq", 3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)
I(LDFSRr,  "ld",  3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)
I(LDFSRi,  "ld",  3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)
I(LDXFSRr, "ldx", 3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)
I(LDXFSRi, "ldx", 3,  2, B12, true , 0, 5,  SPARC_LD,  M_LOAD_FLAG)

// Store integer instructions.
// Requires 1 cycle for address generation (Sparc IIi).
// Default latency is 0 because value is not explicitly used.
I(STBr, "stb",	  3, -1, B12, true , 0, 0,  SPARC_ST,   M_STORE_FLAG)
I(STBi, "stb",	  3, -1, B12, true , 0, 0,  SPARC_ST,   M_STORE_FLAG)
I(STHr, "sth",	  3, -1, B12, true , 0, 0,  SPARC_ST,   M_STORE_FLAG)
I(STHi, "sth",	  3, -1, B12, true , 0, 0,  SPARC_ST,   M_STORE_FLAG)
I(STWr, "stw",	  3, -1, B12, true , 0, 0,  SPARC_ST,   M_STORE_FLAG)
I(STWi, "stw",	  3, -1, B12, true , 0, 0,  SPARC_ST,   M_STORE_FLAG)
I(STXr, "stx",	  3, -1, B12, true , 0, 0,  SPARC_ST,   M_STORE_FLAG)
I(STXi, "stx",	  3, -1, B12, true , 0, 0,  SPARC_ST,   M_STORE_FLAG)

// Store floating-point instructions (Sparc IIi)
I(STFr,    "st",  3, -1, B12, true , 0, 0,  SPARC_ST,  M_STORE_FLAG)
I(STFi,    "st",  3, -1, B12, true , 0, 0,  SPARC_ST,  M_STORE_FLAG)
I(STDFr,   "std", 3, -1, B12, true , 0, 0,  SPARC_ST,  M_STORE_FLAG)
I(STDFi,   "std", 3, -1, B12, true , 0, 0,  SPARC_ST,  M_STORE_FLAG)
I(STFSRr,  "st",  3, -1, B12, true , 0, 0,  SPARC_ST,  M_STORE_FLAG)
I(STFSRi,  "st",  3, -1, B12, true , 0, 0,  SPARC_ST,  M_STORE_FLAG)
I(STXFSRr, "stx", 3, -1, B12, true , 0, 0,  SPARC_ST,  M_STORE_FLAG)
I(STXFSRi, "stx", 3, -1, B12, true , 0, 0,  SPARC_ST,  M_STORE_FLAG)

// Call, Return and "Jump and link".  Operand (2) for JMPL is marked as
// a "result" because JMPL stores the return address for the call in it.
// Latency includes the delay slot.
I(CALL,      "call",	1, -1, B29, true , 1, 2,  SPARC_CTI,  M_CALL_FLAG)
I(JMPLCALLr, "jmpl",	3,  2, B12, true , 1, 2,  SPARC_CTI,  M_CALL_FLAG)
I(JMPLCALLi, "jmpl",	3,  2, B12, true , 1, 2,  SPARC_CTI,  M_CALL_FLAG)
I(JMPLRETr,  "jmpl",	3,  2, B12, true , 1, 2,  SPARC_CTI,  M_RET_FLAG)
I(JMPLRETi,  "jmpl",	3,  2, B12, true , 1, 2,  SPARC_CTI,  M_RET_FLAG)
I(RETURNr,   "return",	2, -1,   0, false, 1, 2,  SPARC_CTI,  M_RET_FLAG)
I(RETURNi,   "return",	2, -1,   0, false, 1, 2,  SPARC_CTI,  M_RET_FLAG)

// SAVE and restore instructions
I(SAVEr,    "save",	3,  2, B12, true , 0, 1,  SPARC_SINGLE, 0)
I(SAVEi,    "save",	3,  2, B12, true , 0, 1,  SPARC_SINGLE, 0)
I(RESTOREr, "restore",	3,  2, B12, true , 0, 1,  SPARC_SINGLE, 0)
I(RESTOREi, "restore",	3,  2, B12, true , 0, 1,  SPARC_SINGLE, 0)

// Read and Write CCR register from/to an int reg
I(RDCCR,  "rd",         2,   1, 0, false,  0,  1,  SPARC_SINGLE,   M_CC_FLAG)
I(WRCCRr,  "wr",         3,   2, 0, false,  0,  1,  SPARC_SINGLE,   M_CC_FLAG)
I(WRCCRi,  "wr",         3,   2, 0, false,  0,  1,  SPARC_SINGLE,   M_CC_FLAG)

// Synthetic phi operation for near-SSA form of machine code
// Number of operands is variable, indicated by -1.  Result is the first op.
I(PHI, "<phi>", 	-1, 0,   0, false, 0, 0,  SPARC_NONE,  M_DUMMY_PHI_FLAG)


#undef B5
#undef B6
#undef B12
#undef B15
#undef B18
#undef B21
#undef B22
#undef B29

#undef I
