summaryrefslogtreecommitdiffstats
path: root/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
diff options
context:
space:
mode:
authorKristian Høgsberg Kristensen <krh@bitplanet.net>2015-12-10 12:27:38 -0800
committerKristian Høgsberg Kristensen <krh@bitplanet.net>2015-12-29 10:39:25 -0800
commitcddfc2cefa93b884c40329dcb193fe4fb22143ab (patch)
tree5f7de35cd73cbdcccb772524b8b80e08612c2c0c /src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
parent17ebb55a14b5a9aa639845fbda9330ef9421834a (diff)
downloadexternal_mesa3d-cddfc2cefa93b884c40329dcb193fe4fb22143ab.zip
external_mesa3d-cddfc2cefa93b884c40329dcb193fe4fb22143ab.tar.gz
external_mesa3d-cddfc2cefa93b884c40329dcb193fe4fb22143ab.tar.bz2
i965: Add support for gl_DrawIDARB and enable extension
We have to break open a new vec4 for gl_DrawIDARB. We've used up all space in the vec4 we use for SGVS and gl_DrawIDARB has to come from its own separate vertex buffer anyway. This is because we point the vb for base vertex and base instance into the draw parameter BO for indirect draw calls, but the draw id is generated by mesa in a different buffer. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_vec4_nir.cpp')
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_nir.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index c20da9b..a3bdbc3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -85,6 +85,13 @@ vec4_visitor::nir_setup_system_value_intrinsic(nir_intrinsic_instr *instr)
glsl_type::int_type);
break;
+ case nir_intrinsic_load_draw_id:
+ reg = &nir_system_values[SYSTEM_VALUE_DRAW_ID];
+ if (reg->file == BAD_FILE)
+ *reg = *make_reg_for_system_value(SYSTEM_VALUE_DRAW_ID,
+ glsl_type::int_type);
+ break;
+
default:
break;
}
@@ -677,6 +684,7 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
case nir_intrinsic_load_base_vertex:
case nir_intrinsic_load_instance_id:
case nir_intrinsic_load_base_instance:
+ case nir_intrinsic_load_draw_id:
case nir_intrinsic_load_invocation_id:
case nir_intrinsic_load_tess_level_inner:
case nir_intrinsic_load_tess_level_outer: {