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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-04-28 14:40:51 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-05-14 13:34:21 -0700 |
| commit | 7be100ac9af52b1ab5e2c34b45aba0d66304d55a (patch) | |
| tree | 30587286f08c2187cf130ec8108fac7e37494910 /src/mesa/drivers/dri/i965/gen7_wm_state.c | |
| parent | 1ec466d0ff59ab17edef95c84ed733c1fea5655e (diff) | |
| download | external_mesa3d-7be100ac9af52b1ab5e2c34b45aba0d66304d55a.zip external_mesa3d-7be100ac9af52b1ab5e2c34b45aba0d66304d55a.tar.gz external_mesa3d-7be100ac9af52b1ab5e2c34b45aba0d66304d55a.tar.bz2 | |
i965/gen7_wm: Move where we set the fast clear op
This better matches gen8 state setup
Acked-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 17dea99..8d2e2c3 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -214,6 +214,8 @@ gen7_upload_ps_state(struct brw_context *brw, if (prog_data->num_varying_inputs != 0) dw4 |= GEN7_PS_ATTRIBUTE_ENABLE; + dw4 |= fast_clear_op; + if (prog_data->prog_offset_16 || prog_data->no_8) { dw4 |= GEN7_PS_16_DISPATCH_ENABLE; @@ -243,8 +245,6 @@ gen7_upload_ps_state(struct brw_context *brw, ksp0 = stage_state->prog_offset; } - dw4 |= fast_clear_op; - BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); OUT_BATCH(ksp0); |