diff options
Diffstat (limited to 'src/gallium/drivers/nouveau/nv30/nv30_clear.c')
-rw-r--r-- | src/gallium/drivers/nouveau/nv30/nv30_clear.c | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_clear.c b/src/gallium/drivers/nouveau/nv30/nv30_clear.c index 4217bca..b0ab91a 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_clear.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_clear.c @@ -58,8 +58,11 @@ nv30_clear(struct pipe_context *pipe, unsigned buffers, struct pipe_framebuffer_state *fb = &nv30->framebuffer; uint32_t colr = 0, zeta = 0, mode = 0; - if (!nv30_state_validate(nv30, NV30_NEW_FRAMEBUFFER | NV30_NEW_SCISSOR, true)) + pipe_mutex_lock(nv30->screen->base.push_mutex); + if (!nv30_state_validate(nv30, NV30_NEW_FRAMEBUFFER | NV30_NEW_SCISSOR, true)) { + pipe_mutex_unlock(nv30->screen->base.push_mutex); return; + } if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) { colr = pack_rgba(fb->cbufs[0]->format, color->f); @@ -96,6 +99,7 @@ nv30_clear(struct pipe_context *pipe, unsigned buffers, PUSH_DATA (push, mode); nv30_state_release(nv30); + pipe_mutex_unlock(nv30->screen->base.push_mutex); } static void @@ -126,11 +130,15 @@ nv30_clear_render_target(struct pipe_context *pipe, struct pipe_surface *ps, rt_format |= NV30_3D_RT_FORMAT_TYPE_LINEAR; } + pipe_mutex_lock(nv30->screen->base.push_mutex); + refn.bo = mt->base.bo; refn.flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_WR; if (nouveau_pushbuf_space(push, 16, 1, 0) || - nouveau_pushbuf_refn (push, &refn, 1)) + nouveau_pushbuf_refn (push, &refn, 1)) { + pipe_mutex_unlock(nv30->screen->base.push_mutex); return; + } BEGIN_NV04(push, NV30_3D(RT_ENABLE), 1); PUSH_DATA (push, NV30_3D_RT_ENABLE_COLOR0); @@ -155,6 +163,8 @@ nv30_clear_render_target(struct pipe_context *pipe, struct pipe_surface *ps, NV30_3D_CLEAR_BUFFERS_COLOR_B | NV30_3D_CLEAR_BUFFERS_COLOR_A); + pipe_mutex_unlock(nv30->screen->base.push_mutex); + nv30->dirty |= NV30_NEW_FRAMEBUFFER | NV30_NEW_SCISSOR; } @@ -191,11 +201,15 @@ nv30_clear_depth_stencil(struct pipe_context *pipe, struct pipe_surface *ps, if (buffers & PIPE_CLEAR_STENCIL) mode |= NV30_3D_CLEAR_BUFFERS_STENCIL; + pipe_mutex_lock(nv30->screen->base.push_mutex); + refn.bo = mt->base.bo; refn.flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_WR; if (nouveau_pushbuf_space(push, 32, 1, 0) || - nouveau_pushbuf_refn (push, &refn, 1)) + nouveau_pushbuf_refn (push, &refn, 1)) { + pipe_mutex_unlock(nv30->screen->base.push_mutex); return; + } BEGIN_NV04(push, NV30_3D(RT_ENABLE), 1); PUSH_DATA (push, 0); @@ -221,6 +235,8 @@ nv30_clear_depth_stencil(struct pipe_context *pipe, struct pipe_surface *ps, BEGIN_NV04(push, NV30_3D(CLEAR_BUFFERS), 1); PUSH_DATA (push, mode); + pipe_mutex_unlock(nv30->screen->base.push_mutex); + nv30->dirty |= NV30_NEW_FRAMEBUFFER | NV30_NEW_SCISSOR; } |