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-rw-r--r--src/mesa/drivers/dri/i915/i830_reg.h4
-rw-r--r--src/mesa/drivers/dri/i915/i830_texstate.c31
-rw-r--r--src/mesa/drivers/dri/i915/i830_vtbl.c57
-rw-r--r--src/mesa/drivers/dri/i915/i915_context.c1
-rw-r--r--src/mesa/drivers/dri/i915/i915_fragprog.c16
-rw-r--r--src/mesa/drivers/dri/i915/i915_texstate.c2
-rw-r--r--src/mesa/drivers/dri/i915/i915_vtbl.c58
7 files changed, 98 insertions, 71 deletions
diff --git a/src/mesa/drivers/dri/i915/i830_reg.h b/src/mesa/drivers/dri/i915/i830_reg.h
index ae13170..99ee1bb 100644
--- a/src/mesa/drivers/dri/i915/i830_reg.h
+++ b/src/mesa/drivers/dri/i915/i830_reg.h
@@ -585,6 +585,8 @@
#define TM0S2_VERITCAL_LINE_STRIDE_OFF (1<<12)
#define TM0S2_OUTPUT_CHAN_SHIFT 10
#define TM0S2_OUTPUT_CHAN_MASK (3<<10)
+#define TM0S2_BASE_MIP_LEVEL_SHIFT 1
+#define TM0S2_LOD_PRECLAMP (1 << 0)
#define TM0S3_MIP_FILTER_MASK (0x3<<30)
#define TM0S3_MIP_FILTER_SHIFT 30
@@ -605,6 +607,8 @@
#define TM0S3_MAX_MIP_MASK (0xff<<9)
#define TM0S3_MIN_MIP_SHIFT 3
#define TM0S3_MIN_MIP_MASK (0x3f<<3)
+#define TM0S3_MIN_MIP_SHIFT_830 5
+#define TM0S3_MIN_MIP_MASK_830 (0x3f<<5)
#define TM0S3_KILL_PIXEL (1<<2)
#define TM0S3_KEYED_FILTER (1<<1)
#define TM0S3_CHROMA_KEY (1<<0)
diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c b/src/mesa/drivers/dri/i915/i830_texstate.c
index b3bb883..c35b4b5 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -28,13 +28,14 @@
#include "main/mtypes.h"
#include "main/enums.h"
#include "main/colormac.h"
+#include "main/macros.h"
#include "intel_mipmap_tree.h"
#include "intel_tex.h"
#include "i830_context.h"
#include "i830_reg.h"
-
+#include "intel_chipset.h"
static GLuint
@@ -139,9 +140,9 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
/* Get first image here, since intelObj->firstLevel will get set in
* the intel_finalize_mipmap_tree() call above.
*/
- firstImage = tObj->Image[0][intelObj->firstLevel];
+ firstImage = tObj->Image[0][tObj->BaseLevel];
- intel_miptree_get_image_offset(intelObj->mt, intelObj->firstLevel, 0, 0,
+ intel_miptree_get_image_offset(intelObj->mt, tObj->BaseLevel, 0, 0,
&dst_x, &dst_y);
drm_intel_bo_reference(intelObj->mt->region->buffer);
@@ -189,6 +190,8 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
{
GLuint minFilt, mipFilt, magFilt;
+ float maxlod;
+ uint32_t minlod_fixed, maxlod_fixed;
switch (tObj->MinFilter) {
case GL_NEAREST:
@@ -252,10 +255,24 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
state[I830_TEXREG_TM0S3] |= SS2_COLORSPACE_CONVERSION;
#endif
- state[I830_TEXREG_TM0S3] |= ((intelObj->lastLevel -
- intelObj->firstLevel) *
- 4) << TM0S3_MIN_MIP_SHIFT;
-
+ /* We get one field with fraction bits for the maximum
+ * addressable (smallest resolution) LOD. Use it to cover both
+ * MAX_LEVEL and MAX_LOD.
+ */
+ minlod_fixed = U_FIXED(CLAMP(tObj->MinLod, 0.0, 11), 4);
+ maxlod = MIN2(tObj->MaxLod, tObj->_MaxLevel - tObj->BaseLevel);
+ if (intel->intelScreen->deviceID == PCI_CHIP_I855_GM ||
+ intel->intelScreen->deviceID == PCI_CHIP_I865_G) {
+ maxlod_fixed = U_FIXED(CLAMP(maxlod, 0.0, 11.75), 2);
+ maxlod_fixed = MAX2(maxlod_fixed, (minlod_fixed + 3) >> 2);
+ state[I830_TEXREG_TM0S3] |= maxlod_fixed << TM0S3_MIN_MIP_SHIFT;
+ state[I830_TEXREG_TM0S2] |= TM0S2_LOD_PRECLAMP;
+ } else {
+ maxlod_fixed = U_FIXED(CLAMP(maxlod, 0.0, 11), 0);
+ maxlod_fixed = MAX2(maxlod_fixed, (minlod_fixed + 15) >> 4);
+ state[I830_TEXREG_TM0S3] |= maxlod_fixed << TM0S3_MIN_MIP_SHIFT_830;
+ }
+ state[I830_TEXREG_TM0S3] |= minlod_fixed << TM0S3_MAX_MIP_SHIFT;
state[I830_TEXREG_TM0S3] |= ((minFilt << TM0S3_MIN_FILTER_SHIFT) |
(mipFilt << TM0S3_MIP_FILTER_SHIFT) |
(magFilt << TM0S3_MAG_FILTER_SHIFT));
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c
index f7fdb78..ebdefea 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -364,7 +364,7 @@ i830_emit_invarient_state(struct intel_context *intel)
#define emit( intel, state, size ) \
- intel_batchbuffer_data(intel->batch, state, size )
+ intel_batchbuffer_data(intel->batch, state, size, false)
static GLuint
get_dirty(struct i830_hw_state *state)
@@ -429,7 +429,8 @@ i830_emit_state(struct intel_context *intel)
* batchbuffer fills up.
*/
intel_batchbuffer_require_space(intel->batch,
- get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
+ false);
count = 0;
again:
aper_count = 0;
@@ -534,14 +535,9 @@ i830_emit_state(struct intel_context *intel)
BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1);
OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
- if (state->tex_buffer[i]) {
- OUT_RELOC(state->tex_buffer[i],
- I915_GEM_DOMAIN_SAMPLER, 0,
- state->tex_offset[i]);
- }
- else {
- OUT_BATCH(state->tex_offset[i]);
- }
+ OUT_RELOC(state->tex_buffer[i],
+ I915_GEM_DOMAIN_SAMPLER, 0,
+ state->tex_offset[i]);
OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]);
OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]);
@@ -584,6 +580,27 @@ i830_destroy_context(struct intel_context *intel)
_tnl_free_vertices(&intel->ctx);
}
+static uint32_t i830_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
+{
+ [MESA_FORMAT_ARGB8888] = DV_PF_8888,
+ [MESA_FORMAT_XRGB8888] = DV_PF_8888,
+ [MESA_FORMAT_RGB565] = DV_PF_565,
+ [MESA_FORMAT_ARGB1555] = DV_PF_1555,
+ [MESA_FORMAT_ARGB4444] = DV_PF_4444,
+};
+
+static bool
+i830_render_target_supported(gl_format format)
+{
+ if (format == MESA_FORMAT_S8_Z24 ||
+ format == MESA_FORMAT_X8_Z24 ||
+ format == MESA_FORMAT_Z16) {
+ return true;
+ }
+
+ return i830_render_target_format_for_mesa_format[format] != 0;
+}
+
static void
i830_set_draw_region(struct intel_context *intel,
struct intel_region *color_regions[],
@@ -623,24 +640,7 @@ i830_set_draw_region(struct intel_context *intel,
DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */
if (irb != NULL) {
- switch (irb->Base.Format) {
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
- value |= DV_PF_8888;
- break;
- case MESA_FORMAT_RGB565:
- value |= DV_PF_565;
- break;
- case MESA_FORMAT_ARGB1555:
- value |= DV_PF_1555;
- break;
- case MESA_FORMAT_ARGB4444:
- value |= DV_PF_4444;
- break;
- default:
- _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
- irb->Base.Format);
- }
+ value |= i830_render_target_format_for_mesa_format[irb->Base.Format];
}
if (depth_region && depth_region->cpp == 4) {
@@ -728,4 +728,5 @@ i830InitVtbl(struct i830_context *i830)
i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
i830->intel.vtbl.finish_batch = intel_finish_vb;
i830->intel.vtbl.invalidate_state = i830_invalidate_state;
+ i830->intel.vtbl.render_target_supported = i830_render_target_supported;
}
diff --git a/src/mesa/drivers/dri/i915/i915_context.c b/src/mesa/drivers/dri/i915/i915_context.c
index f943f81..f32f3cf 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -176,6 +176,7 @@ i915CreateContext(int api,
ctx->ShaderCompilerOptions[MESA_SHADER_VERTEX].EmitCondCodes = GL_TRUE;
ctx->ShaderCompilerOptions[MESA_SHADER_FRAGMENT].EmitNoIfs = GL_TRUE;
ctx->ShaderCompilerOptions[MESA_SHADER_FRAGMENT].EmitNoNoise = GL_TRUE;
+ ctx->ShaderCompilerOptions[MESA_SHADER_FRAGMENT].EmitNoPow = GL_TRUE;
ctx->Const.MaxDrawBuffers = 1;
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c
index c00ee41..1c6e984 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -569,10 +569,14 @@ upload_program(struct i915_fragment_program *p)
if (inst->DstReg.CondMask == COND_TR) {
tmp = i915_get_utemp(p);
+ /* The KIL instruction discards the fragment if any component of
+ * the source is < 0. Emit an immediate operand of {-1}.xywz.
+ */
i915_emit_texld(p, get_live_regs(p, inst),
tmp, A0_DEST_CHANNEL_ALL,
0, /* use a dummy dest reg */
- swizzle(tmp, ONE, ONE, ONE, ONE), /* always */
+ negate(swizzle(tmp, ONE, ONE, ONE, ONE),
+ 1, 1, 1, 1),
T0_TEXKILL);
} else {
p->error = 1;
@@ -1158,11 +1162,6 @@ translate_program(struct i915_fragment_program *p)
fixup_depth_write(p);
i915_fini_program(p);
- if (INTEL_DEBUG & DEBUG_WM) {
- printf("i915:\n");
- i915_disassemble_program(i915->state.Program, i915->state.ProgramSize);
- }
-
p->translated = 1;
}
@@ -1423,6 +1422,11 @@ i915ValidateFragmentProgram(struct i915_context *i915)
if (!p->on_hardware)
i915_upload_program(i915, p);
+
+ if (INTEL_DEBUG & DEBUG_WM) {
+ printf("i915:\n");
+ i915_disassemble_program(i915->state.Program, i915->state.ProgramSize);
+ }
}
void
diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c
index c724a21..af140c8 100644
--- a/src/mesa/drivers/dri/i915/i915_texstate.c
+++ b/src/mesa/drivers/dri/i915/i915_texstate.c
@@ -156,7 +156,7 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
/* Get first image here, since intelObj->firstLevel will get set in
* the intel_finalize_mipmap_tree() call above.
*/
- firstImage = tObj->Image[0][intelObj->firstLevel];
+ firstImage = tObj->Image[0][tObj->BaseLevel];
drm_intel_bo_reference(intelObj->mt->region->buffer);
i915->state.tex_buffer[unit] = intelObj->mt->region->buffer;
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 59dfe08..a94b957 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -217,7 +217,7 @@ i915_emit_invarient_state(struct intel_context *intel)
#define emit(intel, state, size ) \
- intel_batchbuffer_data(intel->batch, state, size)
+ intel_batchbuffer_data(intel->batch, state, size, false)
static GLuint
get_dirty(struct i915_hw_state *state)
@@ -300,7 +300,8 @@ i915_emit_state(struct intel_context *intel)
* batchbuffer fills up.
*/
intel_batchbuffer_require_space(intel->batch,
- get_state_size(state) + INTEL_PRIM_EMIT_SIZE);
+ get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
+ false);
count = 0;
again:
aper_count = 0;
@@ -435,15 +436,9 @@ i915_emit_state(struct intel_context *intel)
OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
for (i = 0; i < I915_TEX_UNITS; i++)
if (dirty & I915_UPLOAD_TEX(i)) {
-
- if (state->tex_buffer[i]) {
- OUT_RELOC(state->tex_buffer[i],
- I915_GEM_DOMAIN_SAMPLER, 0,
- state->tex_offset[i]);
- }
- else {
- OUT_BATCH(state->tex_offset[i]);
- }
+ OUT_RELOC(state->tex_buffer[i],
+ I915_GEM_DOMAIN_SAMPLER, 0,
+ state->tex_offset[i]);
OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
@@ -523,6 +518,27 @@ i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
}
}
+static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
+{
+ [MESA_FORMAT_ARGB8888] = DV_PF_8888,
+ [MESA_FORMAT_XRGB8888] = DV_PF_8888,
+ [MESA_FORMAT_RGB565] = DV_PF_565 | DITHER_FULL_ALWAYS,
+ [MESA_FORMAT_ARGB1555] = DV_PF_1555 | DITHER_FULL_ALWAYS,
+ [MESA_FORMAT_ARGB4444] = DV_PF_4444 | DITHER_FULL_ALWAYS,
+};
+
+static bool
+i915_render_target_supported(gl_format format)
+{
+ if (format == MESA_FORMAT_S8_Z24 ||
+ format == MESA_FORMAT_X8_Z24 ||
+ format == MESA_FORMAT_Z16) {
+ return true;
+ }
+
+ return i915_render_target_format_for_mesa_format[format] != 0;
+}
+
static void
i915_set_draw_region(struct intel_context *intel,
struct intel_region *color_regions[],
@@ -562,24 +578,7 @@ i915_set_draw_region(struct intel_context *intel,
DSTORG_VERT_BIAS(0x8) | /* .5 */
LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
if (irb != NULL) {
- switch (irb->Base.Format) {
- case MESA_FORMAT_ARGB8888:
- case MESA_FORMAT_XRGB8888:
- value |= DV_PF_8888;
- break;
- case MESA_FORMAT_RGB565:
- value |= DV_PF_565 | DITHER_FULL_ALWAYS;
- break;
- case MESA_FORMAT_ARGB1555:
- value |= DV_PF_1555 | DITHER_FULL_ALWAYS;
- break;
- case MESA_FORMAT_ARGB4444:
- value |= DV_PF_4444 | DITHER_FULL_ALWAYS;
- break;
- default:
- _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
- irb->Base.Format);
- }
+ value |= i915_render_target_format_for_mesa_format[irb->Base.Format];
}
/* This isn't quite safe, thus being hidden behind an option. When changing
@@ -686,4 +685,5 @@ i915InitVtbl(struct i915_context *i915)
i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
i915->intel.vtbl.finish_batch = intel_finish_vb;
+ i915->intel.vtbl.render_target_supported = i915_render_target_supported;
}
generated by cgit v1.1 at 2025-08-21 21:05:58 +0000