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* i965/fs: Move some of the prog_data setup into brw_wm_emitJason Ekstrand2015-10-192-98/+100
| | | | | | | | This commit moves the common/modern stuff. Some legacy stuff such as setting use_alt_mode was left because it needs to know whether or not we're an ARB program. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/cs: Rework cs_emit to take a nir_shader and a brw_compilerJason Ekstrand2015-10-193-29/+42
| | | | | | | This commit removes all dependence on GL state by getting rid of the brw_context parameter and the GL data structures. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/gs: Rework gs_emit to take a nir_shader and a brw_compilerJason Ekstrand2015-10-193-40/+29
| | | | | | | | | This commit removes all dependence on GL state by getting rid of the brw_context parameter and the GL data structures. Unfortunately, we still have to pass in the gl_shader_program for gen6 because it's needed for transform feedback. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/vs: Rework vs_emit to take a nir_shader and a brw_compilerJason Ekstrand2015-10-193-49/+49
| | | | | | | | | | | This commit removes all dependence on GL state by getting rid of the brw_context parameter and the GL data structures. v2 (Jason Ekstrand): - Patch use_legacy_snorm_formula through as a function argument rather than trying to go through the shader key. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/fs: Rework wm_fs_emit to take a nir_shader and a brw_compilerJason Ekstrand2015-10-193-39/+47
| | | | | | | This commit removes all dependence on GL state by getting rid of the brw_context parameter and the GL data structures. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Use a const nir_shader in backend_shaderJason Ekstrand2015-10-1911-12/+12
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/vec4: Remove gl_program and gl_shader_program from the generatorJason Ekstrand2015-10-194-29/+20
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/fs: Remove the gl_program from the generatorJason Ekstrand2015-10-195-9/+5
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* nir/info: Add a few bits of info for fragment shadersJason Ekstrand2015-10-193-0/+29
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* nir/info: Add compute shader local size to nir_shader_infoJason Ekstrand2015-10-192-0/+12
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* nir/info: Move the GS info into a stage-specific info unionJason Ekstrand2015-10-192-8/+18
| | | | | | | | This way we can have other stage-specific info without consuming too much extra space. While we're at it, we make sure that the geometry info is only set if we're actually a goemetry shader. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* mesa: Move gl_frag_depth_layout from mtypes.h to shader_enums.hJason Ekstrand2015-10-192-18/+17
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* nir: Add a label to nir_shader_infoJason Ekstrand2015-10-193-0/+7
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/asm: Explicitly use a nir_instr for IR annotationsJason Ekstrand2015-10-194-19/+5
| | | | | | | Now that everything goes through NIR, we don't need this to be a void pointer anymore. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* scons: Build nir/glsl_types.cpp once.Jose Fonseca2015-10-198-29/+8
| | | | | | | | | | | | Undoes early hacks, and ensures nir/glsl_types.cpp is built once, and only once. The root problem is that SCons doesn't know about NIR nor any source file in the NIR_FILES source list. Tested with libgl-gdi and libgl-xlib scons targets. Reviewed-by: Brian Paul <brianp@vmware.com>
* svga: fix incorrect round-down arithmeticBrian Paul2015-10-191-1/+1
| | | | | | | | | Spotted by Roland. Luckily, this code should never really be hit since the const buffer size and offset should already be multiples of 16. I could probably add more assertions to that effect, but let's just fix the arithmetic for now. Reviewed-by: Roland Scheidegger <sroland@vmware.com>
* glsl: fix segfault when indirect indexing a buffer variable which is an arraySamuel Iglesias Gonsalvez2015-10-191-1/+2
| | | | | | | Fixes a regression added by bb5aeb854915ba67abc56257f830d002c956439e. Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com> Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
* st/va: Added support for NV12 to IYUV conversion in vlVaGetImageIndrajit Das2015-10-191-3/+5
| | | | Reviewed-by: Christian König <christian.koenig@amd.com>
* st/va: Used correct parameter to derive the value of the "h" variable in ↵Indrajit Das2015-10-191-1/+1
| | | | | | | | vlVaCreateImage Cc: "11.0" <mesa-stable@lists.freedesktop.org> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
* glsl_to_tgsi: Use {Num}UniformBlocks instead of {Num}BufferInterfaceBlocksIago Toral Quiroga2015-10-191-2/+2
| | | | | | | The latter holds both UBOs and SSBOs, but here we only want UBOs. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* st/mesa: Use {Num}UniformBlocks instead of {Num}BufferInterfaceBlocksIago Toral Quiroga2015-10-191-2/+2
| | | | | | | The latter holds both UBOs and SSBOs, but here we only want UBOs. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* i965: Do not use NumBufferInterfaceBlocksIago Toral Quiroga2015-10-191-1/+1
| | | | | | | | | | This is the only place in the driver where we use this. Since we now work with separate index spaces, always use NumUniformBlocks and NumShaderStorageBlocks instead of NumBufferInterfaceBlocks to be more consistent with the rest of the code. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* main: GL_ACTIVE_UNIFORM_BLOCK_MAX_NAME_LENGTH is about UBOS, not SSBOsIago Toral Quiroga2015-10-191-2/+2
| | | | | Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* main: Use NumUniformBlocks to count UBOsIago Toral Quiroga2015-10-191-5/+1
| | | | | | | | | Now that we have separate index spaces for UBOs and SSBOs we do not need to iterate through BufferInterfaceBlocks any more, we can just take the UBO count directly from NumUniformBlocks. Reviewed-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* ilo: set VME for 3DSTATE_PSChia-I Wu2015-10-181-1/+6
| | | | | When the bit is not set, we can see sampling artifacts on triangle edges when the mip filter is not GEN6_MIPFILTER_NONE.
* ilo: ignore prefer_linear_threshold when zeroChia-I Wu2015-10-182-3/+3
| | | | This was the intended behavior but it did not work as intended until now.
* ilo: remove some unused kernel paramsChia-I Wu2015-10-182-22/+0
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* ilo: remove unused ilo_shader_get_type()Chia-I Wu2015-10-182-12/+0
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* ilo: remove u_debug.h inclusion from ilo_core.hChia-I Wu2015-10-182-1/+2
| | | | Move it to ilo_debug.h.
* ilo: remove u_memory.h inclusion from ilo_core.hChia-I Wu2015-10-183-1/+3
| | | | We do not make allocations generally in the core.
* nvc0: do not bind input params at compute state init on FermiSamuel Pitoiset2015-10-181-8/+0
| | | | | | | | | | | | | | | | | | It looks like binding a constant buffer on compute overwrites the 3D state. To avoid that, we already re-bind all the 3D constant buffers after launching a compute grid but this is not enough. Binding the constant buffer of input parameters for the compute state at initialization corrupts the 3D constant buffers, and it's just useless to bind it because this is not needed until we really launch a grid. This fixes some piglit regressions related to interpolation tests introduced in "nvc0: enable compute support by default on Fermi". Fixes: 00d6186 (nvc0: enable compute support by default on Fermi) Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
* i965/vs: Drop hack that created NIR for fixed function vertex programs.Kenneth Graunke2015-10-171-12/+0
| | | | | | | | Marek made core Mesa call ProgramStringNotify(), which solves this properly. The hack is no longer needed. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965/nir: Switch on shader stage in nir_lower_outputs().Kenneth Graunke2015-10-171-5/+21
| | | | | | | | | | | VS, GS, and FS continue doing the same thing they did before. We can simplify the FS code a bit because it is always scalar. Compute shaders now assert that there are no outputs instead of doing a loop over 0 outputs. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
* radeonsi: don't use the AMDGPU intrinsic for CMPMarek Olšák2015-10-171-9/+22
| | | | | | | No difference according to shader-db. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
* radeonsi: use LRP from gallivmMarek Olšák2015-10-171-2/+0
| | | | | | | | | | | | | | | | | | Totals: SGPRS: 344552 -> 344368 (-0.05 %) VGPRS: 197132 -> 197552 (0.21 %) Code Size: 7375376 -> 7366304 (-0.12 %) bytes LDS: 91 -> 91 (0.00 %) blocks Scratch: 1679360 -> 1615872 (-3.78 %) bytes per wave Totals from affected shaders: SGPRS: 47736 -> 47552 (-0.39 %) VGPRS: 27952 -> 28372 (1.50 %) Code Size: 1392724 -> 1383652 (-0.65 %) bytes LDS: 39 -> 39 (0.00 %) blocks Scratch: 513024 -> 449536 (-12.38 %) bytes per wave Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: don't emit AMDGPU intrinsics for integer abs, min, maxMarek Olšák2015-10-171-10/+50
| | | | | | | No difference according to shader-db. (with the new S_ABS_I32 pattern) Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
* radeonsi: don't emit AMDGPU intrinsics for EX2, ROUND, TRUNCMarek Olšák2015-10-171-3/+3
| | | | | | | No difference according to shader-db. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
* radeonsi: initialize output, temp, and address registers to "undef"Marek Olšák2015-10-171-4/+15
| | | | | | | | | | | | | | | | | | | | | This removes "v_mov v0, 0" which typically occurs before exports. Totals: SGPRS: 345216 -> 344552 (-0.19 %) VGPRS: 197684 -> 197132 (-0.28 %) Code Size: 7390408 -> 7375376 (-0.20 %) bytes LDS: 91 -> 91 (0.00 %) blocks Scratch: 1842176 -> 1679360 (-8.84 %) bytes per wave Totals from affected shaders: SGPRS: 101336 -> 100672 (-0.66 %) VGPRS: 53920 -> 53368 (-1.02 %) Code Size: 2170176 -> 2155144 (-0.69 %) bytes LDS: 2 -> 2 (0.00 %) blocks Scratch: 1015808 -> 852992 (-16.03 %) bytes per wave Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
* gallivm: implement the correct version of LRPMarek Olšák2015-10-171-6/+13
| | | | | | | | | The previous version has precision issues. This can be a problem with tessellation. Sadly, I can't find the article where I read it anymore. I'm not sure if the unsafe-fp-math flag would be enough to revert this. v2: added the comment
* gallivm: set correct opcode info from unary/binary/ternary emitsMarek Olšák2015-10-171-3/+6
| | | | | | | | and clear the emit_data structure. The new radeonsi min/max opcode implementation requires this. (it looks good according to Roland S.)
* radeonsi: implement vertex color clampingMarek Olšák2015-10-175-4/+52
| | | | | | This is only supported in the compatibility profile (without GS and tess). Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: implement fragment color clampingMarek Olšák2015-10-176-2/+18
| | | | | | using the shader key for now. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: clean up other scratch buffer functionsMarek Olšák2015-10-171-15/+8
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: clean up copy-pasted scratch buffer updatesMarek Olšák2015-10-171-26/+13
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: unify shader create functionsMarek Olšák2015-10-171-40/+9
| | | | | | The shader specifies the processor type, so use that instead. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: unify shader delete functionsMarek Olšák2015-10-171-67/+17
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: fix a GS copy shader leakMarek Olšák2015-10-171-1/+3
| | | | | Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: remove an unused ctx parameter in si_shader_destroyMarek Olšák2015-10-174-6/+6
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: print export_prim_id from the shader keyMarek Olšák2015-10-171-0/+2
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: disable NaNs for LS and HSMarek Olšák2015-10-171-2/+4
| | | | | | | They're disabled for all other shaders except compute, but I forgot to do this for tess stages. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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