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* draw: don't assume fixed offset for data in struct vertex_infoRoland Scheidegger2015-12-111-5/+3
| | | | | | Otherwise, if struct vertex_info is changed, you're in for some surprises... Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
* i965/gen9: Don't do fast clears when GL_FRAMEBUFFER_SRGB is enabledNeil Roberts2015-12-111-0/+11
| | | | | | | | | When GL_FRAMEBUFFER_SRGB is enabled any single-sampled renderbuffers are resolved in intel_update_state because the hardware can't cope with fast clears on SRGB buffers. In that case it's pointless to do a fast clear because it will just be immediately resolved. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/gen9: Allow fast clears for non-MSRT SRGB buffersNeil Roberts2015-12-111-1/+2
| | | | | | | | | | | | | | | SRGB buffers are not marked as losslessly compressible so previously they would not be used for fast clears. However in practice the hardware will never actually see that we are using SRGB buffers for fast clears if we use the linear equivalent format when clearing and make sure to resolve the buffer as a linear format before sampling from it. This is an important use case because by default the window system framebuffers are created as SRGB so without this fast clears won't be used there. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/gen9: Resolve SRGB color buffers when GL_FRAMEBUFFER_SRGB enabledNeil Roberts2015-12-111-0/+27
| | | | | | | | | | SKL can't cope with the CCS buffer for SRGB buffers. Normally the hardware won't see the SRGB formats because when GL_FRAMEBUFFER_SRGB is disabled these get mapped to their linear equivalents. In order to avoid relying on the CCS buffer when it is enabled this patch now makes it flush the renderbuffers. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/gen8+: Don't upload the MCS buffer for single-sampled texturesNeil Roberts2015-12-111-1/+5
| | | | | | | | | | | For single-sampled textures the MCS buffer is only used to implement fast clears. However the surface always needs to be resolved before being used as a texture anyway so the the MCS buffer doesn't actually achieve anything. This is important for Gen9 because in that case SRGB surfaces are not supported for fast clears and we don't want the hardware to see the MCS buffer in that case. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/meta-fast-clear: Disable GL_FRAMEBUFFER_SRGB during clearNeil Roberts2015-12-111-0/+16
| | | | | | | | | | | | | | | Adds MESA_META_FRAMEBUFFER_SRGB to the meta save state so that GL_FRAMEBUFFER_SRGB will be disabled when performing the fast clear. That way the render surface state will be programmed with the linear equivalent format during the clear. This is important for Gen9 because the SRGB formats are not marked as losslessly compressible so in theory they aren't support for fast clears. It shouldn't make any difference whether GL_FRAMEBUFFER_SRGB is enabled for the fast clear operation because the color is not actually written to the framebuffer so there is no chance for the hardware to apply the SRGB conversion on it anyway. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* winsys/amdgpu: clear the buffer cache on mmap failure and try againMarek Olšák2015-12-111-0/+5
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/radeon: clear the buffer cache on mmap failure and try againMarek Olšák2015-12-111-3/+10
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: clear the buffer cache on allocation failure and try againMarek Olšák2015-12-111-2/+7
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/radeon: clear the buffer cache on allocation failure and try againMarek Olšák2015-12-111-2/+7
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/radeon: remove radeon_winsys_cs_handleMarek Olšák2015-12-1139-173/+130
| | | | | | | | "radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf". Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/radeon: use pb_cache instead of pb_cache_managerMarek Olšák2015-12-114-178/+75
| | | | | | | | This is a prerequisite for the removal of radeon_winsys_cs_handle. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/radeon: use radeon_bomgr lessMarek Olšák2015-12-112-16/+8
| | | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/radeon: rename radeon_bomgr_init_functionsMarek Olšák2015-12-113-3/+3
| | | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/radeon: move variables from radeon_bomgr to radeon_drm_winsysMarek Olšák2015-12-113-126/+129
| | | | | | | | radeon_bomgr is going away. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/radeon: remove redundant radeon_bomgr::vaMarek Olšák2015-12-111-7/+4
| | | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: don't use the "rws" abbreviation for amdgpu_winsysMarek Olšák2015-12-114-20/+20
| | | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* winsys/amdgpu: use pb_cache instead of pb_cache_managerMarek Olšák2015-12-114-173/+78
| | | | | | | | This is a prerequisite for the removal of radeon_winsys_cs_handle. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/pb_bufmgr_cache: use the new pb_cache moduleMarek Olšák2015-12-111-198/+34
| | | | | | Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com>
* gallium/pb_cache: add a copy of cache bufmgr independent of pb_managerMarek Olšák2015-12-113-0/+362
| | | | | | | | | | | | | | | This simplified (basically duplicated) version of pb_cache_manager will allow removing some ugly hacks from radeon and amdgpu winsyses and flatten simplify their design. The difference is that winsyses must manually add buffers to the cache in "destroy" functions and the cache doesn't know about the buffers before that. The integration is therefore trivial and the impact on the winsys design is negligible. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Acked-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: implement fast stencil clearMarek Olšák2015-12-114-23/+53
| | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: re-enable Hyper-Z for stencilMarek Olšák2015-12-111-9/+3
| | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* r600g: remove a Hyper-Z workaround that's likely not needed anymoreMarek Olšák2015-12-111-19/+7
| | | | | | FORCE_OFF == 0, no need to set that Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* r600g: re-enable Hyper-Z for stencil on Evergreen & CaymanMarek Olšák2015-12-111-4/+1
| | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctlyMarek Olšák2015-12-113-5/+18
| | | | | | | | | | This is the recommended setting according to hw people and it makes Hyper-Z stable. Just the two magic states. This fixes Evergreen, Cayman, SI, CI, VI (using the Cayman code). Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: don't use the CP DMA workaround on Fiji and newerMarek Olšák2015-12-111-16/+20
| | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: apply the streamout workaround to Fiji as wellMarek Olšák2015-12-111-1/+3
| | | | | Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: also print hexadecimal values for register fields in the IB parserMarek Olšák2015-12-111-4/+7
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* radeonsi: implement RB+ for Stoney (v2)Marek Olšák2015-12-115-2/+170
| | | | | | v2: fix dual source blending Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* radeonsi: don't call of u_prims_for_vertices for patches and rectanglesMarek Olšák2015-12-111-1/+13
| | | | | | | | | Both caused a crash due to a division by zero in that function. This is an alternative fix. Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* radeonsi: use tgsi_shader_info::colors_writtenMarek Olšák2015-12-113-11/+1
| | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* r600g: write all MRTs only if there is exactly one output (fixes a hang)Marek Olšák2015-12-111-1/+2
| | | | | | | | This fixes a hang in piglit/arb_blend_func_extended-fbo-extended-blend-pattern_gles2 on REDWOOD. Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* tgsi/scan: add flag colors_writtenMarek Olšák2015-12-112-0/+4
| | | | | | | This is a prerequisite for the following r600g fix. Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* Revert "radeonsi: disable DCC on Stoney"Marek Olšák2015-12-111-4/+0
| | | | | | | | | | | This reverts commit 32f05fadbbdf2a3fb60055e610bbbdcd82dd3ce5. It turned out the problem with Stoney was caused by incorrect handling of a non-power-two VRAM size in the kernel driver. This is an optional BIOS setting and can be worked around by choosing a different VRAM size in the BIOS. Cc: 11.1 <mesa-stable@lists.freedesktop.org>
* nir: silence uninitialized warningTimothy Arceri2015-12-111-1/+1
| | | | Reviewed-by: Rob Clark <robdclark@gmail.com>
* mesa/shader: return correct attribute location for double matrix arraysDave Airlie2015-12-111-3/+8
| | | | | | | | | | | | | | | | | | | If we have a dmat2[4], then dmat2[0] is at 17, dmat2[1] at 19, dmat2[2] at 21 etc. The old code was returning 17,18,19. I think this code is also wrong for float matricies as well. There is now a piglit for the float case. This partly fixes: GL41-CTS.vertex_attrib_64bit.limits_test [airlied: update with Tapani suggestion to clean it up]. Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> Reviewed-by: Tapani Pälli <tapani.palli@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* draw: fix clipping with linear interpolated values and gl_ClipVertexRoland Scheidegger2015-12-111-4/+4
| | | | | | | | | | | | | | | | Discovered this when working on other clip code, apparently didn't work correctly - the combination of linear interpolated values and using gl_ClipVertex produced wrong values (failing all such combinations in piglits glsl-1.30 interpolation tests, named interpolation-noperspective-XXX-vertex). Use the pre-clip-pos values when determining the interpolation factor to fix this. Noone really understands this code well, but everybody agrees this looks sane... This fixes all those failing tests (10 in total) both with the llvm and non-llvm draw paths, with no piglit regressions. Reviewed-by: Brian Paul <brianp@vmware.com> Reviewed-by: Dave Airlie <airlied@redhat.com>
* r600: add missing return value check.Dave Airlie2015-12-111-0/+2
| | | | | | Pointed out by coverity scan. Signed-off-by: Dave Airlie <airlied@redhat.com>
* nir: Get rid of *_indirect variants of input/output load/store intrinsicsJason Ekstrand2015-12-1019-414/+391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is some special-casing needed in a competent back-end. However, they can do their special-casing easily enough based on whether or not the offset is a constant. In the mean time, having the *_indirect variants adds special cases a number of places where they don't need to be and, in general, only complicates things. To complicate matters, NIR had no way to convdert an indirect load/store to a direct one in the case that the indirect was a constant so we would still not really get what the back-ends wanted. The best solution seems to be to get rid of the *_indirect variants entirely. This commit is a bunch of different changes squashed together: - nir: Get rid of *_indirect variants of input/output load/store intrinsics - nir/glsl: Stop handling UBO/SSBO load/stores differently depending on indirect - nir/lower_io: Get rid of load/store_foo_indirect - i965/fs: Get rid of load/store_foo_indirect - i965/vec4: Get rid of load/store_foo_indirect - tgsi_to_nir: Get rid of load/store_foo_indirect - ir3/nir: Use the new unified io intrinsics - vc4: Do all uniform loads with byte offsets - vc4/nir: Use the new unified io intrinsics - vc4: Fix load_user_clip_plane crash - vc4: add missing src for store outputs - vc4: Fix state uniforms - nir/lower_clip: Update to the new load/store intrinsics - nir/lower_two_sided_color: Update to the new load intrinsic NIR and i965 changes are Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> NIR indirect declarations and vc4 changes are Reviewed-by: Eric Anholt <eric@anholt.net> ir3 changes are Reviewed-by: Rob Clark <robdclark@gmail.com> NIR changes are Acked-by: Rob Clark <robdclark@gmail.com>
* i965/fs_nir: Refactor store_output, load_input, and load_uniformJason Ekstrand2015-12-101-26/+19
| | | | | | | | There was way too much incrementing of things going on. Instead, let's just start everything off at the right base location, and then increment in the loop. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* gallium/util: return correct number of bound vertex buffersPatrick Rudolph2015-12-101-1/+7
| | | | | | | | | | | | | | | | | | | | In case a state tracker unbinds every slot by a seperate pipe->set_vertex_buffers() call, starting from slot zero, the number of bound buffers would not reach zero at all. The current algorithm does not account for pre-existing holes in the buffer list. Unbinding all buffers at once or starting at the top-most slot results in correct behaviour. Calculating the correct number of bound buffers fixes a NULL pointer dereference in nvc0_validate_vertex_buffers_shared(). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93004 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu> Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
* blit: Don't take into account the Mesa format when checking MSRT blitNeil Roberts2015-12-101-13/+15
| | | | | | | | | | | | | | | | | | | | | | According to the GLES3 spec, blitting between multisample FBOs with different internal formats should not be allowed. The compatible_resolve_formats function implements this check. Previously it had a shortcut where if the Mesa formats of the two renderbuffers were the same then it would assume the blit is ok. However some drivers map different internal formats to the same Mesa format, for example it might implement both GL_RGB and GL_RGBA textures with MESA_FORMAT_R8G8B8A_UNORM. The function is used to generate a GL error according to what the GL spec requires so the blit should not be allowed in that case. This patch just removes the shortcut so that it only ever looks at the internal format. Note that I posted a related patch to disable this check altogether for desktop GL. However this function is still used on GLES3 because there are conformance tests that require this behaviour so this patch is still useful. Cc: Marek Olšák <maraeo@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com>
* i965: Check base format to determine whether to use tiled memcpyNeil Roberts2015-12-102-6/+8
| | | | | | | | | | | | | The tiled memcpy doesn't work for copying from RGBX to RGBA because it doesn't override the alpha component to 1.0. Commit 2cebaac479d4 added a check to disable it for RGBX formats by looking at the TexFormat. However a lot of the rest of the code base is written with the assumption that an RGBA texture can be used internally to implement a GL_RGB texture. If that is done then this check breaks. This patch makes it instead check the base format of the texture which I think more directly matches the intention. Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
* i965/gen8: Allow rendering to B8G8R8X8Neil Roberts2015-12-101-4/+5
| | | | | | | | | Since Gen8 this is allowed as a rendering target so we don't need to override it to B8G8R8A8. This is helpful on Gen9+ where using this override causes fast clears not to work. Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com> Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965/gen9: Allow fast clear for MSRT formats matching renderNeil Roberts2015-12-101-4/+11
| | | | | | | | | | | | | | | | | Previously fast clear was disallowed on Gen9 for MSRTs with the claim that some formats don't work but we didn't understand why. On further investigation it seems the formats that don't work are the ones where the render surface format is being overriden to a different format than the one used for texturing. The one used for texturing is not actually a renderable format. It arguably makes sense that the sampler hardware doesn't handle the fast color correctly in these cases because it shouldn't be possible to end up with a fast cleared surface that is non-renderable. This patch changes the limitation to prevent fast clear for surfaces where the format for rendering is overriden. Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
* i965/gen9/fast-clear: Handle linear→SRGB conversionNeil Roberts2015-12-101-0/+11
| | | | | | | | | | | | | | | If GL_FRAMEBUFFER_SRGB is enabled when writing to an SRGB-capable framebuffer then the color will be converted from linear to SRGB before being written. There is no chance for the hardware to do this itself because it can't modify the clear color that is programmed in the surface state so it seems pretty clear that the driver should be handling this itself. Note that this wasn't a problem before Gen9 because previously we were only able to do fast clears to 0 or 1 and those values are the same in linear and SRGB space. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* docs: Add ARB_compute_shader to 11.2.0 release notesJordan Justen2015-12-091-0/+1
| | | | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
* docs: Mark ARB_compute_shader as done for i965Jordan Justen2015-12-091-2/+2
| | | | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
* i965: Enable ARB_compute_shader extension on supported hardwareJordan Justen2015-12-092-5/+8
| | | | | | | | | | | | | | | Enable ARB_compute_shader on gen7+, on hardware that supports the OpenGL 4.3 requirements of a local group size of 1024. With SIMD16 support, this is limited to Ivy Bridge and Haswell. Broadwell will work with a local group size up to 896 on SIMD16 meaning programs that use this size or lower should run when setting MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader. Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
* i965/nir: Implement shared variable atomic operationsJordan Justen2015-12-092-0/+60
| | | | | | | | | v3: * Update based on latest SSBO code (Iago) Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
generated by cgit v1.1 at 2024-12-26 13:04:28 +0000