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* glsl: Match unnamed record types across stages.Grigori Goronzy2014-01-211-0/+4
| | | | | | | | | | | | | | Unnamed record types are assigned to separate types per stage, e.g. if uniform struct { ... } a; is defined in both vertex and fragment shader, two separate types will result with different names. When linking the shader, this results in a type conflict. However, there is no reason why this should not be allowed according to GLSL specifications. Compare and match record types when linking shader stages to avoid this conflict. Reviewed-by: Matt Turner <mattst88@gmail.com>
* glsl: Extract function for record comparisons.Grigori Goronzy2014-01-212-30/+44
| | | | Reviewed-by: Matt Turner <mattst88@gmail.com>
* docs: remove some ancient README.* filesBrian Paul2014-01-214-617/+0
| | | | | | None of this info is relevant anymore. Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* svga: implement TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFSBrian Paul2014-01-214-8/+47
| | | | | | | | | | | | Fixes several colorbuffer tests, including piglit "fbo-drawbuffers-none" for "gl_FragColor" and "glDrawPixels" cases. v2: rework patch to only avoid creating extra shader variants when TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS is not specified. Per Jose. Use a write_color0_to_n_cbufs key field to replicate color0 to N color buffers only when N > 0 and WRITES_ALL_CBUFS is set. Reviewed-by: José Fonseca <jfonseca@vmware.com>
* svga: rename color output variablesBrian Paul2014-01-213-9/+10
| | | | | | Just to be bit more readable. Reviewed-by: José Fonseca <jfonseca@vmware.com>
* svga: fix clearing for null color buffersBrian Paul2014-01-211-3/+3
| | | | | | Fixes piglit "fbo-drawbuffers-none glClear" test. Reviewed-by: José Fonseca <jfonseca@vmware.com>
* mesa: add missing TYPE_DOUBLEN_2 cases in get.cBrian Paul2014-01-211-0/+12
| | | | | | | | | | | | The new TYPE_DOUBLEN_2 type was added in 0e60d850 but the code to return values of that type wasn't completed. Fixes conform's default state test. glGetFloatv(GL_DEPTH_RANGE) wasn't returning anything. v2: remove stray 'break' statements. Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
* i965: Modify some error messages to refer to "vec4" instead of "vs".Paul Berry2014-01-212-5/+5
| | | | | | | | | These messages are in code that is shared between the VS and GS back-ends, so use the terminology "vec4" to avoid confusion. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Add GS support to INTEL_DEBUG=shader_time.Paul Berry2014-01-218-10/+37
| | | | | | | Previously, time spent in geometry shaders would be counted as part of the vertex shader time. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* draw: fix points with negative w coords for d3d style point clippingRoland Scheidegger2014-01-211-2/+6
| | | | | | | | | | | | | Even with depth clipping disabled, vertices which have negative w coords must be discarded. And since we don't have a proper guardband implementation yet (relying on driver to handle all values except infs/nans in rasterization for such points) we need to kill them off manually (as they can end up with coordinates inside viewport otherwise). v2: use 0.0f instead of 0 (spotted by Brian). Reviewed-by: Jose Fonseca <jfonseca@vmware.com> Reviewed-by: Brian Paul <brianp@vmware.com>
* i965: Reserve space for "Vertex Count" in GS outputs.Kenneth Graunke2014-01-212-0/+13
| | | | | | | | v2: Also increment ir->offset in the GS visitor, rather than at the final assembly generation stage (requested by Paul). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Paul Berry <stereotype441@gmail.com>
* i965: Update blitter code for 48-bit addresses.Kenneth Graunke2014-01-201-16/+48
| | | | | | | v2: Rebase on Eric's SET_FIELD changes. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
* i965: Update PIPE_CONTROL packet lengths for Broadwell.Kenneth Graunke2014-01-201-2/+20
| | | | | | | | | On Broadwell, PIPE_CONTROL needs an extra DWord to accomodate the 48-bit addressing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Re-combine the Gen4-5 and Gen6+ write_depth_count functions.Kenneth Graunke2014-01-203-23/+10
| | | | | | | | | Now that we have a helper function that handles the PIPE_CONTROL variations between the various platforms, these are basically the same. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Create a helper function for emitting PIPE_CONTROL writes.Kenneth Graunke2014-01-204-93/+69
| | | | | | | | | | | | | | | | | | | There are a lot of places that use PIPE_CONTROL to write a value to a buffer (either an immediate write, TIMESTAMP, or PS_DEPTH_COUNT). Creating a single function to do this seems convenient. As part of this refactor, we now set the PPGTT/GTT selection bit correctly on Gen7+. Previously, we set bit 2 of DW2 on all platforms. This is correct for Sandybridge, but actually part of the address on Ivybridge and later! Broadwell will also increase the length of these packets by 1; with the refactoring, we should have to adjust that in substantially fewer places, giving us confidence that we've hit them all. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Use full-length PIPE_CONTROL packets for workaround writes.Kenneth Graunke2014-01-201-6/+9
| | | | | | | | | | | | | | | I believe that PIPE_CONTROL uses the length field to decide whether to do 32-bit or 64-bit writes. A length of 4 would do a 32-bit write, while a length of 5 would do a 64-bit write. (I haven't verified this, though.) For workaround writes, we don't care what value gets written, or how much data. We're only writing something because hardware bugs mandate that do so. So using a 64-bit write should be fine. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Emit full-length PIPE_CONTROLs for (non-write) flushes.Kenneth Graunke2014-01-201-2/+3
| | | | | | | | | | | | | | | | The PIPE_CONTROL packet actually has 5 DWords on Gen6+: 1. Header 2. Flags 3. Address 4. Immediate Data: Lower DWord 5. Immediate Data: Upper DWord We just never emitted the last one. While it appears to work, it's probably safer to emit the entire thing. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Matt Turner <mattst88@gmail.com>
* i965: Create a helper function for emitting PIPE_CONTROL flushes.Kenneth Graunke2014-01-204-86/+66
| | | | | | | | | | | | | | | These days, we need to emit PIPE_CONTROL flushes all over the place. Being able to do that via a single function call seems convenient. Broadwell will also increase the length of these packets by 1; with the refactoring, we should have to do this in substantially fewer places. v2: Add back forgotten intel_emit_post_sync_nonzero_flush (caught by Eric Anholt). Drop unlikely() from BLT_RING check. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Fix MI_STORE_REGISTER_MEM for Broadwell.Kenneth Graunke2014-01-201-10/+23
| | | | | | | It now takes a 48-bit address. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
* i965: Introduce an OUT_RELOC64 macro.Kenneth Graunke2014-01-202-0/+34
| | | | | | | | | Broadwell uses 48-bit addresses. The first DWord is the low 32 bits, and the second DWord is the high 16 bits. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i965: Use the new drm_intel_bo offset64 field.Kenneth Graunke2014-01-2012-30/+30
| | | | | | | | | | | | | | | | | | | libdrm 2.4.52 introduces a new 'uint64_t offset64' field, intended to replace the old 'unsigned long offset' field. To preserve ABI, libdrm continues to store the presumed offset in both locations. On Broadwell, a 64-bit kernel may place BOs at "high" (> 4G) addresses. However, with a 32-bit userspace, the 'unsigned long offset' field will only be 32-bit, which is not large enough to hold this value. We need to use a proper uint64_t (like the kernel does). Technically, a lot of this code doesn't affect Broadwell, so we could leave it using the old field. But it makes sense to just switch to the new, properly typed field. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* build: Require libdrm 2.4.52 for Intel.Kenneth Graunke2014-01-201-1/+1
| | | | Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Delete intel_batchbuffer_emit_reloc_fenced.Kenneth Graunke2014-01-202-30/+0
| | | | | | | | Nothing in i965 uses it. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* i915: Silence warning: unused parameter warning in intel_bufferobj_bufferIan Romanick2014-01-203-13/+5
| | | | | | | | | | | intel_buffer_objects.c: In function 'old_intel_bufferobj_buffer': intel_buffer_objects.c:471:17: warning: unused parameter 'flag' [-Wunused-parameter] The parameter hasn't been used since the i915 and i965 drivers had their breakup. i965 got the flags, and i915 got to cry itself to sleep. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i915: Ensure that intel_bufferobj_map_range meets alignment guaranteesIan Romanick2014-01-201-7/+21
| | | | | | | | | | | | Not actually tested, but the changes are identical to the i965 changes that are tested. v2: Remove MAX2(64, ...). Suggested by Ken (in the i965 version of this patch). Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Eric Anholt <eric@anholt.net> Cc: Siavash Eliasi <siavashserver@gmail.com>
* i965: Ensure that intel_bufferobj_map_range meets alignment guaranteesIan Romanick2014-01-201-7/+21
| | | | | | | | | | | | | | | | No piglit regressions on IVB. With minor tweaks to the arb_map_buffer_alignment-map-invalidate-range test (disable the extension check, set alignment to 64 instead of querying), the i965 driver would fail the test without this patch (as predicted by Eric). With this patch, it passes. v2: Remove MAX2(64, ...). Suggested by Ken. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net> Cc: Siavash Eliasi <siavashserver@gmail.com>
* docs: Note that GL_ARB_viewport_array is done on i965Ian Romanick2014-01-202-1/+2
| | | | | | | At least for GEN7+, anyway. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Enable ARB_viewport_arrayCourtney Goeltzenleuchter2014-01-202-0/+17
| | | | | | | | | | | | | v2 (idr): Only enable the extension on GEN7+ w/core profile because it requires geometry shaders. v3 (idr): Add some casting to fix setting of ViewportBounds.Min. Negating an unsigned value, then casting to float doesn't do what you might think it does. Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Consider all viewports before enabling guardband clippingIan Romanick2014-01-201-5/+9
| | | | | Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Consider only the scissor rectangle for viewport 0 for clearsIan Romanick2014-01-201-1/+1
| | | | | | | | | | | noop_scissor (correctly) only examines the scissor rectangle for viewport 0. Therefore, it should only be called when that scissor rectangle is enabled. v2: Remove spurious change to radeon code. Noticed by Ken. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Set all the supported scissor rectangles for GEN7Ian Romanick2014-01-201-27/+33
| | | | | | | | | Currently MaxViewports is still 1, so this won't affect any change. v2: Minor code reformatting suggested by Ken. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Refactor bounding-box calculation out of _mesa_update_draw_buffer_boundsIan Romanick2014-01-202-29/+61
| | | | | | | | | | | | Drivers that currently use _Xmin and friends to set their scissor rectangle will need to use this code directly once they are updated for GL_ARB_viewport_array. v2: Use different bit-test idiom and fix mixed tabs and spaces. Both were suggested by Ken. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Set all the supported viewports for GEN7Ian Romanick2014-01-203-37/+48
| | | | | | | Currently MaxViewports is still 1, so this won't affect any change. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Emit writes to viewport indexIan Romanick2014-01-202-3/+7
| | | | | | | This variable is handled in a fashion identical to gl_Layer. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* i965: Set the maximum VPIndexIan Romanick2014-01-203-1/+5
| | | | | | | | | | | | | At various stages the hardware clamps the gl_ViewportIndex to these values. Setting them to zero effectively makes gl_ViewportIndex be ignored. This is acutally useful in blorp (so that we don't have to modify all of the viewport / scissor state). v2: Use INTEL_MASK to create GEN6_CLIP_MAX_VP_INDEX_MASK. Suggested by Ken. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Add ARB_viewport_array plumbingCourtney Goeltzenleuchter2014-01-206-11/+99
| | | | | | | | | | | | | | | | Define API connections to extension entry points added in previous commits. Update entry points to use floating point arguments as required by the extension. Add get tokens for ARB_viewport_array state. v2: Include review feedback. v3 (idr): Fix 'make check'. Add missing Get infrastructure (some was culled from other pathces). Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* glsl: Add gl_ViewportIndex built-in variableCourtney Goeltzenleuchter2014-01-201-0/+2
| | | | | | | | v2 (idr): Fix copy-and-paste bug... s/LAYER/VIEWPORT/ Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* glsl: Add extension infrastructure for ARB_viewport_arrayIan Romanick2014-01-204-0/+7
| | | | | Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Add varying slot for viewport indexIan Romanick2014-01-202-4/+8
| | | | | Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Add new viewport and depth-range entry points for GL_ARB_viewport_arrayCourtney Goeltzenleuchter2014-01-202-0/+178
| | | | | | | | | | | | | | | | | | | v2 (idr): Use set_viewport_no_notify / set_depth_range_no_notify (and manually notify the driver) instead of calling _mesa_set_viewporti / _mesa_set_depthrangei. Refactor bodies of _mesa_ViewportIndexed and _mesa_ViewportIndexedv into a shared function. Remove spurious CLAMP calls in _mesa_DepthRangeArrayv and _mesa_DepthRangeIndexed. v3 (idr): Add some missing return-statements after calls to _mesa_error. v4 (idr): Only perform the ViewportBounds.Min / ViewportBounds.Max clamping in set_viewport_no_notify if GL_ARB_viewport_array is enabled. Otherwise the driver may not have set ViewportBounds, and the clamping will do bad things. Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Add new scissor entry points for GL_ARB_viewport_arrayCourtney Goeltzenleuchter2014-01-202-0/+101
| | | | | | | | | | | | | v2 (idr): Use set_scissor_no_notify (and manually notify the driver) instead of calling _mesa_set_scissori. Refactory bodies of _mesa_ScissorIndexed and _mesa_ScissorIndexedv into a shared function. Perform parameter validation in the same order in all three functions. Pull MaxViewports comparison fix (in _mesa_ScissorArrayv) from the next patch to this patch. Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Add custom get function for SCISSOR_TEST to _mesa_IsEnablediCourtney Goeltzenleuchter2014-01-201-0/+7
| | | | | | | | | Now that the scissor enable state is a bitfield need a custom function to extract the correct value from gl_context. Modeled Scissor.EnableFlags after Color.BlendEnabled. Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Add new get entrypoints for ARB_viewport_arrayCourtney Goeltzenleuchter2014-01-202-0/+195
| | | | | | | | | v2 (idr): Fix several "comparison between signed and unsigned integer expressions" warnings. Signed-off-by: Courtney Goeltzenleuchter <courtney@LunarG.com> Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Change parameter to _mesa_set_viewport to floatIan Romanick2014-01-202-8/+9
| | | | | | | | This matches the expectations of GL_ARB_viewport_array and the storage type where the values will land. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* meta: Restore all scissor stateIan Romanick2014-01-201-3/+11
| | | | | | | | | | Previously the restore code would enable all scissor rectangles if any scissor rectangles were enabled on entry to meta. When there is only one scissor rectangle, this is fine. As soon as a driver supports multiple viewports, this will be a problem. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Set all scissor rectsIan Romanick2014-01-202-4/+28
| | | | | | | | | | | In _mesa_Scissor, make sure that ctx->Driver.Scissor is only called once instead of once per scissor rectangle. v2: Use MAX_VIEWPORTS instead of ctx->Const.MaxViewports because the driver may not set ctx->Const.MaxViewports yet. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Set all viewports from _mesa_Viewport and _mesa_DepthRangeIan Romanick2014-01-201-2/+28
| | | | | | | | | | | | In _mesa_Viewport and _mesa_DepthRange, make sure that ctx->Driver.Viewport is only called once instead of once per viewport or depth range. v2: Make _mesa_DepthRange actually set all of the depth ranges (instead of just index 0). Noticed by Ken. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Restore all the viewports in _mesa_PopAttribIan Romanick2014-01-201-2/+7
| | | | | Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Restore all the scissor rectangles in _mesa_PopAttribIan Romanick2014-01-201-6/+10
| | | | | Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
* mesa: Initialize all the viewportsIan Romanick2014-01-203-26/+49
| | | | | | | | | | | | | v2: Use MAX_VIEWPORTS instead of ctx->Const.MaxViewports because the driver may not set ctx->Const.MaxViewports yet. v3: Handle all viewport entries in update_viewport_matrix and _mesa_copy_context too. This was previously in an earlier patch. Having the code in the earlier patch could cause _mesa_copy_context to access a matrix that hadn't been constructed. Signed-off-by: Ian Romanick <ian.d.romanick@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> [v2]
generated by cgit v1.1 at 2025-01-16 00:49:11 +0000